CN110020558A - A kind of safe crypto chip Testability Design structure under boundary scan design environment - Google Patents
A kind of safe crypto chip Testability Design structure under boundary scan design environment Download PDFInfo
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- CN110020558A CN110020558A CN201910278520.1A CN201910278520A CN110020558A CN 110020558 A CN110020558 A CN 110020558A CN 201910278520 A CN201910278520 A CN 201910278520A CN 110020558 A CN110020558 A CN 110020558A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0894—Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
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Abstract
The invention discloses the Testability Design structures for protecting AES crypto chip from scanning attack a kind of under boundary scan design environment.The Testability Design structure of the safety introduces the enabled logic of displacement, scan chain pattern switching reseting logic and Key-insulated logic on the basis of Conventional boundary scan design structure.Enabled logic is shifted for disabling scanning shifting function in the functional mode；Scan chain pattern switching reseting logic makes chip that primary reset operation be first carried out when being switched to test pattern from functional mode, to protect the confidential information being stored in scan chain；Key-insulated logic for being isolated encryption key in test mode, so that attacker be prevented to obtain key information in test mode.The present invention does not introduce new input, output signal, it is only necessary to which seldom hardware spending, can carry out automatic protection to chip can resist all potentially based on the side-channel attack of scanning under the premise of not losing circuit testability.
Description
Technical field
The invention belongs to chip secure fields, protect crypto chip from based on the non-of scanning more particularly, to a kind of
The safe Testability Design structure of Network Intrusion.
Background technique
With the development of the emerging technologies such as Internet of Things, big data, information security and privacy are become more and more important, and password is calculated
Method is widely applied.Since the data throughput that software realization provides is lower, and more computing resource is needed, password is calculated
Method is usually realized using hardware module.Encryption Algorithm is zero tolerance to failure, therefore encryption hardware needs to carry out strictly
Test.
Scan Design improves the controllability and observability of chip interior trigger, and the test of sequence circuit is converted
At the test of combinational circuit, great convenience is brought to integrated circuit testing, becomes industrially widely applied now and tests
Property designing technique.As shown in attached drawing 1 (a), as soon as by selected in input terminal addition 21 multiplexer, a trigger becomes
At inner scanning unit (internal scan cell, ISC).ISC is there are two optional input source: data input (DI) and
Scanning input (SI).DI is the input of former trigger, and SI is by the output driving of another ISC.Shift enable signal (Shift_
En selection DI or SI) is determined.ISC output is both data output (DO) and scanning output (SO).Further, since usual situation
The data channel of lower test equipment is limited, and carrying out test to a numerous chip of input/output (I/O) port number is
One huge challenge.Boundary scan design successfully solves this problem, it is equipped with a boundary for each chip I/O
Scanning element (boundary scan cell, BSC).One BSC is made of two d type flip flops and two multiplexers, such as
Shown in attached drawing 1 (b).BSC as input, input source DI are driven by chip input port (ChipIn), and it is corresponding that data export DO
(PI) is originally inputted in internal logic.As the BSC of output, input source DI is driven by the original output (PO) of internal logic,
Data export the output port (ChipOut) that DO corresponds to chip.The value of DO is traveled to by operating mode selection signal (Mode_
Sel it) determines.Internal scan chain (or boundary scan chain) is to connect and shape by by the SO of ISC (or BSC) with the SI of subsequent cell
At shift register.The SI of first scanning element in scan chain is connected to chip input pin, by last scanning element
SO be connected to chip output pin, so that it may from outside access scan chain.Work as Mode_sel=0, when Shift_en=0, core
Piece operates in functional mode.At this point, no matter BSC or ISC, DO directly drives by DI.As Mode_sel=0, chip fortune
In test mode, there are three phase of operation for the mode for row: displacement is updated and is captured.In shift phase, Shift_en=1 is moved
Bit clock pulse is inputted applied to the clock of each BSC and ISC, test vector is moved into scan chain by scanning displacement, simultaneously
Test is responded and removes scan chain.In the more new stage only for BSC, by providing clock to the UpdateClock of each BSC
The test data being stored in D1 (referred to as capture trigger) is transmitted to D2 (referred to as update trigger) by pulse.At this point, D2
State transfer has arrived the DO of BSC.In acquisition phase, Shift_en=0 applies one to the clock input of each BSC and ISC and catches
Clock pulses is obtained, in the D1 that the response at DI is captured to ISC or BSC.
On the one hand the interleave scan chain in crypto chip improves its testability, ensure that the test quality of chip；
On the other hand security risk also is brought to crypto chip.By means of scan chain, attacker can load in chip input terminal to be appointed
The plaintext of meaning, then in the intermediate state of the output end observation encryption of scan chain.Finally according to known-plaintext, corresponding intermediate shape
The knowledge of state and Encryption Algorithm carrys out breaking cryptographic keys.AES (Advanced Encryption Standard) is a kind of widely applied Encryption Algorithm, according to report
Road, AES chip are easy to be cracked by the attack based on scanning.It is an object of the invention to improve existing Testability Design knot
Structure is to protect AES chip from the side-channel attack based on scanning.
In existing patent, do not find and crypto chip Testability Design structure phase safe under boundary scan design environment
As patented invention.
Summary of the invention
For the defect of existing boundary scanning technique, the purpose of the present invention is to provide a kind of safe Scan Design sides
Case overcomes the side-channel attack based on scanning under the premise of not influencing circuit performance and test quality.
To achieve the above object, the present invention provides Testability Design sides safe under a kind of boundary scan design environment
Case.Compared with conventional Scan Design scheme, the safe Testability Design scheme of proposition increases scan chain reset mechanism, close
Key isolation mech isolation test and displacement enable mechanism.When chip is in test pattern (Mode_sel=1) and functional mode (Mode_sel=
0) when switching between, scan chain is resetted first, and the confidential information of storage is removed, so as to prevent based on pattern switching
Scanning attack.At test pattern (Mode_sel=1), key is isolated with encrypting module, is only relied upon so as to overcome
The scanning attack of test pattern.At functional mode (Mode_sel=0), shifting function is disabledSo as to
To defeat under functional mode illegally using the scanning attack for using shifting function.
Safe Testability Design structure of the invention is to joined displacement on the basis of Conventional boundary scan design to make
Energy logic, scan chain pattern switching reseting logic and Key-insulated logic, as shown in Fig. 2.Conventional scan chain is close taking turns
Other triggers in the wheel register and chip in cipher key register and wheel operating unit in key generator, which are transformed into, to be swept
Unit is retouched to be connected in series later.Here wheel operating unit and round key generator is the core component of AES encryption chip.This hair
The security control logical description that bright safe Testability Design introduces is as follows:
1. shifting enabled logic
Attacker illegally utilizes shifting function (Shift_en=1) at functional mode (Mode_sel=0) in order to prevent
Intermediate cryptographic is obtained as a result, the overall situation (system) shift control signal SHIFT_EN passes through one and controls each scanning list again behind the door
The enabled input Shift_en of the displacement of first (including boundary scan cell and conventional sweep unit).Another input with door is by work
Operation mode selection signal Mode_sel control, as shown in Fig. 3.It ensure that when Mode_sel is 0, each scanning element
0 can only be received by shifting enabled input port, i.e., disable shifting function in the functional mode.
2. scan chain pattern switching reseting logic
In traditional Scan Architecture, global (system) resets input (System_Reset) and drives each scanning element
Reset terminal (Reset), chip can be initialized as System_Reset=0, as shown in attached drawing 4 (a).In order in pattern switching
Shi Zhihang resets operation, and security sweep structure proposed by the present invention introduces scan chain reseting logic, including a d type flip flop,
One same or door and one and door, as shown in Fig. 4 (b).The d type flip flop of insertion stores the Mode_sel of a clock cycle
Value.If the Mode_sel of present clock period is identical as the Mode_sel value of a upper clock cycle, the output of same or door is
1.At this point, System_Reset determines the output with door, that is, determine the Reset value of each scanning element.On the contrary, if working as
When the Mode_sel value difference of the Mode_sel of preceding clock cycle and a upper clock cycle, same or door output is 0.At this point, not
What value pipe System_Reset takes, and the output with door is all 0, and controlled scanning element, which executes, resets operation, thus encryption information
It is removed.In addition, regardless of why same or door output is worth, the output with door also must be 0, therefore if System_Reset is 0
System-level reset operation can be executed normally.
3. Key-insulated logic
The typical structure of AES round key generation module is as shown in Fig. 5, it is by cipher key register and some combinational logic groups
At.Cipher key register is used to store and export the round key of generation.In original round key generation module, in cipher key register
The DI of each storage unit by 4 select 1 multiplexer receive four input signals: encryption key (userkey, that is, just
Beginning key), previous round key (roundkeyi-1, for decrypting), next round key (roundkeyi+1, for encrypting) and other
Input, such as attached drawing 6 (a).Encryption key loads in the incipient stage of encryption from nonvolatile storage, is to generate each wheel
The basis of key.Multiplexer currently needs to deposit there are two address input (in Fig. 6 (a) label be and A2) for selecting
The round key of storage.Assuming that { A1, A2 } be { 0,0 }, { 0,1 }, { 1,0 } and { 1,1 } when, respectively selection userkey,
roundkeyi-1、roundkeyi+1With other inputs.When encrypted circuit be powered after, { Mode_sel, Shift_en } be set as 0,
0 }, chip entered function mode.Firstly, { A1, A2 } is set as { 0,0 }, initial key is sent into cipher key register.With
In clock cycle afterwards, { A1, A2 } is set as { 1,0 }, key generator will generate and store next round key.When decryption,
{ A1, A2 } is set as { 0,1 }, generates in reverse order and stores round key.
Key-insulated logic is inserted in round key generation module.It is made by the address input of modification multiplexer
Initial key is disabled in test phase, as shown in attached drawing 6 (b).Mode_sel after several logic gates by assisting A1 and A2 to control
Multiplexer processed.When encrypted circuit entered function mode (Mode_sel=0), the logic gate of insertion does not work, i.e.,
{ A1, A2 } is constantly equal to { A1', A2'}.As Mode_sel=1, { A1, A2 } is corresponding for { 0,0 }, { 0,1 }, { 1,0 } and { 1,1 }
A1', A2'} are respectively { 1,1 }, { 0,1 }, { 1,0 } and { 1,1 }, that is,It means that testing
Initial key can not be transmitted in cipher key register under mode.It should be noted that if initial key is isolated,
roundkeyi-1And roundkeyi+1It is not real round key, they are unrelated with initial key, they are only dependent upon key and post
The test data of scanning element in storage.
Contemplated above technical scheme through the invention, compared with prior art, have it is below the utility model has the advantages that
1, all possible attack based on scanning under boundary scan design environment can be overcome, while having not been changed test stream
Journey, therefore there is no any influence to chip testing, allow to execute all types of tests, such as stuck-at fault test and time delay event
Barrier test etc..
2, safety test structure proposed by the present invention, does not increase additional input, output signal, does not need additional yet
Time is tested, automatic protection can be carried out to chip, and the influence to circuit design is smaller.
3, area overhead is low.The contemplated Testability Design structure of the present invention is on the basis of existing testability structure
A trigger and a small amount of logic gate are increased only, increased area overhead is low-down.
Detailed description of the invention
Fig. 1 is inner scanning unit and boundary scan cell structural schematic diagram.
Fig. 2 is safe Testability Design the general frame proposed by the present invention.
Fig. 3 is to shift enabled logical schematic.
Fig. 4 is the scan chain with reset function and the scan chain schematic diagram for increasing pattern switching reset function.
Fig. 5 is AES round key generation module.
Fig. 6 is the key deposit structure of former AES chip and the key deposit structure with isolation features.
Specific embodiment
Present invention will now be described in detail with reference to the accompanying drawings..
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
When using technical protection chip of the invention, chip design stage is needed to be inserted into above-mentioned security control logic.Insertion
After security control logic, the work of chip and testing process are as follows.
1. after the power-up if mode select signal and displacement enable signal { Mode_sel, SHIFT_EN } are both configured to 0
When, crypto chip operates in functional mode, and initial key can be loaded into cipher key register to execute encryption/decryption operation.
2. after the power-up if mode select signal and displacement enable signal { Mode_sel, SHIFT_EN } be set as 0,
When 1 }, the Shift_en input of each scanning element is still 0, and shifting function can not carry out, and crypto chip operates in function mould
Formula, initial key can be loaded into cipher key register to execute encryption/decryption operation.
3. once chip resets immediately Mode_sel becomes 1 from 0, i.e., the state of scanning element is reset.Resetting operation will
Delete the confidential information being stored in scan chain.Then, crypto chip works in test mode.Test pattern is operated by three
Phase (shifted phases, more new phase and acquisition phase) composition, and the rotation between these three phase of operation.SHIFT_EN signal is used
Rotation between control phase of operation.In shifted phases, SHIFT_EN=1, scanning element is in serial shift mode.At this time
Apply a certain number of Clock clock pulses in the clock input of each BSC and ISC, so that it may by scanning input pin
By test vector serial scan into scan chain, while the test of previous test vector is responded by scanning output pin and is moved
Out.Once test vector is completely scanned in scan chain, chip enters more new phase, and the UpdateClock of each BSC will be answered
With a clock pulses.In this more new phase, the test data being stored in D1 (capture trigger of BSC) is transported to
D2 (the update trigger of BSC), while test vector is applied to combinational logic by the DO of scanning element.Next, SHIFT_
EN becomes 0, and circuit enters the acquisition phase of a clock cycle.In this acquisition phase, test response is loaded by DI is swept
It retouches in chain.Initial key cannot load into when due to Mode_sel=0, in the sound of acquisition phase cipher key register capture
It should be unrelated with initial key.It ensure that the response removed from scan chain does not include confidential information.By again by SHIFT_
EN is set as " 1 ", and the test that had previously captured response will be removed from scan chain by scanning output end mouth, while by next survey
Examination vector is moved into scan chain.
4. crypto chip is worked at once in test pattern, test pattern after the power-up if Mode_sel is initially set to 1
It is made of shifted phases, more new phase and acquisition phase.Concrete operations process is similar to above-mentioned 3.
Crypto chip can be with free switching operating mode.Once receiving mode switch request, chip resets immediately.
Based on the detailed description of above-mentioned safe Testability Design scheme, working principle can be broadly described as follows: attack
The person of hitting cannot carry out shifting function in the functional mode, can not be removed by the way that chip is switched to test pattern from functional mode
The confidential information being stored in scan chain can not also obtain key information in test mode, therefore based on the non-intrusive of scanning
When attack be virtually impossible to complete.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include
Within protection scope of the present invention.
Claims (4)
1. a kind of safe crypto chip Testability Design structure under boundary scan design environment, which is characterized in that in routine
The enabled logic of displacement, scan chain pattern switching reseting logic and Key-insulated logic are introduced on the basis of boundary scan design.
Enabled logic is shifted for disabling scanning shifting function in the functional mode；Scan chain pattern switching reseting logic make chip from
Functional mode is first carried out primary reset and operates when being switched to test pattern, to protect the secret letter being stored in scan chain
Breath；Key-insulated logic for being isolated encryption key in test mode, so that it is close to prevent attacker from obtaining in test mode
Key information.
2. safe Testability Design structure according to claim 1, which is characterized in that shift enabled logic and selected by operating mode
Select signal control.If operating mode selection signal is " 0 " (functional mode), shifts enabled logic and scan chain is forbidden to execute displacement
Operation, chip can only operate in functional mode.If operating mode selection signal is " 1 " (test pattern), pass through setting at this time
Global (system) displacement enable signal can execute capture and scanning displacement.
3. safe Testability Design structure according to claim 1, which is characterized in that scan chain pattern switching reseting logic is deposited
It stores up the operating mode selection signal value of previous clock cycle and is compared with the operating mode selection signal value of current period,
If the two is different, the clear input of scanning element is assigned to virtual value, is executed primary reset and is operated, removes in scan chain
Information.When global (system) reset signal is virtual value, scan chain pattern switching reseting logic allows scan chain directly to reset,
To guarantee being normally carried out for system reset.If the operating mode selection signal value of former and later two clock cycle is identical and global
When (system) reset signal is invalid value, then reset operation is not carried out.
4. safe Testability Design structure according to claim 1, which is characterized in that Key-insulated logic is selected by operating mode
Select signal control.If operating mode selection signal is " 0 " (functional mode), Key-insulated logic allows chip normal load close
Key, that is, key is not isolated.If operating mode selection signal be " 1 " (test pattern), Key-insulated logic by key with
Chip isolation.Key-insulated logic is inserted in round key generation module, it is inputted by the address of modification multiplexer, with
Extremely low hardware spending be selected encryption key can not in test phase, to cannot be introduced into cipher key register.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111046444A (en) * | 2019-12-06 | 2020-04-21 | 合肥市卓怡恒通信息安全有限公司 | Storage encryption system based on domestic chip platform, mode switching method thereof and computer |
| WO2021049991A1 (en) * | 2019-09-12 | 2021-03-18 | Fingerprint Cards Ab | Biometric device with cryptographic circuitry |
| CN112684327A (en) * | 2020-11-30 | 2021-04-20 | 海光信息技术股份有限公司 | Scan chain and design method thereof and serial scan reset method based on scan chain |
| CN112910623A (en) * | 2019-11-19 | 2021-06-04 | 硅实验室公司 | Side channel attack mitigation for security devices with embedded sensors |
| WO2021224886A1 (en) * | 2020-05-07 | 2021-11-11 | Ozgur Sinanoglu | System, method, computer-accessible medium, and circuit for crippling the oracle in logic locking |
| CN113702816A (en) * | 2021-08-26 | 2021-11-26 | 中国电子科技集团公司第五十八研究所 | Boundary scanning-based register unit design method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030204801A1 (en) * | 2002-04-30 | 2003-10-30 | Motorola, Inc. | Method and apparatus for secure scan testing |
| US20040153801A1 (en) * | 2002-09-24 | 2004-08-05 | Yoshitaka Kayukawa | Semiconductor integrated circuit and method for testing same |
| CN101859267A (en) * | 2010-05-12 | 2010-10-13 | 宇龙计算机通信科技(深圳)有限公司 | Mainboard and test method capable of protecting chip on mainboard |
| CN103997402A (en) * | 2014-05-30 | 2014-08-20 | 中国科学院深圳先进技术研究院 | Encryption chip safety performance testing method and device |
| CN106707139A (en) * | 2017-01-03 | 2017-05-24 | 大唐微电子技术有限公司 | Scan chain test device and realizing method |
| CN108896903A (en) * | 2018-06-13 | 2018-11-27 | 天津大学 | The gradually verifying type security sweep chain apparatus and method of logic-based encryption |
| CN109188246A (en) * | 2018-09-06 | 2019-01-11 | 长沙理工大学 | A kind of safe encryption chip Testability Design structure |
-
2019
- 2019-04-09 CN CN201910278520.1A patent/CN110020558A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030204801A1 (en) * | 2002-04-30 | 2003-10-30 | Motorola, Inc. | Method and apparatus for secure scan testing |
| US20040153801A1 (en) * | 2002-09-24 | 2004-08-05 | Yoshitaka Kayukawa | Semiconductor integrated circuit and method for testing same |
| CN101859267A (en) * | 2010-05-12 | 2010-10-13 | 宇龙计算机通信科技(深圳)有限公司 | Mainboard and test method capable of protecting chip on mainboard |
| CN103997402A (en) * | 2014-05-30 | 2014-08-20 | 中国科学院深圳先进技术研究院 | Encryption chip safety performance testing method and device |
| CN106707139A (en) * | 2017-01-03 | 2017-05-24 | 大唐微电子技术有限公司 | Scan chain test device and realizing method |
| CN108896903A (en) * | 2018-06-13 | 2018-11-27 | 天津大学 | The gradually verifying type security sweep chain apparatus and method of logic-based encryption |
| CN109188246A (en) * | 2018-09-06 | 2019-01-11 | 长沙理工大学 | A kind of safe encryption chip Testability Design structure |
Non-Patent Citations (1)
| Title |
|---|
| 王伟征等: "A Low-Area Overhead Secure Scan Aichtecture Resisting Scan-Based Attacks for Crypto Chips", 《PROCEEDINGS OF THE INTERNATIONAL MULTICONFERENCE OF ENGINEERS AND COMPUTER SCIENTISTS》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021049991A1 (en) * | 2019-09-12 | 2021-03-18 | Fingerprint Cards Ab | Biometric device with cryptographic circuitry |
| US11997199B2 (en) | 2019-09-12 | 2024-05-28 | Fingerprint Cards Anacatum Ip Ab | Biometric device with cryptographic circuitry |
| CN112910623A (en) * | 2019-11-19 | 2021-06-04 | 硅实验室公司 | Side channel attack mitigation for security devices with embedded sensors |
| CN112910623B (en) * | 2019-11-19 | 2023-12-26 | 硅实验室公司 | Side channel attack mitigation for security devices with embedded sensors |
| CN111046444A (en) * | 2019-12-06 | 2020-04-21 | 合肥市卓怡恒通信息安全有限公司 | Storage encryption system based on domestic chip platform, mode switching method thereof and computer |
| WO2021224886A1 (en) * | 2020-05-07 | 2021-11-11 | Ozgur Sinanoglu | System, method, computer-accessible medium, and circuit for crippling the oracle in logic locking |
| CN112684327A (en) * | 2020-11-30 | 2021-04-20 | 海光信息技术股份有限公司 | Scan chain and design method thereof and serial scan reset method based on scan chain |
| CN112684327B (en) * | 2020-11-30 | 2023-09-05 | 海光信息技术股份有限公司 | Scan chain, design method thereof and serial scanning resetting method based on scan chain |
| CN113702816A (en) * | 2021-08-26 | 2021-11-26 | 中国电子科技集团公司第五十八研究所 | Boundary scanning-based register unit design method |
| CN113702816B (en) * | 2021-08-26 | 2024-05-10 | 中国电子科技集团公司第五十八研究所 | Register unit design method based on boundary scanning |
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