CN110010499A - A kind of radio frequency chip system in package technique with electro-magnetic screen function - Google Patents
A kind of radio frequency chip system in package technique with electro-magnetic screen function Download PDFInfo
- Publication number
- CN110010499A CN110010499A CN201811176851.6A CN201811176851A CN110010499A CN 110010499 A CN110010499 A CN 110010499A CN 201811176851 A CN201811176851 A CN 201811176851A CN 110010499 A CN110010499 A CN 110010499A
- Authority
- CN
- China
- Prior art keywords
- insulating layer
- copper
- rdl
- range
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 78
- 229910052802 copper Inorganic materials 0.000 claims abstract description 128
- 239000010949 copper Substances 0.000 claims abstract description 128
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 126
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 238000012545 processing Methods 0.000 claims abstract description 10
- 238000005538 encapsulation Methods 0.000 claims abstract description 7
- 238000012805 post-processing Methods 0.000 claims abstract description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 60
- 238000001259 photo etching Methods 0.000 claims description 57
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 239000002184 metal Substances 0.000 claims description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 48
- 229910052710 silicon Inorganic materials 0.000 claims description 48
- 239000010703 silicon Substances 0.000 claims description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 41
- 230000008569 process Effects 0.000 claims description 36
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 30
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 30
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 30
- 239000004411 aluminium Substances 0.000 claims description 30
- 229910052782 aluminium Inorganic materials 0.000 claims description 30
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 30
- 229910052759 nickel Inorganic materials 0.000 claims description 30
- 229910052709 silver Inorganic materials 0.000 claims description 30
- 239000004332 silver Substances 0.000 claims description 30
- 229910052718 tin Inorganic materials 0.000 claims description 30
- 239000011135 tin Substances 0.000 claims description 30
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 27
- 229910052737 gold Inorganic materials 0.000 claims description 27
- 239000010931 gold Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 20
- 238000001312 dry etching Methods 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 15
- 238000009713 electroplating Methods 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 claims description 15
- 229910052763 palladium Inorganic materials 0.000 claims description 15
- 229910052716 thallium Inorganic materials 0.000 claims description 15
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 15
- 238000000280 densification Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000005496 eutectics Effects 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 description 7
- 239000007769 metal material Substances 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 5
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The radio frequency chip system in package technique with electro-magnetic screen function that the invention discloses a kind of includes the following steps: 101) cover board processing step, 102) copper post processing step, 103) production cavities step, 104) pedestal processing step, 105) encapsulation step；The present invention is provided in the case where not increasing cost and area occupied, realizes a kind of radio frequency chip system in package technique with electro-magnetic screen function of the electro-magnetic screen function between radio frequency chip.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, it is related to a kind of radio frequency with electro-magnetic screen function
Chip system grade packaging technology.
Background technique
With being gradually reduced for chip size, traditional monolithic package technique is transitioned into from original insertion slot type
BGA, then finally arrive Fan-out to WLCSP, but with the proposition of system level function module, the mode of system in package again by
Gradually instead of past one chip, by carrier, the integrated chip of unlike material and different function to a lesser region,
The unit area occupied for reducing chip, shortens signal interconnection line, while being conducive to the assembling of product.
However for the communications industry, the radio frequency chip of high frequency is gradually instead of original low frequency products, such radio frequency
Between chip and radio frequency chip, between radio frequency chip and other function chip and radio frequency system grade module is with other radio frequency systems
Electromagnetic Interference problem between grade module is just increasingly taken seriously.
In order to cope with this problem, the increase of electro-magnetic screen layer is current mainstream means, and prevents Contamination of Electromagnetic Wave must
Must preventive means, general IC chip plastic body be it is nonconducting, to electromagnetic field almost without shielding action.It is more at present
It is that metallic shield is placed outside packaging body, this mode advantages of good shielding performance, but than great, area occupied is big, it is at high cost,
And it is not corrosion-resistant.
Summary of the invention
The present invention overcomes the deficiencies in the prior art, provides in the case where not increasing cost and area occupied, realize
A kind of radio frequency chip system in package technique with electro-magnetic screen function of electro-magnetic screen function between radio frequency chip.
Technical scheme is as follows:
A kind of radio frequency chip system in package technique with electro-magnetic screen function, includes cover board and pedestal in structure, specific to locate
Reason includes the following steps:
101) cover board processing step: the hole TSV is made in upper cover plate surface by photoetching, etching technics, TSV bore dia range exists
1um to 1000um, depth is in 10um to 1000um；Side's setting insulating layer, thickness of insulating layer range are arrived in 10nm on the cover board
Between 100um；Side's setting seed layer on the insulating layer, seed layer thickness range is in 1nm to 100um, and seed layer sheet is as being one
Layer or multilayered structure, it is one or more of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel that seed layer, which uses,；Pass through plating
Copper makes copper metal full of the hole TSV, and carries out densification at a temperature of 200 to 500 degree, and the copper of lid surface is made by CMP process
Removal, leaves behind and fills out copper；
Make whole face metal layer on the surface of cover board comprising production insulating layer, thickness of insulating layer range in 10nm to 1000um,
It is opened a window by photoetching, dry etch process, connects metal layer and one end of the copper post in the hole TSV；
102) copper post processing step: carrying out thinned in one end that the copper post of cover board is not exposed, and passes through grinding, wet etching and dry
The technique of method etching exposes the copper post other end, covers insulating layer on the copper post surface of exposing, thickness of insulating layer range is in 10nm
To 1000um, is opened a window by photoetching, etching technics in surface of insulating layer, expose copper post after windowing；
103) it makes cavities step: cavity being made by photoetching, dry etching on pedestal, cavity shape is cube, the ladder that falls
Shape, cylinder or hemispherical, size range are 10um to 10000um, and size includes cube, the length and width of inverted trapezoidal herein
High or cylindrical, hemispheric diameter, height；Insulating layer, thickness of insulating layer model are made in the one side of cover board setting cavity
It is trapped among between 10nm to 100um；Side's setting seed layer on the insulating layer, seed layer thickness range is in 1nm to 100um, seed layer
, as being one or more layers structure, it is one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or more that seed layer, which uses, for this
Kind；
Copper metal is set to cover cavity surface by electro-coppering, CMP process makes lid surface copper removal only remaining insulating layer, then passes through
Photoetching, dry etching remove copper post in the hole TSV and appear the insulating layer of part；There is the one side of cavity to pass through photoetching, electricity on the cover board
Depositing process makes RDL, bond wire, and pad height range is made to reach 10nm to 1000um, and bond wire uses copper, aluminium, nickel,
Silver, gold, one or more of tin, bond wire structure are one or more layers, and thickness range is 10nm to 1000um；
104) pedestal processing step: the hole TSV is made on upper bed-plate surface by photoetching, etching technics, TSV bore dia range exists
1um to 1000um, depth is in 10um to 1000um；Insulating layer is set above pedestal, and thickness of insulating layer range is arrived in 10nm
Between 100um；Side's setting seed layer on the insulating layer, seed layer thickness range is in 1nm to 100um, and seed layer sheet is as being one
Layer or multilayered structure, it is one or more of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel that seed layer, which uses,；Pass through plating
Copper makes copper metal full of the hole TSV, and carries out densification at a temperature of 200 to 500 degree, and the copper of lid surface is made by CMP process
Removal, leaves behind and fills out copper；
Susceptor surface makes RDL, and process includes production insulating layer, and thickness of insulating layer range is used in 10nm to 1000um
Silica or silicon nitride；It is opened a window by photoetching, dry etch process, connects the copper post one end in the hole RDL with TSV of pedestal；
Its pad and RDL are located at the same face, that is, are located at one end that the copper post in the hole TSV is exposed；Pedestal without metal carry out on one side it is thinned, lead to
The technique for crossing grinding, wet etching and dry etching exposes the copper post other end；Insulating layer is covered on the copper post surface of exposing, absolutely
Edge layer thickness range opens a window in 10nm to 1000um, by photoetching, etching technics in surface of insulating layer, reveals copper post after windowing
Out；And RDL is made on the surface of pedestal；
105) encapsulation step: being placed in functional chip by way of eutectic bonding on the pad of pedestal, will by routing technique
The PAD of functional chip is with the pad connection of pedestal, and wherein functional chip thickness is between 50um to 600um；Pass through wafer key again
The mode of conjunction is bonded together cover board and pedestal, and cutting obtains final mould group；Wherein bonding temperature range is 200 to 500
Degree.
Further, above step 101) cover board by cvd silicon oxide perhaps silicon nitride as insulating layer or direct
Thermal oxide forms insulating layer.
Further, the metal layer of step 101) cover board includes RDL, and RDL is not connected to copper post top.
Further, photoetching, electroplating technology production RDL include production insulating layer, thickness of insulating layer range in step 103)
In 10nm to 1000um, material prestige silica or silicon nitride；RDL, RDL are made in silicon chip surface by photoetching, plating again
Including cabling and bonding.
Further, insulating layer is covered on the surface RDL, open a window exposed pad on the insulating layer, and the metal of RDL uses copper,
Aluminium, nickel, silver, gold, tin is one such or several, this body structure of RDL is one or more layers, and thickness range arrives for 10nm
1000um；Pad windowing 10um to 10000um diameter.
Advantage is the present invention compared with prior art: the present invention utilizes silicon cavity structure, does metal layer in silicon cavity inside,
The closed environment with complete metal cover is formed by wafer bonding, makes single electromagnetic shielding environment for radio frequency chip,
In the case where not increasing cost and area occupied, between realizing radio frequency chip, radio frequency chip and functional chip and system-level mould
Block is with the electromagnetic shielding between other modules.
Detailed description of the invention
Fig. 1 is the structure chart that cover board of the invention makes the hole TSV；
Fig. 2 is the copper post processing of cover board of the invention and the structure chart of production cavity；
Fig. 3 is the structure chart that pedestal of the invention is handled；
Fig. 4 is the structure chart after encapsulation of the invention；
Fig. 5 is the structure chart of cover board of the invention；
Fig. 6 is the structure chart of pedestal preliminary treatment of the invention；
Fig. 7 is the structure chart of the pedestal for installing functional chip of the invention；
Fig. 8 is the structure chart after another encapsulation of the invention.
It is identified in figure: cover board 101, the hole cover board TSV 102, pedestal 201, the hole pedestal TSV 202, functional chip 203.
Specific embodiment
Embodiments of the present invention are described below in detail, in which the same or similar labels are throughly indicated identical or classes
As element or the element of similar functions.It is exemplary below with reference to the embodiment of attached drawing description, is only used for explaining
The present invention and cannot function as limitation of the present invention.
Those skilled in the art can understand that unless otherwise defined, all terms used herein (including skill
Art term and scientific and technical terminology) there is meaning identical with the general understanding of those of ordinary skill in fields of the present invention.Also
It should be understood that those terms such as defined in the general dictionary should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless definition as here, will not be explained in an idealized or overly formal meaning.
The label about step mentioned in each embodiment, it is only for the convenience of description, without substantial
The connection of sequencing.Different step in each specific embodiment can carry out the combination of different sequencings, realize this hair
Bright goal of the invention.
The present invention is further described with reference to the accompanying drawings and detailed description.
Embodiment 1:
As shown in Figures 1 to 8, a kind of radio frequency chip system in package technique with electro-magnetic screen function includes lid in structure
Plate 101 and pedestal 201, specific processing include the following steps:
101) hole cover board TSV 102, cover board 101 processing step of cover board: are made on 101 surface of upper cover plate by photoetching, etching technics
102 diameter range of the hole TSV is in 1um to 1000um, and depth is in 10um to 1000um；Insulating layer is set above cover board 101, is insulated
Layer thickness range is between 10nm to 100um；By cvd silicon oxide or silicon nitride as insulating layer above cover board 101, or
Person's directly thermal oxidation forms insulating layer.Side's setting seed layer on the insulating layer, seed layer thickness range is in 1nm to 100um, seed
For layer originally as being one or more layers structure, it is one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or more that seed layer, which uses,
Kind；By electro-coppering, make copper metal full of the hole cover board TSV 102, and carry out densification at a temperature of 200 to 500 degree, passes through CMP
Technique removes the copper on 101 surface of cover board, leaves behind and fills out copper；
Whole face metal layer is made on the surface of cover board 101 comprising production insulating layer, thickness of insulating layer range are arrived in 10nm
1000um is opened a window by photoetching, dry etch process, connects metal layer and one end of the copper post in the hole cover board TSV 102；Lid
The metal layer of plate 101 includes RDL, and RDL is not connected to copper post top.
Specific as shown in Figure 1, passing through photoetching, etching technics makes the hole cover board TSV 102 in 101 silicon chip surface of upper cover plate, covers
102 diameter range of the hole plate TSV is in 1um to 1000um, and depth is in 10um to 1000um；In silicon wafer disposed thereon silica or nitrogen
The insulating layers such as SiClx or directly thermal oxidation, thickness of insulating layer range is between 10nm to 100um；Pass through physical sputtering, magnetic control
Sputtering or evaporation process just make seed layer on the insulating layer, and seed layer thickness range can be one in 1nm to 100um
Layer is also possible to multilayer, and metal material can be titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel etc.；
By electro-coppering, copper metal is set to be full of TSV, densification keeps copper finer and close at a temperature of 200 to 500 degree；Copper CMP technique makes silicon wafer
Copper removal in surface makes silicon chip surface only be left to fill out copper；Silicon chip surface insulating layer can use dry etching or wet corrosion technique
Removal；Silicon chip surface insulating layer can also retain；
Whole face metal layer (this metal layer may include RDL) is made on the surface of silicon wafer, process includes production insulating layer, insulation
For layer thickness range in 10nm to 1000um, material can be silica or silicon nitride；By photoetching, dry etch process is opened
Window connects metal layer with TSV copper column one end；
By photoetching, electroplating technology makes the RDL of whole face metal layer or special graph in silicon chip surface；RDL can also be with copper
Top end is not connected to；
102) copper post processing step: carried out in one end that the copper post of cover board 101 is not exposed it is thinned, pass through grinding, wet etching
Expose the copper post other end with the technique of dry etching, covers insulating layer on the copper post surface of exposing, thickness of insulating layer range exists
10nm to 1000um, material can be silica or silicon nitride；It is opened a window by photoetching, etching technics in surface of insulating layer,
Expose copper post after windowing；
103) it makes cavities step: cavity being made by photoetching, dry etching on cover board 101, cavity shape is cube, falls
Trapezoidal, cylindrical or hemispherical, size range are 10um to 10000um, and size includes cube, the length of inverted trapezoidal herein
Wide high or cylindrical, hemispheric diameter, height；Insulating layer, insulating layer thickness are made in the one side that cavity is arranged in cover board 101
Range is spent between 10nm to 100um；Side's setting seed layer on the insulating layer, seed layer thickness range is in 1nm to 100um, kind
Sublayer sheet as being one or more layers structure, seed layer using be one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or
It is a variety of；
Copper metal is set to cover cavity surface by electro-coppering, CMP process makes 101 surface copper of cover board removal only remaining insulating layer, then
By photoetching, dry etching, removes copper post in the hole cover board TSV 102 and appear the insulating layer of part；There is cavity on cover board 101
RDL, bond wire are made by photoetching, electroplating technology on one side, pad height range is made to reach 10nm to 1000um, bond wire
Using copper, aluminium, nickel, silver, gold, one or more of tin, bond wire structure is one or more layers, thickness range 10nm
To 1000um；Wherein RDL includes production insulating layer, thickness of insulating layer range in 10nm to 1000um, material prestige silica or
Person's silicon nitride；RDL is made in silicon chip surface by photoetching, plating again, RDL includes cabling and bonding.It covers and insulate on the surface RDL
Layer, open a window exposed pad on the insulating layer, and the metal of RDL uses copper, and aluminium, nickel, silver, gold, tin is one such or several, RDL
This body structure is one or more layers, and thickness range is 10nm to 1000um；Pad windowing 10um to 10000um diameter.
Particularly pass through photoetching and be dry-etched on wafer and make cavity, cavity can be cube, inverted trapezoidal
It can be cylindrical or hemispherical；Its size range is between 10um to 10000um, and size includes cube herein, terraced
The length, width and height or cylinder of shape, hemispheric diameter or height；In the face cvd silicon oxide or silicon nitride etc. for having cavity
Insulating layer or directly thermal oxidation, thickness of insulating layer range is between 10nm to 100um；By physical sputtering, magnetron sputtering or
Person's evaporation process just makes seed layer on the insulating layer, and for seed layer thickness range in 1nm to 100um, can be one layer can also
To be multilayer, metal material can be titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel etc.；
By electro-coppering, copper metal is made to cover cavity surface, copper CMP technique removes silicon chip surface copper, remains silicon chip surface only
Lower insulating layer；Photoetching, etching remove TSV copper column and appear the insulating layer of part, can use dry etching or wet corrosion technique
Removal；RDL is made by photoetching and electroplating technology in the one side for having cavity, process includes production insulating layer, thickness of insulating layer
For range in 10nm to 1000um, material can be silica or silicon nitride；By photoetching, electroplating technology is in silicon chip surface system
Make RDL；RDL includes cabling and key function；
Specifically, can also cover insulating layer on the surface RDL, open a window exposed pad on the insulating layer；RDL metal can be herein
Copper, aluminium, nickel, silver, gold, the materials such as tin can be one layer and are also possible to multilayer, and thickness range is 10nm to 1000um；Pad
Open a window 10um to 10000um diameter；
Insulating layer can not also be covered on cavity surface metal, directly by photoetching, electroplating technology makes RDL in silicon chip surface
Or bonding welding pad；
Furthermore bond wire is made in silicon chip surface by photoetching, electroplating technology, pad height range is in 10nm to 1000um, gold
Category can be copper, and aluminium, nickel, silver is golden, and the materials such as tin can be one layer and be also possible to multilayer, and thickness range arrives for 10nm
1000um；
104) hole pedestal TSV 202, pedestal 201 processing step of pedestal: are made on 201 surface of upper bed-plate by photoetching, etching technics
202 diameter range of the hole TSV is in 1um to 1000um, and depth is in 10um to 1000um；Insulating layer is set above pedestal 201, is insulated
Layer thickness range is between 10nm to 100um；Side's setting seed layer, seed layer thickness range are arrived in 1nm on the insulating layer
100um, seed layer sheet as being one or more layers structure, seed layer using be titanium, copper, aluminium, silver, palladium, gold, thallium, tin, in nickel
It is one or more kinds of；By electro-coppering, make copper metal full of the hole pedestal TSV 202, and carries out at a temperature of 200 to 500 degree close
Change, removes the copper on 201 surface of pedestal by CMP process, leave behind and fill out copper；
201 surface of pedestal makes RDL, and process includes production insulating layer, and thickness of insulating layer range is adopted in 10nm to 1000um
With silica or silicon nitride；It is opened a window by photoetching, dry etch process, makes the copper in the hole RDL and pedestal TSV 202 of pedestal 201
The connection of column one end；Its pad and RDL are located at the same face, that is, are located at one end that the copper post in the hole pedestal TSV 202 is exposed；201 nothing of pedestal
Carrying out on one side for metal is thinned, exposes the copper post other end by the technique of grinding, wet etching and dry etching；In exposing
Copper post surface covers insulating layer, and thickness of insulating layer range is in 10nm to 1000um, by photoetching, etching technics in surface of insulating layer
Windowing, exposes copper post after windowing；And RDL is made on the surface of pedestal 201；Insulating layer is covered on the surface RDL, on the insulating layer
Open a window exposed pad, and the metal of RDL uses copper, and aluminium, nickel, silver, gold, tin is one such or several, this body structure of RDL is one layer
Or multilayer, thickness range are 10nm to 1000um；Pad windowing 10um to 10000um diameter.
Specifically as shown in figure 3, by photoetching, etching technics makes the hole pedestal TSV 202, pedestal in 201 silicon chip surface of pedestal
202 diameter range of the hole TSV is in 1um to 1000um, and depth is in 10um to 1000um；In silicon wafer disposed thereon silica or nitridation
The insulating layers such as silicon or directly thermal oxidation, thickness of insulating layer range is between 10nm to 100um；By physical sputtering, magnetic control splashes
It penetrates or evaporation process just makes seed layer on the insulating layer, seed layer thickness range can be one layer in 1nm to 100um
It is also possible to multilayer, metal material can be titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel etc.；
By electro-coppering, densification keeps copper finer and close at a temperature of spending copper metal full of the hole pedestal TSV 202,200 to 500；Copper CMP
Technique removes silicon chip surface copper, and silicon chip surface is made only to be left to fill out copper；Silicon chip surface insulating layer can use dry etching or wet
The removal of method etching process；Silicon chip surface insulating layer can also retain；
RDL is made on the surface of 201 silicon wafer of pedestal, process is as described above, include production insulating layer, thickness of insulating layer range
In 10nm to 1000um, material can be silica or silicon nitride；By photoetching, dry etch process windowing, make RDL and
The connection of TSV copper column one end；By photoetching, electroplating technology makes RDL in silicon chip surface；RDL includes cabling and key function；
Specific its can also cover insulating layer on the surface RDL, and open a window exposed pad on the insulating layer；RDL metal can be with herein
It is copper, aluminium, nickel, silver is golden, the materials such as tin, can be one layer and is also possible to multilayer, thickness range is 10nm to 1000um；Weldering
Disk windowing 10um to 10000um diameter；
By photoetching, electroplating technology makes bond wire in silicon chip surface, and pad height range can in 10nm to 1000um, metal
To be copper, aluminium, nickel, silver is golden, the materials such as tin, can be one layer and is also possible to multilayer, thickness range is 10nm to 1000um；
Pad and RDL are one sides herein, positioned at one end that TSV copper column is exposed；
To 201 wafer of pedestal do not make smithcraft carry out on one side it is thinned, by grinding, wet etching and dry etching
Technique exposes the copper post other end；Cover insulating layer on the copper post surface of exposing, thickness of insulating layer range in 10nm to 1000um,
Its material can be silica or silicon nitride；By photoetching, etching technics opens a window in surface of insulating layer, reveals copper post after windowing
Out；
RDL is made on the surface of 201 silicon wafer of pedestal, process includes production insulating layer, and thickness of insulating layer range is arrived in 10nm
1000um, material can be silica or silicon nitride；By photoetching, electroplating technology makes RDL in silicon chip surface；RDL packet
Include cabling and key function；
Insulating layer can also be covered on the surface RDL, open a window exposed pad on the insulating layer；RDL metal can be copper herein, aluminium,
Nickel, silver, gold, the materials such as tin can be one layer and are also possible to multilayer, and thickness range is 10nm to 1000um；Pad windowing
10um to 10000um diameter；
By photoetching, electroplating technology makes bond wire in silicon chip surface, and pad height range can in 10nm to 1000um, metal
To be copper, aluminium, nickel, silver is golden, the materials such as tin, can be one layer and is also possible to multilayer, thickness range is 10nm to 1000um；
105) encapsulation step: functional chip 203 is placed on the pad of pedestal 201 by way of eutectic bonding, passes through routing
Technique by the PAD of functional chip 203 with the pad connection of pedestal 201, wherein 203 thickness of functional chip 50um to 600um it
Between；Cover board 101 and pedestal 201 are bonded together by way of wafer bonding again, cutting obtains final mould group；Wherein key
Temperature range is closed in 200 to 500 degree.I.e. as shown in figure 4,101 wafer of cover board is passed through pad gold by the technique by wafer bonding
Belong to melting bonding to cover on 201 wafer of pedestal, bonding temperature range is in 200 to 500 degree herein；Bonded wafer is cut into single envelope
Assembling structure is placed on the protrusion conductive column of substrate or pcb board by way of welding and completes the radio frequency chip of electro-magnetic screen function
The connection of system-in-package structure；Bonded wafer is cut into single encapsulation module.
Embodiment 2 is the specific embodiment in another structure, is specifically comprised the following steps:
Specific embodiment 2 includes:
201) upper cover plate 101 with cavity structure and pad is made；
As shown in figure 5, etching technics insulate in 101 silicon chip surface cvd silicon oxide of upper cover plate or silicon nitride etc. by photoetching
Layer or directly thermal oxidation, thickness of insulating layer range is between 10nm to 100um；By physical sputtering, magnetron sputtering or steaming
Depositing process just makes seed layer on the insulating layer, and seed layer thickness range can be one layer and be also possible in 1nm to 100um
Multilayer, metal material can be titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel etc.；
Pad is made in crystal column surface by photoetching and electroplating technology, then pass through photoetching and is dry-etched in production on wafer is empty
Chamber, cavity can be cube, and inverted trapezoidal is also possible to cylindrical or hemispherical；Its size range is in 10um to 10000um
Between, size includes cube, the length, width and height or cylinder of inverted trapezoidal, hemispheric diameter or height herein；
It can also be in the face cvd silicon oxide for having the cavity perhaps insulating layers such as silicon nitride or directly thermal oxidation, insulating layer thickness
Range is spent between 10nm to 100um；Photoetching, etching, removes the insulating layer of pad portion, can use dry etching or wet process
Etching process removal；
B: groove, TSV and RDL structure are made on 201 wafer of pedestal；
As shown in fig. 6, producing groove by the method for dry etching in 201 silicon chip surface of pedestal, groove can be cube,
Inverted trapezoidal is also possible to cylindrical or hemispherical；Its size range is between 10um to 10000um, and size includes cube herein
Shape, the length, width and height or cylinder of inverted trapezoidal, hemispheric diameter or height；The silicon wafer of this step includes 4,6,8,12 cun of crystalline substances
Circle, thickness range are 200um to 2000um, are also possible to other materials, including glass, quartz, silicon carbide, and aluminium oxide etc. is inorganic
Material, is also possible to epoxy resin, the organic materials such as polyurethane, and major function is to provide supporting role.
In silicon wafer disposed thereon the silica perhaps insulating layers such as silicon nitride or directly thermal oxidation, thickness of insulating layer range
Between 10nm to 100um；By physical sputtering, magnetron sputtering or evaporation process just make seed layer on the insulating layer, kind
Molecular layers thick range can be one layer and be also possible to multilayer in 1nm to 100um, metal material can be titanium, copper, aluminium, silver,
Palladium, gold, thallium, tin, nickel etc.；
Electro-coppering makes groove surfaces be paved with copper metal layer, and for thickness degree between 100nm to 100um, copper CMP technique makes silicon wafer table
Copper removal in face makes silicon chip surface only be left to fill out copper；Silicon chip surface insulating layer can be gone with dry etching or wet corrosion technique
It removes；Silicon chip surface insulating layer can also retain；
By photoetching, etching technics makes the hole TSV in silicon chip surface, and bore dia range is arrived in 1um to 1000um, depth in 10um
1000um；In the insulating layers such as silicon wafer disposed thereon silica or silicon nitride, thickness of insulating layer range 10nm to 100um it
Between；By physical sputtering, magnetron sputtering or evaporation process just make seed layer on the insulating layer, and seed layer thickness range exists
1nm to 100um can be one layer and be also possible to multilayer, and metal material can be titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel
Deng；
Electro-coppering makes copper metal be full of TSV, and densification keeps copper finer and close at a temperature of 200 to 500 degree；Copper CMP technique makes silicon chip surface
Copper removal makes silicon chip surface only be left to fill out copper；Silicon chip surface insulating layer can be removed with dry etching or wet corrosion technique；
Silicon chip surface insulating layer can also retain；
Make RDL on the surface of silicon wafer, process includes production insulating layer, thickness of insulating layer range in 10nm to 1000um,
Material can be silica or silicon nitride；By photoetching, dry etch process windowing connects RDL with TSV copper column one end；
By photoetching, electroplating technology makes RDL in silicon chip surface；RDL includes cabling and key function；RDL may include heat radiating metal
Block will be again by being sputtered if metal block thickness requirement is special by seed layer, and photoetching is electroplated and goes the works such as seed layer
Skill makes heat radiating metal block, and heat radiating metal is connected with TSV copper column one end fastly；
Insulating layer can also be covered on the surface RDL, open a window exposed pad on the insulating layer；RDL metal can be copper herein, aluminium,
Nickel, silver, gold, the materials such as tin can be one layer and are also possible to multilayer, and thickness range is 10nm to 1000um；Pad windowing
10um to 10000um diameter；
By photoetching, electroplating technology makes bond wire in silicon chip surface, and pad height range can in 10nm to 1000um, metal
To be copper, aluminium, nickel, silver is golden, the materials such as tin, can be one layer and is also possible to multilayer, thickness range is 10nm to 1000um；
The two sides that is also possible to that pad can be one side herein has, and RDL can be one side, and being also possible to two sides has；
Structure can first do groove herein, can also finish TSV, do groove after RDL again.
C: being placed in functional chip 203 in the groove of 201 wafer of pedestal, keeps chip and pedestal 201 brilliant by routing technique
Round pad connection；Make cover wafer together with 201 wafer bonding of pedestal with the technique that wafer scale is bonded, cutting obtains single
Mould group.
As shown in fig. 7, functional chip 203 is welded on 201 wafer of pedestal, routing draws signal；As shown in figure 8, logical
The technique for crossing wafer bonding is covered wafer 101 on 201 wafer of pedestal by pad metal melting bonding, herein bonding temperature model
It is trapped among 200 to 500 degree；Bonded wafer is cut into single package structure, the protrusion of substrate or pcb board is placed in by way of welding
The connection of the closed radio frequency chip encapsulating structure of side heat radiating type is completed on conductive column；
The above is only a preferred embodiment of the present invention, it is noted that for those skilled in the art,
Under the premise of not departing from present inventive concept, several improvements and modifications can also be made, these improvements and modifications also should be regarded as this hair
In bright protection scope.
Claims (5)
1. a kind of radio frequency chip system in package technique with electro-magnetic screen function, which is characterized in that include cover board in structure
And pedestal, specific processing include the following steps:
101) cover board processing step: the hole TSV is made in upper cover plate surface by photoetching, etching technics, TSV bore dia range exists
1um to 1000um, depth is in 10um to 1000um；Side's setting insulating layer, thickness of insulating layer range are arrived in 10nm on the cover board
Between 100um；Side's setting seed layer on the insulating layer, seed layer thickness range is in 1nm to 100um, and seed layer sheet is as being one
Layer or multilayered structure, it is one or more of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel that seed layer, which uses,；Pass through plating
Copper makes copper metal full of the hole TSV, and carries out densification at a temperature of 200 to 500 degree, and the copper of lid surface is made by CMP process
Removal, leaves behind and fills out copper；
Make whole face metal layer on the surface of cover board comprising production insulating layer, thickness of insulating layer range in 10nm to 1000um,
It is opened a window by photoetching, dry etch process, connects metal layer and one end of the copper post in the hole TSV；
102) copper post processing step: carrying out thinned in one end that the copper post of cover board is not exposed, and passes through grinding, wet etching and dry
The technique of method etching exposes the copper post other end, covers insulating layer on the copper post surface of exposing, thickness of insulating layer range is in 10nm
To 1000um, is opened a window by photoetching, etching technics in surface of insulating layer, expose copper post after windowing；
103) it makes cavities step: cavity being made by photoetching, dry etching on pedestal, cavity shape is cube, the ladder that falls
Shape, cylinder or hemispherical, size range are 10um to 10000um, and size includes cube, the length and width of inverted trapezoidal herein
High or cylindrical, hemispheric diameter, height；Insulating layer, thickness of insulating layer model are made in the one side of cover board setting cavity
It is trapped among between 10nm to 100um；Side's setting seed layer on the insulating layer, seed layer thickness range is in 1nm to 100um, seed layer
, as being one or more layers structure, it is one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or more that seed layer, which uses, for this
Kind；
Copper metal is set to cover cavity surface by electro-coppering, CMP process makes lid surface copper removal only remaining insulating layer, then passes through
Photoetching, dry etching remove copper post in the hole TSV and appear the insulating layer of part；There is the one side of cavity to pass through photoetching, electricity on the cover board
Depositing process makes RDL, bond wire, and pad height range is made to reach 10nm to 1000um, and bond wire uses copper, aluminium, nickel,
Silver, gold, one or more of tin, bond wire structure are one or more layers, and thickness range is 10nm to 1000um；
104) pedestal processing step: the hole TSV is made on upper bed-plate surface by photoetching, etching technics, TSV bore dia range exists
1um to 1000um, depth is in 10um to 1000um；Insulating layer is set above pedestal, and thickness of insulating layer range is arrived in 10nm
Between 100um；Side's setting seed layer on the insulating layer, seed layer thickness range is in 1nm to 100um, and seed layer sheet is as being one
Layer or multilayered structure, it is one or more of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel that seed layer, which uses,；Pass through plating
Copper makes copper metal full of the hole TSV, and carries out densification at a temperature of 200 to 500 degree, and the copper of lid surface is made by CMP process
Removal, leaves behind and fills out copper；
Susceptor surface makes RDL, and process includes production insulating layer, and thickness of insulating layer range is used in 10nm to 1000um
Silica or silicon nitride；It is opened a window by photoetching, dry etch process, connects the copper post one end in the hole RDL with TSV of pedestal；
Its pad and RDL are located at the same face, that is, are located at one end that the copper post in the hole TSV is exposed；Pedestal without metal carry out on one side it is thinned, lead to
The technique for crossing grinding, wet etching and dry etching exposes the copper post other end；Insulating layer is covered on the copper post surface of exposing, absolutely
Edge layer thickness range opens a window in 10nm to 1000um, by photoetching, etching technics in surface of insulating layer, reveals copper post after windowing
Out；And RDL is made on the surface of pedestal；
105) encapsulation step: being placed in functional chip by way of eutectic bonding on the pad of pedestal, will by routing technique
The PAD of functional chip is with the pad connection of pedestal, and wherein functional chip thickness is between 50um to 600um；Pass through wafer key again
The mode of conjunction is bonded together cover board and pedestal, and cutting obtains final mould group；Wherein bonding temperature range is 200 to 500
Degree.
2. a kind of radio frequency chip system in package technique with electro-magnetic screen function according to claim 1, feature
Be: by cvd silicon oxide, perhaps silicon nitride is formed absolutely as insulating layer or directly thermal oxidation above step 101) cover board
Edge layer.
3. a kind of radio frequency chip system in package technique with electro-magnetic screen function according to claim 1, feature
Be: the metal layer of step 101) cover board includes RDL, and RDL is not connected to copper post top.
4. a kind of radio frequency chip system in package technique with electro-magnetic screen function according to claim 1, feature
Be: photoetching, electroplating technology production RDL include production insulating layer in step 103), and thickness of insulating layer range is arrived in 10nm
1000um, material prestige silica or silicon nitride；RDL is made in silicon chip surface by photoetching, plating again, RDL includes cabling
And bonding.
5. according to claim 1 or a kind of radio frequency chip system in package with electro-magnetic screen function as claimed in claim 4
Technique, it is characterised in that: insulating layer is covered on the surface RDL, open a window exposed pad on the insulating layer, and the metal of RDL uses copper,
Aluminium, nickel, silver, gold, tin is one such or several, this body structure of RDL is one or more layers, and thickness range arrives for 10nm
1000um；Pad windowing 10um to 10000um diameter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811176851.6A CN110010499B (en) | 2018-10-10 | 2018-10-10 | Radio frequency chip system-in-package process with electromagnetic shielding function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811176851.6A CN110010499B (en) | 2018-10-10 | 2018-10-10 | Radio frequency chip system-in-package process with electromagnetic shielding function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110010499A true CN110010499A (en) | 2019-07-12 |
| CN110010499B CN110010499B (en) | 2021-01-22 |
Family
ID=67164863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811176851.6A Active CN110010499B (en) | 2018-10-10 | 2018-10-10 | Radio frequency chip system-in-package process with electromagnetic shielding function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110010499B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112786454A (en) * | 2021-01-12 | 2021-05-11 | 中国电子科技集团公司第五十八研究所 | Radio frequency chip packaging method and packaging structure with electromagnetic shielding function |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101282594A (en) * | 2008-04-10 | 2008-10-08 | 苏州敏芯微电子技术有限公司 | Encapsulation structure for Micro-electromechanical microphone with two-sided mounting-pasted electrode |
| CN101552263A (en) * | 2009-05-18 | 2009-10-07 | 中国电子科技集团公司第十三研究所 | Wafer-level packaging of chip and packaging method thereof |
| CN203503623U (en) * | 2013-10-21 | 2014-03-26 | 安徽北方芯动联科微***技术有限公司 | Monolithic integrated MEMS chip based on conductive pole wafer level packaging |
| CN108083223A (en) * | 2018-01-15 | 2018-05-29 | 杭州臻镭微波技术有限公司 | The radio frequency micro-system and its manufacturing method of a kind of silicon based three-dimensional Manufacturing resource |
| US20180278231A1 (en) * | 2017-03-24 | 2018-09-27 | Dror Hurwitz | Single Crystal Piezoelectric RF Resonators and Filters |
-
2018
- 2018-10-10 CN CN201811176851.6A patent/CN110010499B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101282594A (en) * | 2008-04-10 | 2008-10-08 | 苏州敏芯微电子技术有限公司 | Encapsulation structure for Micro-electromechanical microphone with two-sided mounting-pasted electrode |
| CN101552263A (en) * | 2009-05-18 | 2009-10-07 | 中国电子科技集团公司第十三研究所 | Wafer-level packaging of chip and packaging method thereof |
| CN203503623U (en) * | 2013-10-21 | 2014-03-26 | 安徽北方芯动联科微***技术有限公司 | Monolithic integrated MEMS chip based on conductive pole wafer level packaging |
| US20180278231A1 (en) * | 2017-03-24 | 2018-09-27 | Dror Hurwitz | Single Crystal Piezoelectric RF Resonators and Filters |
| CN108083223A (en) * | 2018-01-15 | 2018-05-29 | 杭州臻镭微波技术有限公司 | The radio frequency micro-system and its manufacturing method of a kind of silicon based three-dimensional Manufacturing resource |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112786454A (en) * | 2021-01-12 | 2021-05-11 | 中国电子科技集团公司第五十八研究所 | Radio frequency chip packaging method and packaging structure with electromagnetic shielding function |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110010499B (en) | 2021-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105206592B (en) | The structure and production method of fan-out package | |
| EP2469595B1 (en) | Vertically integrated systems | |
| US5380681A (en) | Three-dimensional multichip package and methods of fabricating | |
| US20090072357A1 (en) | Integrated shielding process for precision high density module packaging | |
| CN110010563A (en) | A kind of bottom heat radiation type radio frequency chip pinboard packaging technology | |
| US5182420A (en) | Method of fabricating metallized chip carriers from wafer-shaped substrates | |
| US20040259351A1 (en) | Method for manufacturing semiconductor package | |
| CN110010548A (en) | A kind of cavity structure production method of bottom belt pad | |
| CN110010571A (en) | A kind of water cooling groove structure of high-power RF chip system grade encapsulation and preparation method thereof | |
| CN110010500A (en) | A kind of highly integrated radio frequency chip system in package technique | |
| CN111952243A (en) | Groove chip embedding process | |
| KR20190015097A (en) | Chip Package and Method of Manufacturing the Same | |
| CN110010498A (en) | A kind of hermetic type system in package technique of side heat dissipation | |
| CN110010478A (en) | A kind of radio frequency micro-system and moulding process with electro-magnetic screen function | |
| CN110010499A (en) | A kind of radio frequency chip system in package technique with electro-magnetic screen function | |
| CN110010480A (en) | A kind of radio frequency chip electromagnetic shielding packaging technology of wafer scale | |
| CN110010504A (en) | A kind of radio-frequency module manufacture craft with electro-magnetic screen function | |
| CN110010476A (en) | A kind of novel electroplating process for filling hole in system-in-package structure | |
| CN110010482A (en) | A kind of hermetic type radio frequency chip packaging technology based on flexible circuit board | |
| CN110010566A (en) | It is a kind of to erect the liquid-cooling heat radiation radio-frequency structure and preparation method thereof placed | |
| CN110010475A (en) | A kind of radiating module manufacture craft of radio frequency chip system in package | |
| CN110190376B (en) | Radio frequency system-in-package module with antenna combined with liquid cooling heat dissipation structure and manufacturing method thereof | |
| CN110010487A (en) | A kind of radio frequency chip system in package technique of vertical welding | |
| CN110649002A (en) | Fan-out type packaging structure of integrated antenna and manufacturing method thereof | |
| CN110010495A (en) | A kind of high density side wall interconnected method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |