CN110009107B - 一种用于形成量子比特设备的方法 - Google Patents

一种用于形成量子比特设备的方法 Download PDF

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CN110009107B
CN110009107B CN201811590556.5A CN201811590556A CN110009107B CN 110009107 B CN110009107 B CN 110009107B CN 201811590556 A CN201811590556 A CN 201811590556A CN 110009107 B CN110009107 B CN 110009107B
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insulating layer
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CN110009107A (zh
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C·梅克林
N·科莱尔特
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Interuniversitair Microelektronica Centrum vzw IMEC
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Abstract

根据本发明概念的一方面，提供了一种用于形成量子比特设备的方法，该方法包括：形成嵌入被形成在基板上的绝缘层中的栅电极，其中该基板的上表面由IV族半导体材料形成，并且其中该栅电极沿着该基板在第一水平方向上延伸，在绝缘层中形成孔洞，该孔洞暴露基板的一部分，在外延生长工艺中形成包括III‑V族半导体基板接触部件和III‑V族半导体盘部件的半导体结构，该基板接触部件具有与基板的所述部分邻接的底部分和在绝缘层的上表面上方从孔洞突出的上部分，半导体盘部件从基板接触部件的所述上部分沿着绝缘层的所述上表面水平地延伸，以与栅电极的一部分重叠，形成覆盖盘部件的一部分的掩模，盘部件的所述部分在第二水平方向上跨栅电极的所述部分延伸，蚀刻通过掩模暴露的半导体结构的区域，使得盘部件的掩模部分保留以形成跨栅电极的所述部分延伸的沟道结构，以及在栅电极的所述部分的相对侧处，在沟道结构上形成超导体源极接触和超导体漏极接触。

Description

一种用于形成量子比特设备的方法
技术领域
本发明概念涉及一种用于形成量子比特设备的方法。本发明概念进一步涉及一种量子比特设备。
背景
量子信息科学有潜力从根本上改进用于传感、计算、模拟和通信的现有技术和设备。
量子信息处理***的一个主要挑战是实现具有足够程度的相干性的量子比特，同时仍然允许操纵和测量。一种显示出前景的量子比特设备类型是基于所谓的Majorana(马约拉纳)费米子的设备。Majorana费米子是它自己的反粒子，并可在量子力学架构中被描述为电子和空穴的叠加。
尽管基于Majorana费米子的量子比特设备已经在实验室规模上得以证明，但实现工业上可行且可扩展的量子比特设备仍然是一个挑战。因此，量子信息处理实验仍然是昂贵且耗时的努力。现有的实验室设置在面对微调和缩放时也具有挑战。
概述
本发明概念的目标是解决在现有技术中的该问题。可从下文理解进一步和替换的目标。
根据本发明概念的一方面，提供了一种用于形成量子比特设备的方法，该方法包括：
形成嵌入被形成在基板上的绝缘层中的栅电极，其中该基板的上表面由IV族半导体材料形成，并且其中栅电极沿着基板在第一水平方向上延伸，
在绝缘层中形成孔洞，该孔洞暴露基板的一部分，
在外延生长工艺中形成包括III-V族半导体基板接触部件和III-V族半导体盘部件的半导体结构，
该基板接触部件具有与基板的所述部分邻接的底部分和在绝缘层的上表面上方从孔洞突出的上部分，
半导体盘部件从基板接触部件的所述上部分沿着绝缘层的所述上表面水平地延伸，以与栅电极的一部分重叠，
形成覆盖盘部件的一部分的掩模，盘部件的所述部分在第二水平方向上跨栅电极的所述部分延伸，
蚀刻通过掩模暴露的半导体结构的区域，使得盘部件的掩模部分保留以形成跨栅电极的所述部分延伸的沟道结构，以及
形成超导体源极接触和超导体漏极接触以便在栅电极的所述部分的相对侧处接触沟道结构。
本发明方法能够对量子比特设备进行准确、可重复和可扩展的制造。III-V族半导体沟道结构与超导体源极和漏极接触的组合使得能够实现基于Majorana费米子的量子比特设备。量子比特设备在此意味着具有这样的配置的半导体设备：使得在正确的操作条件下，它可以支持或提供状态或粒子(或者更具体地，在Majorana费米子的情况下为准粒子)，该状态或粒子可作为其状态可***纵和检测的量子比特来操作。
由于沟道结构是通过图案化外延生长的III-V族材料结构而形成的，因此可避免在单独的晶片上生长纳米结构(诸如垂直纳米线)并随后将它们转移到目标基板的典型现有技术方式。该方法因此允许整体更有效的工艺，因为将纳米线转移到目标基板处的预期位置处可能是微妙的并且难以缩放。
此外，通过图案化形成沟道结构允许相对于栅电极对沟道结构的尺寸、形状和布置进行相当程度的控制。
通过将栅电极形成为嵌入式栅电极，可避免使沟道结构暴露于栅电极和栅极电介质形成的潜在的不利工艺条件。此外，栅电极的嵌入式配置使得能够实现对于量子比特设备操作而言合适的强度的栅-沟道耦合。
在设备特性方面，该方法使得量子比特设备的可扩展制造在结构和性能方面具有改进的均匀性。
超导体源极接触和超导体漏极接触有利地在形成沟道结构之后被形成。更具体地，该方法可包括在栅电极的所述部分的相对侧处，在沟道结构上形成超导体源极接触和超导体漏极接触。这有助于实现沟道结构的源极/漏极部分与源极/漏极接触之间的适当对准。
基板的上表面预期为基板的主表面，在该主表面上执行根据本发明方法的工艺。因此，“上(部)”不应被解释为需要基板的特定取向。
如本文所使用的，术语第一水平方向指的是沿着基板(即沿着基板的上表面)的方向。
相应地，第二水平方向指的是沿着基板的方向，该第二水平方向与该第一水平方向不同。第一和第二水平方向可表示相互垂直的方向，但是可更一般地相对于彼此以一定角度延伸。因此，术语水平平面可被用于指代由第一和第二水平方向定义的平面。
换言之，术语水平平面可代表平行于基板的上(主)表面的平面。
垂直方向可指代法向于基板的上(主)表面或垂直于第一和第二水平方向的方向。
超导体在此意味着当保持在低于因材料而异的临界温度TC的温度时表现出超导性的任何材料。作为示例，Al的TC为1.20K、Ta的TC为4.48K、Ti的TC为0.39K、Nd的TC为9.26K。
掩模可被形成为使得基板接触部件通过掩模暴露。因此，可在蚀刻期间移除基板接触部件，其中沟道结构通过绝缘层与基板电绝缘。
根据一实施例，所述形成被嵌入绝缘层中的栅电极包括：
在基板的上表面上形成第一部分绝缘层，
形成部分地延伸穿过第一部分绝缘层的沟槽，
在沟槽中形成栅电极，以及
用第二部分绝缘层覆盖栅电极和第一部分绝缘层，其中第一部分绝缘层和第二部分绝缘层一起形成所述绝缘层。由于沟槽被形成为仅部分地延伸穿过绝缘层，所以栅电极可被形成在沟槽的电绝缘底表面上。
栅电极可被形成为在第一水平方向上伸长。经伸长的栅电极能够沿着沟道的方向定义短的栅极-沟道界面。可由此实现高度局部化的栅极控制。
该方法可进一步包括在栅电极上，在沟道结构的相对侧处形成一对栅极接触。可由此提供与栅电极的易于访问的电接触。在栅电极被形成为伸长的情况下，接触可与沟道结构间隔开地形成，以减轻接触和沟道之间的不期望的杂散电容耦合。
根据一实施例，所述栅电极形成第一栅电极，并且该方法进一步包括形成至少第二栅电极，每个栅电极都被嵌入绝缘层并在所述第一方向上延伸。提供多于一个的栅电极能够实现沿沟道结构的长度的改善的沟道控制。
半导体盘部件可被形成为与每个栅电极的相应部分重叠，其中沟道结构可跨栅电极的所述部分中的每一个部分延伸。可由此以有效的方式在多个位置处获得栅电极-沟道结构重叠。
外延生长工艺可被调适使得在在其中盘部件生长的外延生长工艺的一部分期间，水平平面中的生长速率大于在垂直方向上的生长速率。由此可生长具有比垂直尺寸更大的水平尺寸的盘部件。这进而能够形成相对长且薄的沟道结构。
沟道结构可被形成为在第二水平方向上伸长。结合促进水平平面生长速率的外延生长工艺，可实现具有高的长度与厚度比和任选地高的宽度与厚度比的沟道结构。此类沟道结构可被称为纳米线。
盘部件可被形成为在水平平面中包围基板接触部件的上部分。沟道结构可因此被形成为在基板接触部件的任一侧上延伸。
根据一实施例，形成源极和漏极超导体接触可包括：
形成接触掩模，该接触掩模包括暴露沟道结构的源极部分的源极接触开口，并且进一步包括暴露沟道结构的漏极部分的漏极接触开口，以及
在源极接触开口中形成源极超导体接触，且在漏极接触开口中形成漏极超导体接触。
可由此方便地形成超导体接触，其中，由接触掩模覆盖的沟道结构的各部分(即，源极部分和漏极部分以外的各部分)可被保护以至少在一定程度上免受接触形成的工艺条件的影响。在各个掩模开口中形成源极和漏极超导体接触可包括在各个开口中沉积超导体材料。任选地，超导体种子层可被形成在暴露在接触开口中的沟道结构的各部分上。这可改善超导体源极/漏极接触和沟道结构之间的界面质量。
超导体源极接触和超导体漏极接触可包括Al、Ta、Ti或Nd，或者由Al、Ta、Ti或Nd组成。
外延生长工艺可包括生长InSb、InAs、InGaAs或InGaSb的半导体结构。当这些半导体材料与超导体接触结合使用时，能够在设备沟道中形成Majorana费米子。
有利地，为了能够实现改进的设备操作，至少盘部件可由单晶InSb、InAs、InGaAs或InGaSb形成。
根据本发明的概念的另一方面，提供了一种量子比特设备，包括：
嵌入被形成在基板上的绝缘层中的栅电极，其中该基板的上表面由IV族半导体材料形成，并且其中栅电极沿着基板在第一水平方向上延伸，
III-V族半导体沟道结构在第二水平方向上沿着绝缘层的上表面并跨栅电极的一部分水平地延伸，以及
超导体源极接触和超导体漏极接触在栅电极的所述部分的相对侧处被形成在沟道结构上。
根据本发明的概念的另一方面，提供了一种根据任何上述实施例及其变型的方法制造或获得的量子比特设备。这些进一步的方面可通常呈现与前述方法方面相同或相应的优点。
附图简述
参考附图，通过以下解说性和非限制性详细描述，将更好地理解本发明构思的以上以及附加目标、特征和优点。在附图中，除非另有说明，否则相同的附图标记将被用于相同的元件。
图1-13示意性地例示了用于形成量子比特设备的方法。
图14示意性地示出了量子比特设备的变体。
具体实施方式
现在将结合图1-13公开一种用于形成量子比特设备的方法。每个图都示出了该结构的横截面侧视图(图a)和俯视图(图b)。图A中的横截面图是沿相应编号的图B中所示的几何线截取的(即，线AA’或BB’)。在图中，轴Z代表垂直方向，对应于相对于基板100的上表面100a的法线方向。轴X和Y指的是相互正交的第一和第二水平方向，即，平行于基板100的主延伸平面(或相应地，平行于其上表面100a)的方向。应该注意的是，诸如结构层的相对厚度之类的所示元件的相对尺寸，仅仅是示意性的，并可以出于说明清楚性的目的而与物理结构不同。
图1A、1B例示了半导体基板100。半导体基板100可以是单一材料基板，或者由不同材料的组合形成，诸如堆叠在彼此之上的各种层来形成。在任何情况下，至少基板100的上表面100a由元素族IV半导体或化合物族IV半导体形成。上表面可由硅(Si)面[111]形成。可能的基板100结构包括Si基板或硅绝缘体(SOI)基板。基板100的上表面100a可被称为基板100的前侧表面。
在图2A、2B中，第一部分绝缘层102a已被形成在基板100的上表面100a上。第一部分绝缘层102a覆盖上表面100a。第一部分绝缘层102a可以是氧化物层，例如诸如SiO2之类的氧化硅。第一部分绝缘层102a也可以是例如高K介电材料(诸如氧化铝或一些其他CMOS兼容的栅极电介质)的介电层。第一部分绝缘层102a可通过诸如化学气相沉积(CVD)或原子层沉积(ALD)之类的任何合适和常规的沉积技术，或通过热氧化沉积在表面100a上。
在图3A、3B中，形成了部分地延伸穿过第一部分绝缘层102a的沟槽104。沟槽104的纵向尺寸在第一水平方向X上延伸。沟槽104的垂直尺寸在垂直方向Z上延伸。如图3A、3B所指示的，沟槽104的底表面由第一部分绝缘层102a的剩余厚度部分形成。在第一部分绝缘层102a上形成沟槽掩模层103。在掩模层103中形成沟槽限定开口。随后通过蚀刻第一部分绝缘层102a的材料将开口转移到第一部分绝缘层102a中以形成沟槽104。掩模层103可以是与形成第一部分绝缘层102a的材料兼容的任何其他典型光刻堆叠的基于光致抗蚀剂的掩模层103。可采用允许对第一部分绝缘层102a的材料进行蚀刻的任何传统的湿蚀刻或干蚀刻工艺。在对沟槽104进行蚀刻之后，掩模层103可被移除。沟槽104可取决于将被形成的最终沟道结构的预期长度被形成为例如具有20-100nm范围内的宽度。
在图4A、4B中，栅电极106已被形成在沟槽104中。栅电极106是伸长的，并沿基板上表面在第一水平方向X上延伸。栅电极106通过绝缘层102与基板100电绝缘。导电栅电极材料可被沉积在沟槽104中。导电栅电极材料可以是金属或金属合金。然而，其他栅电极材料也是可能的，诸如多晶硅。材料可通过任何常规沉积技术，诸如通过ALD、CVD或物理气相沉积(PVD)来沉积。材料可被沉积以填充沟槽104并覆盖第一部分绝缘层102a。过载栅电极材料(即，沉积在沟槽104外部的材料部分)可随后通过化学机械抛光(CMP)和/或回蚀刻工艺从沟槽外部移除，从而暴露绝缘层102a的上表面。
在图5A、5B中，栅电极106和第一部分绝缘层102a已被第二部分绝缘层102b覆盖。第一部分绝缘层102a和第二部分绝缘层102b一起形成嵌入栅电极106的化合物绝缘层，下文中被称为绝缘层102。第二部分绝缘层102b可以由与第一部分绝缘层102a相同的材料形成。第二部分绝缘层102b可以以与第一部分绝缘层102a类似的方式被沉积。绝缘层102的总厚度可以例如在10-50nm的范围内。
在图6A、6B中，孔洞108已被形成在绝缘层102中。孔洞108暴露基板100的上表面部分100b(即上表面100a的一部分)。孔洞108垂直地延伸穿过绝缘层102。在绝缘层102上已形成了孔洞掩模层107。在掩模层107中已形成了孔洞限定开口。随后通过蚀刻绝缘层102的材料将开口转移到绝缘层102中以形成孔洞108。掩模层107可以是与形成第一部分绝缘层102a的材料兼容的任何其他典型光刻堆叠的基于光致抗蚀剂的掩模层107。可采用允许对绝缘层102的材料进行蚀刻的任何传统的湿蚀刻或干蚀刻工艺。在对孔洞108进行蚀刻之后，掩模层107可被移除。
在图7A、7B中，半导体结构110已经在外延生长工艺中被形成，以包括III-V族半导体基板接触部件112和III-V族半导体盘部件114。基板接触部件112被形成在孔洞108中。盘部件114被形成在绝缘层102上方。基板接触部件112具有邻接上表面部分100b的底部分112a。基板接触部件112具有在绝缘层102的上表面102c上方从孔洞108突出的上部分112b。盘部件114从基板接触部件112的上部分112b沿着上表面102c(即在由X轴和Y轴定义的水平平面中)水平或横向地延伸。盘部件114因此被形成为在水平平面内包围，或换言之，在相对于基板接触部件112的圆周方向上包围基板接触部件112的上部分112b。如在图7a和7b中可以看到的，盘部件114的水平延伸使得盘部件114与栅电极106的部分106a重叠。半导体结构110可通过气相外延来形成。
应该注意的是，图7b中所例示的盘部件114的特定多边形形状仅仅是一个示例，并因此诸如大致六边形形状之类的其他形状也是可能的。具体形状通常可取决于生长条件和生长表面的取向。
InSb、InAs、InGaAs或InGaSb中的任何一种的半导体结构110都可被外延生长。外延工艺的工艺条件可被控制至少使得至少盘部件114由单晶材料形成，例如单晶InSb、InAs、InGaAs或InGaSb。但是，使用具有足够大的Lande(朗德)G因子的其他材料也是可能的。
外延生长工艺可被调适，使得对于III-V族半导体盘部件114，在水平平面(即沿第一和第二水平方向X和Y)中的生长速率大于在垂直方向Z上的生长速率。横向/水平生长速率可以例如(至少)比垂直生长速率大10倍。这可在其中生长盘部件114的外延生长过程的至少一部分期间被实现。然而，由于孔洞108内的横向生长将受到孔洞108的横向尺寸的限制，因此可在整个半导体结构110的外延生长中促进横向生长。
例如，通过将生长温度控制在500℃至650℃的范围内，可获得III-V族半导体材料的横向生长。总压力(在生长室中)可以在20毫巴至150毫巴的范围内。生长期间的工艺条件可被控制，使得获得在1nm/s至5nm/s的范围内的横向生长速率，以及在0.1nm/s至0.5nm/s的范围之内或之下的垂直生长速率。
在图8A、8B中，掩模115已被形成在半导体结构110上。掩模115可被称为沟道结构掩模115。掩模115覆盖盘部件114的一部分。掩模部分可被形成为在第二水平方向Y上延伸的盘部件114的伸长部分。该部分(以及掩模115)包括跨栅电极106的部分106a延伸的子部分114a。掩模115可如图9B所示被形成以暴露基板接触部件112。可通过在半导体结构110上沉积掩模层来形成掩模115，诸如基于光致抗蚀剂的掩模层或与半导体结构110的材料兼容的任何其他典型的光刻堆叠。随后可通过使用常规的图案化技术对掩模层进行图案化来定义掩模115。
在图9A、9B中，通过掩模115暴露的半导体结构110的区域已被蚀刻，使得盘部件114的掩模部分保留以形成沟道结构116。如图9A、9B所示，沟道结构116包括跨栅电极106的部分106a延伸的部分116a。沟道结构116沿绝缘层102的上表面延伸，以在第二水平方向Y上伸长。由于掩模115暴露基板接触部件112，当完成从基板100断开蚀刻之后形成沟道结构116。在蚀刻之后，绝缘层102中的任何剩余孔(即，先前暴露部分100b并容纳基板接触部件112的孔)都可例如由绝缘材料填充。可使用允许蚀刻半导体结构110的材料的任何常规干蚀刻工艺来蚀刻半导体结构110，诸如反应离子蚀刻(RIE)或离子束蚀刻(IBE)。在形成沟道结构116之后，掩模115可被移除。
在图10A、10B中，接触掩模118(即，源极/漏极接触掩模118)已被形成以覆盖沟道结构116和绝缘层102。接触掩模118可以例如是基于抗蚀剂的掩模或PMMA掩模。暴露沟道结构116的源极部分116s的源极接触开口118s已在掩模118中被定义。此外，暴露沟道结构116的漏极部分116d的漏极接触开口118d已在掩模118中被定义。
在图11A、11B中，超导体源极接触120和超导体漏极接触122已在栅电极106的部分106b的相对侧处被形成在沟道结构116上。超导体已被沉积在源极接触开口118s和漏极接触开口118d中。例如，可用CVD、ALD或PVD来沉积Al、Ta、Nd或Ti。超导体可被沉积以填充开口118s和118d并覆盖接触掩模118。过载超导体材料可随后通过CMP和/或回蚀刻工艺从沟槽外部移除，从而暴露接触掩模118的上表面。接触掩模118可随后被移除，其中接触120、122可保留在沟道结构116上。任选地，在接触开口118s、118d中沉积超导体之前，可在接触开口118s、118d中暴露的沟道结构116的各部分上沉积超导体种子层(例如，通过选择性区域外延)。
在图12A、12B中，栅极接触掩模124已被形成以覆盖沟道结构116，接触120、122和绝缘层102。栅极接触掩模124可以例如是基于抗蚀剂的掩模或PMMA掩模。已在掩模124中定义了一对栅极接触开口124a、124b，从而在栅电极106的正上方暴露绝缘层的相应部分。
在图13A、13B中，一对栅极接触126、128已被形成在沟道结构116的相对侧上。栅极接触开口124a、124b已被转移到绝缘层102中，以在绝缘层102中形成一对栅极接触孔。栅极接触孔随后用导电接触材料来填充，例如诸如合适的CMOS兼容金属接触材料之类的金属。例如，可用CVD、ALD或PVD来沉积接触材料。过载接触材料可随后通过CMP和/或回蚀刻工艺从栅极接触孔外部移除，从而暴露栅极接触掩模124的上表面。掩模124随后被移除，其中接触126、128保留在栅电极106上。
所得到的设备具有使其适合用作量子比特设备的配置，该量子比特设备在本领域已知的正确操作条件下能够形成Majorana费米子并沿着在超导体源极和漏极120、122之间的沟道结构116传导Majorana费米子。栅电极106的配置允许纳米结构116中的化学势被调适以使得Majorana费米子(即量子比特)能***纵。有利地，多个此类量子比特可被形成在基板100上并且彼此互连以实现量子比特逻辑门。
在上文中已经参考了有限数量的示例主要地描述了本发明概念。然而，如本领域技术人员容易领会的，除了上文所公开的各示例以外的其他示例在如所附权利要求限定的发明概念的范围内是同样是可能的。
例如，同时从盘部件114形成多于一个(诸如两个或更多个)的沟道结构是可能的。沟道结构可被形成为跨栅电极106的相应部分106a延伸。沟道结构可被形成为彼此平行地延伸。通过对沟道结构掩模(对应于上文的掩模115)进行图案化可形成多于一个的沟道结构以包括多个分立的掩模部分，每个掩模部分限定相应的沟道结构。
根据进一步的变型，图14例示了一量子比特设备，其中与栅电极106平行的附加的嵌入式栅电极206、306已沿着沟道结构116被形成。在栅极接触206、306上已形成了相应的另外的栅极接触对226、228和326、328。如结合图3A和3B所公开的，可通过形成与沟槽104平行的另外的沟槽来形成另外的栅电极206、306。然而，三个栅电极仅表示一个示例，并且量子比特设备可被形成为沿着沟道结构116包括任何数量(但是至少一个)的嵌入式栅电极。

Claims (11)

1.一种形成量子比特设备的方法，所述方法包括：
形成嵌入被形成在基板(100)上的绝缘层(102)中的栅电极(106)，其中所述基板(100)的上表面(100a)由IV族半导体材料形成，并且其中所述栅电极(106)沿着所述基板(100)延伸并被形成以在第一水平方向上伸长，
在所述绝缘层(102)中形成孔洞(108)，所述孔洞(108)暴露所述基板(100)的一部分(100b)，
在外延生长工艺中形成包括III-V族半导体基板接触部件(112)和III-V族半导体盘部件(114)的半导体结构(110)，
所述基板接触部件(112)具有与所述基板(100)的所述部分(100b)邻接的底部分(112a)和在所述绝缘层(102)的上表面(102c)上方从所述孔洞(108)突出的上部分(112b)，
所述半导体盘部件(114)从所述基板接触部件(112)的所述上部分(112b)沿着所述绝缘层(102)的所述上表面(102c)水平地延伸，以与所述栅电极(106)的一部分(106a)重叠，
形成覆盖所述盘部件(114)的一部分的掩模(115)，所述盘部件(114)的被所述掩模(115)覆盖的所述部分在第二水平方向上跨所述栅电极(106)的所述部分(106a)延伸，其中所述基板接触部件(112)通过所述掩模(115)暴露，
蚀刻通过所述掩模(115)暴露的所述半导体结构(110)的区域，使得所述盘部件(114)的掩模部分保留以形成沟道结构(116)，沟道结构(116)在第二水平方向上伸长并跨所述栅电极(106)的所述部分(106a)延伸，以及
在所述栅电极(106)的所述部分(106b)的相对侧处，在所述沟道结构(116)上形成超导体源极接触(120)和超导体漏极接触(122)。
2.如权利要求1所述的方法，其特征在于，所述形成被嵌入所述绝缘层(102)中的所述栅电极(106)包括：
在所述基板(100)的所述上表面(100a)上形成第一部分绝缘层(102a)，
形成部分地延伸穿过所述第一部分绝缘层(102a)的沟槽(104)，
在所述沟槽(104)中形成所述栅电极(106)，以及
用第二部分绝缘层(102b)覆盖所述栅电极(106)和所述第一部分绝缘层(102a)，其中所述第一部分绝缘层(102a)和所述第二部分绝缘层(102b)一起形成所述绝缘层(102)。
3.如权利要求1或2所述的方法，其特征在于，进一步包括在所述沟道结构(116)的相对侧处，在所述栅电极(106)上形成一对栅极接触(126，128)。
4.如权利要求2所述的方法，其特征在于，所述栅电极(106)形成第一栅电极(106)，并且该方法进一步包括形成至少第二栅电极(206)，每个栅电极(106，206)被嵌入所述绝缘层(102)中并在所述第一水平方向上延伸。
5.如权利要求4所述的方法，其特征在于，所述半导体盘部件(114)被形成为与所述栅电极(106，206)中的每一个栅电极的相应部分重叠，并且其中所述沟道结构(116)跨所述栅电极(106、206)的被所述半导体盘部件(114)重叠的所述相应部分中的每一个部分延伸。
6.如权利要求1或2所述的方法，其特征在于，所述外延生长工艺被调适为使得在在其中所述盘部件(114)生长的所述外延生长工艺的一部分期间，水平平面中的生长速率大于在垂直方向上的生长速率。
7.如权利要求1或2所述的方法，其特征在于，所述盘部件(114)被形成为在水平平面内包围所述基板接触部件(112)的所述上部分(112b)。
8.如权利要求1或2所述的方法，其特征在于，形成所述源极和漏极超导体接触(120，122)包括：
形成接触掩模(118)，所述接触掩模(118)包括暴露所述沟道结构(116)的源极部分(116s)的源极接触开口(118s)，并且进一步包括暴露所述沟道结构(116)的漏极部分(116d)的漏极接触开口(118d)，以及
在所述源极接触开口(118s)中形成所述源极超导体接触，且在所述漏极接触开口(118d)中形成所述漏极超导体接触。
9.如权利要求1或2所述的方法，其特征在于，所述超导体源极接触(120)和所述超导体漏极接触(122)包括Al、Ta、Ti或Nd。
10.如权利要求1或2所述的方法，其特征在于，所述外延生长工艺包括生长InSb、InAs、InGaAs或InGaSb的所述半导体结构(110)。
11.如权利要求10所述的方法，其特征在于，至少所述盘部件(114)由单晶InSb、InAs、InGaAs或InGaSb形成。
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