CN109994069A - GOA driving circuit and array substrate - Google Patents
GOA driving circuit and array substrate Download PDFInfo
- Publication number
- CN109994069A CN109994069A CN201910213094.3A CN201910213094A CN109994069A CN 109994069 A CN109994069 A CN 109994069A CN 201910213094 A CN201910213094 A CN 201910213094A CN 109994069 A CN109994069 A CN 109994069A
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- China
- Prior art keywords
- cabling
- signal lead
- goa
- via hole
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
This announcement provides a kind of GOA driving circuit and array substrate, including GOA circuit region and bus area, and GOA circuit region includes cascade multiple GOA circuit units；Bus area includes a plurality of signal lead and a plurality of connection cabling, it is stacked with per adjacent two bars cabling to form a signal lead unit, via hole is equipped on every bars cabling, connection cabling is electrically connected by via hole with corresponding signal lead, GOA circuit unit is attached by connection cabling with corresponding signal lead, by being stacked to every adjacent two bars cabling, bus area is not only made to complete original function, and it can be by the reduced width in GOA driving circuit bus area to original 1/2, to realize the frame for reducing GOA driving circuit, achieve the purpose that ultra-narrow frame, it reduces costs, improve product competitiveness.
Description
Technical field
This announcement is related to field of display technology more particularly to a kind of GOA driving circuit and array substrate.
Background technique
It is directly to make gate driving circuit that array substrate row, which drives (Gate driver On Array, GOA) technology,
In array substrate, the driving method progressively scanned to Gate is realized, to replace the driving chip made by external silicon chip
A kind of technology.GOA technology can realize the narrow frame even Rimless design of product, be set with increasing client to display panel technique
Meter selection, extended products application field.
However, Fig. 1 is that the signal in existing 100 ' of GOA driving circuit is walked by taking conventional 4CK GOA driving circuit as an example
The attachment structure schematic diagram of line and GOA circuit unit；Fig. 2 is the structure of the signal lead in existing GOA driving circuit bus area
Schematic diagram.As shown in Figure 1 and Figure 2, every bars cabling CK1, CK2, CK3, CK4 individually separate vertical placement, and mutually protect
Maintain an equal level row, and offers via hole in each signal lead respectively, and be electrically connected with cabling is connect by the via hole.Cause
This, the wider width in GOA driving circuit bus area in the prior art causes the frame of GOA driving circuit wider, does not meet and work as
The trend of lower ultra-narrow frame, does not have product competitiveness and price competitiveness.
Accordingly, it is desirable to provide a kind of the GOA driving circuit and array substrate of the frame that can reduce GOA driving circuit, to solve
Certainly above-mentioned technical problem.
Summary of the invention
This announcement provides a kind of GOA driving circuit and array substrate, solves GOA driving circuit bus area in the prior art
Wider width, and then lead to the wider technical problem of GOA driving circuit frame.
To solve the above problems, the technical solution that this announcement provides is as follows:
This announcement embodiment provides a kind of GOA driving circuit, comprising:
GOA circuit region, the GOA circuit region include cascade multiple GOA circuit units；
Bus area, the bus area includes a plurality of signal lead and a plurality of connection cabling, per adjacent two bars cabling phase
It mutually stacks to form a signal lead unit, every bars cabling is equipped with via hole, and the connection cabling passes through the via hole
It is electrically connected with the corresponding signal lead, the GOA circuit unit is walked by the connection cabling with the corresponding signal
Line connection.
According to this announcement embodiment provide GOA driving circuit, the signal lead unit include the first signal lead with
Second signal cabling, first signal lead are arranged along the vertical direction with the second signal cabling.
According to the GOA driving circuit that this announcement embodiment provides, the second signal cabling is set to first signal
On cabling.
According to the GOA driving circuit that this announcement embodiment provides, the via hole includes the first via hole and the second via hole, described
First via hole is set in first signal lead, and second via hole is set on second signal cabling.
According to the GOA driving circuit that this announcement embodiment provides, the quantity phase of first via hole and second via hole
Together.
According to the GOA driving circuit that this announcement embodiment provides, the second signal cabling surrounds first via hole, makes
It obtains the second signal cabling and first via hole forms winding structure.
According to the GOA driving circuit that this announcement embodiment provides, the quantity of the signal lead is 2N, wherein N is nature
Number.
According to the GOA driving circuit that this announcement embodiment provides, the connection cabling is made of indium tin oxide.
This announcement embodiment provides a kind of array substrate, and the array substrate includes above-mentioned GOA driving circuit.
According to the array substrate that this announcement embodiment provides, the array substrate is amorphous silicon array substrate or indium gallium zinc oxygen
Compound array substrate.
The GOA driving circuit and array substrate that this announcement offer is provided of this announcement, by driving electricity to GOA
Road bus area is stacked with per adjacent two bars cabling to form a signal lead unit, and to connect by via hole
Cabling is electrically connected with corresponding signal lead, and then is connected to corresponding GOA circuit unit, completes bus area
Original function, and the reduced width in GOA driving circuit bus area to original 1/2 can be driven to realize and reduce GOA
The frame of dynamic circuit, achievees the purpose that ultra-narrow frame, reduces costs, improve product competitiveness.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of announcement
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the attachment structure schematic diagram of the signal lead and GOA circuit unit in the GOA driving circuit of the prior art；
Fig. 2 is the structural schematic diagram of the signal lead in the GOA driving circuit of the prior art in bus area.
Fig. 3 is the company of the signal lead and GOA circuit unit in a kind of GOA driving circuit that this announcement embodiment one provides
Connect structural schematic diagram；
The structure of signal lead in a kind of GOA driving circuit that Fig. 4 provides for this announcement embodiment one in bus area is shown
It is intended to.
Fig. 5 is a kind of structural schematic diagram for array substrate that this announcement embodiment two provides.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate this announcement
Example.The direction term that this announcement is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand this announcement, rather than to
Limit this announcement.The similar unit of structure is with being given the same reference numerals in the figure.
This announcement is directed to the GOA driving circuit and array substrate of the prior art, leads to the width in GOA driving circuit bus area
It is wider, and then lead to the wider technical problem of the frame of GOA driving circuit, the present embodiment is able to solve the defect.
Embodiment one
As shown in Figure 3, Figure 4, this announcement embodiment provides a kind of GOA driving circuit 100, comprising:
GOA circuit region 1, the GOA circuit region 1 include cascade multiple GOA circuit units 10；
Bus area 2, the bus area 2 includes a plurality of signal lead 20 and a plurality of connection cabling 21, per adjacent two bars
Cabling 20 is stacked with to form a signal lead unit, and every bars cabling 20 is equipped with via hole, the connection cabling 21
It is electrically connected by the via hole with the corresponding signal lead 20, the GOA circuit unit 10 passes through the connection cabling 21
It is attached with the corresponding signal lead 20, and then gives clock signal transmission to the corresponding GOA circuit unit 10, it is more
A GOA circuit unit 10 is then for generating corresponding gate drive signal realization to the essence of every scan line of array substrate
Really control.
The quantity of the signal lead 20 may be configured as 2N, wherein N is natural number, that is to say, that the signal lead 20
Quantity may be configured as multiple, this announcement embodiment should not limit this announcement as limit.However, due to forming the signal
Wiring unit at least needs 2 signal leads 20, and therefore, the quantity of the signal lead 20 should be at least 2, that is,
Say that the quantity of the clock signal should be at least 2.For the driving capability of the different GOA driving circuits 100, when described
The quantity of clock signal is different.The driving capability of the GOA driving circuit 100 is higher, and the quantity of the clock signal is more,
The present embodiment is illustrated by taking the GOA driving circuit 100 comprising 4 clock signal CK1~CK4 as an example.
Since the quantity of the clock signal is 4, then the quantity of the signal lead 20 is 4, the letter per adjacent two
Number cabling 20, which stack, forms a signal lead unit, therefore the signal lead list in the GOA driving circuit 100
The quantity of member is 2, i.e. the first signal lead unit 20a and second signal wiring unit 20b.The signal lead 20 is all made of
Single-layer metal setting, it is simple and easy, and the thickness of the signal lead unit can be reduced, and then the GOA driving can be reduced
The thickness of circuit 100.
Wherein, the first signal lead unit 20a includes signal lead 201, signal lead 203, i.e., the described signal is walked
Line 201 is the first signal lead, and the signal lead 202 is second signal cabling, and the signal lead 201, the signal are walked
Line 202 is arranged along the vertical direction.Specifically, the signal lead 201 is stacked with setting, institute with the signal lead 202
State the top that signal lead 202 is set to the signal lead 201；The second signal wiring unit 20b includes signal lead
203, signal lead 204, i.e., the described signal lead 203 are the first signal lead, and the signal lead 204 is walked for second signal
Line, the signal lead 203, the signal lead 204 are arranged along the vertical direction.Specifically, the signal lead 203 and institute
The mutually overlapping setting of signal lead 204 is stated, the signal lead 204 is set to the top of the signal lead 203.Described first
The signal lead unit 20a and second signal wiring unit 20b keeps vertical and is parallel to each other.
Several via holes 2011 are provided in the signal lead 201, due to being provided with first in the first signal element
Via hole, the via hole 2011 are the first via hole.First connection cabling 211 is covered in the mistake in the signal lead 201
At hole 2011 so that the signal lead 201 is connect cabling 211 with first and is electrically connected by the via hole 2011, by when
Clock signal CK1 is transferred to corresponding GOA unit 11 by the first connection cabling 211.Wherein, the first connection cabling
211 are chosen as indium tin oxide (Indium tin oxide, ITO).
The signal lead 201 is set to 202 top of signal lead, to realize the light of the GOA driving circuit 100
Thinning can paste the signal lead 202 to realize the lightening of the display panel comprising the GOA driving circuit 100
In the top of the signal lead 201.Meanwhile the signal lead 202 makees Winding Design around the via hole 2011, so that institute
It states signal lead 202 and the via hole 2011 forms winding structure, so that the signal lead 202 covers the signal lead
The part that the via hole 2011 is removed on 201, avoid influencing the first connection cabling 211 by the via hole 2011 with it is described
Signal lead 201 is electrically connected.
Meanwhile several via holes 2021 are provided in the signal lead 202, due on the second signal cabling
It is provided with the second via hole, the via hole 2021 is the second via hole.The via hole 2021 is disposed adjacent with the via hole 2011, is made
It obtains the via hole 2011 and the via hole 2021 is non-overlapping in the horizontal direction.Meanwhile second connection cabling 212 be covered in it is described
At the via hole 2021 in signal lead 202, so that the signal lead 202 is connected by the via hole 2021 with described second
It connects cabling 212 to be electrically connected, clock signal CK2 is transferred to corresponding GOA unit by the second connection cabling 212
12.Similarly, the second connection cabling 212 is also chosen as ITO.
Since the via hole 2011 and the via hole 2022 itself have a certain size impedance, in order to enable institute
The consistency of the impedance of signal lead 201 and signal lead 202 is stated, it can be by the quantity of the via hole 2011 and the via hole 2021
Keep identical.It further, can also be identical as the size holding of the via hole 2021 by the via hole 2011.It is same with this
When, this announcement embodiment does not limit the quantity of the via hole 2011 and the via hole 2021, can be 4 institutes as shown in Figure 4
Via hole 2011 and 4 via hole 2021 is stated, the via hole 2011 and the via hole 2021 can also be suitably reduced or increase and decrease
Quantity.
Similarly, structure one of the structure of the second signal wiring unit 20b with the first signal lead unit 20a
It causes.The signal lead 203 and the signal lead 204 are mutually overlapping, constitute the second signal wiring unit 20b, described
It is provided with via hole 2031 in signal lead 203, is provided with via hole 2041 in the signal lead 204, i.e., the described via hole 2031 is
For the first via hole, the via hole 2041 is the second via hole.The signal lead 203 is connect by the via hole 2031 with third
Cabling 213 is electrically connected, and clock signal CK3 is transferred to corresponding GOA unit 13 by the second connection cabling 212；
The signal lead 204 connect cabling 214 with the 4th by the via hole 2041 and is electrically connected, and clock signal CK4 is passed through
The 4th connection cabling 214 is transferred to corresponding GOA unit 14.
Since the signal lead 201 and the signal lead 202 are stacked, the signal lead 203 with it is described
Signal lead 204 is stacked, therefore the width in the bus area 2 will be reduced at least original 1/2, to reduce institute
State the frame of GOA driving circuit 100.
The present embodiment will be stacked together per adjacent two bars cabling, form a signal lead unit, described
Signal lead unit includes the first signal lead and second signal cabling.The signal lead unit also can further include third
Signal lead, for example, will be stacked together per adjacent three bars cabling, specifically, the second signal cabling setting
In in first signal lead, the third signal lead is set on the second signal cabling.Similarly, the third letter
It should still be provided with third via hole on number cabling, so that the connection cabling passes through the third via hole and the third signal lead
It is electrically connected, so that the GOA circuit unit is connect by the connection cabling with the third signal lead.Using
The frame in the GOA driving circuit bus area of this mode will further reduce.Form the signal of the signal lead unit
There is no restriction for the quantity of cabling, however the quantity of the signal lead stacked is more, and the thickness of the GOA driving circuit is got over
Greatly, therefore, the quantity for forming the signal lead of the signal lead unit can be determined according to actual conditions, this announcement is implemented
Example should not be as limitation.
Embodiment two
As shown in figure 5, this announcement embodiment provides a kind of array substrate 1000, the array substrate 1000 is amorphous silicon battle array
Column substrate or indium gallium zinc oxide array substrate, the array substrate 1000 includes viewing area 200 and non-display area 300, described
Non-display area 300 is located at the outside of the viewing area 200, and the non-display area 300 includes described in this announcement embodiment one
GOA driving circuit 100, the GOA driving circuit 100 are located at the left and right sides of the viewing area 200.In the viewing area 200
It is provided with multi-strip scanning line 201 and multiple data lines 202, clock signal CK1~CK4 is transmitted by the GOA driving circuit 100
To the scan line 201, data driver 400 generates data signal transmission to the data line 202.Since the GOA drives
Every adjacent two bars cabling 20 in the bus area 2 in circuit 100 is stacked together, to reduce the GOA driving
The frame of circuit 100, therefore, the frame size of the array substrate 1000 greatly reduce, and are advantageously implemented the narrow of display panel
Frame.
It has the beneficial effect that the GOA driving circuit and array substrate that this announcement provides, passes through the bus to GOA driving circuit
Area is stacked with to form one signal lead unit per adjacent two bars cabling, and by via hole make connection cabling and
Corresponding signal lead is electrically connected, and then is connected to corresponding GOA unit, and bus area is not only made to complete original function
Can, and the reduced width in bus area to original 1/2 to realize the frame for reducing GOA driving circuit, can be reached super
The purpose of narrow frame.
Although above preferred embodiment is not to limit in conclusion this announcement is disclosed above with preferred embodiment
This announcement is made, those skilled in the art can make various changes and profit in the spirit and scope for not departing from this announcement
Decorations, therefore the protection scope of this announcement subjects to the scope of the claims.
Claims (10)
1. a kind of GOA driving circuit characterized by comprising
GOA circuit region, the GOA circuit region include cascade multiple GOA circuit units；
Bus area, the bus area includes a plurality of signal lead and a plurality of connection cabling, per the adjacent mutual heap of two bars cabling
It is folded that form one signal lead unit, every bars cabling is equipped with via hole, the connection cabling pass through the via hole with it is right
The signal lead electrical connection answered, the GOA circuit unit are connected by the connection cabling with the corresponding signal lead
It connects.
2. GOA driving circuit according to claim 1, which is characterized in that the signal lead unit includes the first signal
Cabling and second signal cabling, first signal lead are arranged along the vertical direction with the second signal cabling.
3. GOA driving circuit according to claim 2, which is characterized in that the second signal cabling is set to described
In one signal lead.
4. GOA driving circuit according to claim 1, which is characterized in that the via hole includes the first via hole and the second mistake
Hole, first via hole are set in first signal lead, and second via hole is set on second signal cabling.
5. GOA driving circuit according to claim 4, which is characterized in that first via hole and second via hole
Quantity is identical.
6. GOA driving circuit according to claim 4, which is characterized in that the second signal cabling surrounds described first
Via hole, so that the second signal cabling and first via hole form winding structure.
7. GOA driving circuit according to claim 2, which is characterized in that the quantity of the signal lead is 2N, wherein N
For natural number.
8. GOA driving circuit according to claim 1, which is characterized in that the connection cabling is by indium tin oxide
It constitutes.
9. a kind of array substrate, which is characterized in that the array substrate includes the described in any item GOA drivings of claim 1 to 8
Circuit.
10. array substrate according to claim 9, which is characterized in that the array substrate be amorphous silicon array substrate or
Indium gallium zinc oxide array substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910213094.3A CN109994069A (en) | 2019-03-20 | 2019-03-20 | GOA driving circuit and array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910213094.3A CN109994069A (en) | 2019-03-20 | 2019-03-20 | GOA driving circuit and array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109994069A true CN109994069A (en) | 2019-07-09 |
Family
ID=67129698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910213094.3A Pending CN109994069A (en) | 2019-03-20 | 2019-03-20 | GOA driving circuit and array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109994069A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111223439A (en) * | 2020-03-12 | 2020-06-02 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit |
| CN111261094A (en) * | 2020-03-31 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | Grid driving array type display panel |
| CN113870796A (en) * | 2021-12-03 | 2021-12-31 | 北京京东方技术开发有限公司 | Display substrate and display device |
| CN113964136A (en) * | 2021-10-13 | 2022-01-21 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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| CN104698711A (en) * | 2015-04-01 | 2015-06-10 | 上海天马微电子有限公司 | Array substrate, display panel and electronic equipment |
| CN108563082A (en) * | 2018-04-27 | 2018-09-21 | 京东方科技集团股份有限公司 | Circuit board, display device and driving method |
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| CN104700813A (en) * | 2015-04-01 | 2015-06-10 | 上海中航光电子有限公司 | Array substrate and forming method thereof |
| CN104698711A (en) * | 2015-04-01 | 2015-06-10 | 上海天马微电子有限公司 | Array substrate, display panel and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111223439A (en) * | 2020-03-12 | 2020-06-02 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit |
| CN111261094A (en) * | 2020-03-31 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | Grid driving array type display panel |
| US11361695B2 (en) | 2020-03-31 | 2022-06-14 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Gate-driver-on-array type display panel |
| CN113964136A (en) * | 2021-10-13 | 2022-01-21 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN113964136B (en) * | 2021-10-13 | 2022-12-06 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN113870796A (en) * | 2021-12-03 | 2021-12-31 | 北京京东方技术开发有限公司 | Display substrate and display device |
| CN113870796B (en) * | 2021-12-03 | 2022-03-04 | 北京京东方技术开发有限公司 | Display substrate and display device |
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