CN109983570A - 具有晶片级有源管芯和外部管芯底座的半导体封装 - Google Patents

具有晶片级有源管芯和外部管芯底座的半导体封装 Download PDF

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Publication number
CN109983570A
CN109983570A CN201680091229.8A CN201680091229A CN109983570A CN 109983570 A CN109983570 A CN 109983570A CN 201680091229 A CN201680091229 A CN 201680091229A CN 109983570 A CN109983570 A CN 109983570A
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China
Prior art keywords
solder projection
epoxy resin
solder
silicon wafer
die
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CN201680091229.8A
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English (en)
Inventor
V.V.梅塔
E.J.李
S.加内桑
D.马利克
R.L.桑克曼
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Intel Corp
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Intel Corp
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Publication of CN109983570A publication Critical patent/CN109983570A/zh
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Abstract

描述了具有硅晶片上的有源管芯和外部管芯底座的半导体封装和封装组件，以及制作这样的半导体封装和封装组件的方法。在示例中，半导体封装组件包括具有通过第一焊料凸块而附接到硅晶片的有源管芯的半导体封装。第二焊料凸块在硅晶片上从有源管芯横向向外以提供用于外部管芯的底座。环氧树脂层可以围绕有源管芯并且覆盖硅晶片。孔可以在第二焊料凸块上方贯穿环氧树脂层以通过该孔暴露第二焊料凸块。因此，外部存储器管芯可以通过该孔而直接连接到硅晶片上的第二焊料凸块。

Description

具有晶片级有源管芯和外部管芯底座的半导体封装
技术领域
实施例处于集成电路封装的领域中，并且特别地，处于具有晶片级封装的半导体封装的领域中。
背景技术
移动半导体工业不断地朝着更小且更薄的半导体封装而工作以供用在移动设备产品中。已经出现了各种解决方案来减小半导体封装尺寸。例如，努力集中在减小片上***管芯或保持该管芯的有机嵌入式迹线衬底的总厚度上。其它解决方案包括离开堆叠封装（package-on-package）配置而朝向宽I/O存储器配置移动。此外，已经提出了晶片级封装，即将集成电路封装为硅晶片的一部分，以通过消除有机嵌入式迹线衬底来提供芯片规模封装。在这些解决方案中的任何解决方案中，不管尺寸减小如何，重要的是最大化半导体封装的功能性，例如智能电话的罗盘、感测、无线或电力管理功能。
附图说明
图1图示了依照实施例的半导体封装组件的横截面视图。
图2图示了依照实施例的包括硅晶片上的有源管芯和外部管芯底座（mount）的半导体封装的横截面视图。
图3图示了依照实施例的制作包括硅晶片上的有源管芯和外部管芯底座的半导体封装的方法的流程图。
图4A-4I图示了依照实施例的制作包括硅晶片上的有源管芯和外部管芯底座的半导体封装的方法中的操作。
图5是依照实施例的计算机***的示意图。
具体实施方式
描述了包括硅晶片上的有源管芯和外部管芯底座的半导体封装，以及制作这样的半导体封装的方法。在以下描述中，阐述了众多具体细节，诸如封装和互连架构，以便提供对实施例的透彻理解。对本领域技术人员将显而易见的是，可以在没有这些具体细节的情况下实践实施例。在其它实例中，并未详细描述公知的特征，诸如具体的半导体制作工艺，以免不必要地使实施例模糊。此外，要理解，图中所示的各种实施例是说明性表示并且不一定按比例绘制。
存在使得移动半导体封装更小且更薄的现有解决方案。然而，所述解决方案在功能性和/或制造成本方面可能具有折衷。例如，被提出用于减小片上***管芯或有机嵌入式迹线衬底的尺寸的解决方案移除那些部件的功能性以实现较小的尺寸。另一方面，被提出用于完全消除有机嵌入式迹线衬底的解决方案可能要求围绕有源管芯形成铜柱。类似地，被提出用于宽I/O存储器配置的解决方案可能要求制作硅通孔和硅通孔上的键合。用于精确地构建铜柱或硅通孔的制造工艺可以是复杂的，并且因此，这样的解决方案很可能具有低制造产量和高制造成本。因此，需要用于在不牺牲功能性的情况下减小移动半导体封装尺寸的低成本解决方案。
在一方面，一种半导体封装包括芯片到晶片封装，其消除了对于有机嵌入式迹线衬底和这样的衬底所要求的管芯到衬底互连的需要。倘若有机嵌入式迹线衬底通常具有175μm的厚度，并且用于这样的衬底的管芯到衬底互连通常具有45μm的厚度，则以下描述的半导体封装的总厚度可以近似比典型的移动半导体封装薄220μm。以下描述的半导体封装可以包括安装在硅晶片上的有源管芯，并且硅晶片可以合并功能性，即集成电路。因此，可以在不牺牲功能性的情况下减小半导体封装尺寸。半导体封装可以包括硅晶片上的外部管芯底座（例如，焊料凸块）以允许将外部存储器管芯直接安装在硅晶片上。因此，外部存储器可以使用高量且低成本的制造操作（诸如焊料回流工艺）直接连接到硅晶片，而不需要形成诸如铜柱之类的复杂互连结构。
参考图1，图示了依照实施例的半导体封装组件的截面视图。半导体封装组件100可以包括具有（多个）有源半导体管芯104的一个或多个半导体封装102。例如，半导体封装102可以是具有芯片到封装组件而没有有机嵌入式迹线衬底的WL-CSP。
（多个）有源管芯104可以电气连接到彼此或通过诸如硅晶片106之类的介于中间的结构而电气连接到外部部件。例如，如以下所描述的，诸如焊料凸块、硅通孔或重分布（redistribution）线之类的电气互连可以将（多个）有源管芯104电气连接到外部管芯108或印刷电路板110。
在实施例中，外部管芯108具有一个或多个I/O接触件（contact）112，并且可以直接连接到芯片到晶片组件中的硅晶片106。芯片到晶片互连114，例如铜柱、焊线或焊料凸块，可以从I/O接触件112延伸到硅晶片106上的对应电气互连。例如，I/O接触件112可以从有源管芯104横向向外连接到硅晶片106上的焊料凸块，如以下所描述的。
外部管芯108可以是任何类型的有源管芯。在实施例中，外部管芯108是高容量存储器管芯。高容量存储器管芯可以与有源管芯104通信以促进通过有源管芯104进行的较快处理以用于各种移动半导体封装功能性。例如，半导体封装可以是用在移动设备天线电路应用中的WL-CSP。
在实施例中，可以以具有一个或多个硅芯片的WL-CSP的形式使用外部管芯108。例如，可以使用具有（多个）重分布层和焊料凸块112的一个或一组（多个）外部管芯108。因此，小封装，例如WL-CSP封装，可以用作安装在半导体封装102上的外部管芯108。
半导体封装102可以安装在印刷电路板110上。（多个）有源管芯104、硅晶片106和印刷电路板110之间的电气互连可以包括焊料球和/或其它金属凸块、迹线或导线互连。作为示例，半导体封装组件100的半导体封装102可以是具有被布置在球场中的若干焊料球116的球珊阵列（BGA）部件。也就是说，可以以栅格或其它图案来布置焊料球116的阵列。印刷电路板110可以包括若干接触垫118，并且每一个焊料球116可以被安装并附接到对应的接触垫118。印刷电路板110可以是计算机***或设备（诸如智能电话）的母板或另一印刷电路板。印刷电路板110可以将信号路由至外部设备连接器（未示出）。因此，焊料球和接触垫附接可以提供半导体封装102的（多个）有源管芯104与外部设备之间的电气接口。
参考图2，示出了依照实施例的包括硅晶片上的有源管芯和外部管芯底座的半导体封装的横截面视图。半导体封装102可以包括硅晶片106，所述硅晶片106具有各种电气互连以用于耦合到其它部件。例如，硅晶片106可以具有从顶部表面204朝向底部表面206延伸以用于将顶部表面204上的电气接触件连接到底部表面206上的电气接触件的一个或多个晶片通孔202。晶片通孔202可以是部分地或完全地贯穿硅晶片106的厚度的导电结构。例如，晶片通孔202可以是隧穿硅晶片106的硅材料的铜互连。晶片通孔202可以具有等于硅晶片106的厚度的高度。也就是说，硅晶片106可以具有在顶部表面204与底部表面206之间的晶片厚度，并且晶片通孔202可以从顶部表面204向底部表面206延伸。
硅晶片106的材料类型和尺寸可以不同于有机嵌入式迹线衬底的对应特性。第一，可以由硅材料制作晶片106，并且可以由有机树脂材料形成嵌入式迹线衬底。第二，有机嵌入式迹线衬底通常具有在200-300μm的范围中的厚度，并且硅晶片106可以具有在顶部表面204与底部表面206之间的小于100μm的厚度。
半导体封装102可以包括用于将硅晶片106电气连接到其它封装部件的焊料凸块。例如，若干焊料凸块可以被布置在硅晶片106的顶部表面204上以将顶部表面204上的接触垫连接到有源管芯104和/或外部管芯108。在实施例中，第一焊料凸块208被布置在顶部表面204上在有源管芯104与硅晶片106之间。更特别地，有源管芯104可以安装在硅晶片106上，并且第一焊料凸块208可以将有源管芯104附接到硅晶片106。
第二焊料凸块210可以被从有源管芯104横向向外布置在顶部表面204上。术语横向向外指示第二焊料凸块210被在从有源管芯104的向外边缘的横向方向上布置在顶部表面204上。也就是说，第二焊料凸块210可以不竖直在有源管芯104与硅晶片106之间。此外，第二焊料凸块210可以不在围绕第一焊料凸块208的底部填充材料212内。因此，第一焊料凸块208和第二焊料凸块210可以在平行于顶部表面204的横向平面214内与彼此共面。也就是说，由于第一焊料凸块208和第二焊料凸块210二者都被布置在顶部表面204上，与通过铜柱从顶部表面204偏移相反，焊料凸块208、210可以在横向方向上在相同竖直位置处对准。
第一焊料凸块208和第二焊料凸块210可以适应于预期的互连功能。更特别地，顶部表面204上的每一个焊料凸块的尺寸可以对应于预期的互连。在实施例中，第一焊料凸块208小于第二焊料凸块210。例如，第一焊料凸块208可以提供有源管芯104上的电气接触件与顶部表面204上的电气接触件之间的互连，而第二焊料凸块210可以提供芯片到晶片互连114与顶部表面204上的电气接触件之间的互连。芯片到晶片互连114可以具有比有源管芯104上的电气接触件大的轮廓，并且因此，第二焊料凸块210可以具有比第一焊料凸块208大的横截面尺寸。焊料凸块尺寸方面的变化可以使焊料凸块通过不同工艺而形成。例如，可以通过电镀操作来制作较小的第一焊料凸块208，并且可以通过顶侧球附接操作来制作较大的第二焊料凸块210，如以下所描述的。因此，第一焊料凸块208可以是经电镀的焊料凸块，并且第二焊料凸块210可以是经顶侧球附接的焊料凸块。
在实施例中，环氧树脂层216围绕（多个）有源管芯104的四个或更多侧面。例如，环氧树脂层216可以被布置在硅晶片106的顶部表面204之上，并且可以围绕有源管芯104的侧壁和/或面向硅晶片106的顶部表面204的有源管芯104的底部表面延伸。环氧树脂层216还可以从有源管芯104横向向外覆盖第二焊料凸块210的一部分。然而，可以在第二焊料凸块210上方在环氧树脂层216中形成孔218，以通过孔218暴露第二焊料凸块210。也就是说，可以通过贯穿环氧树脂层216的孔218暴露第二焊料凸块210的至少一部分。因此，芯片到晶片互连114可以通过孔218从I/O接触件112延伸到第二焊料凸块210以通过孔218将I/O接触件112电气连接到第二焊料凸块210。
在实施例中，半导体封装102的上表面是平坦的。半导体封装102的上表面可以包括有源管芯104的上管芯表面220和环氧树脂层216的上环氧树脂表面222，其二者可以组合以形成平坦表面。例如，上管芯表面220和上环氧树脂表面222可以在第二横向平面224内共面。第二横向平面224可以被从穿过硅晶片106的顶部表面204上的焊料凸块的横向平面214竖直偏移。因此，第二横向平面224可以平行于顶部表面204。
半导体封装102可以包括安装在硅晶片106的底部表面206上的重分布层230。重分布层230可以具有若干重分布线232以将电气信号从硅晶片106的底部表面206上的电气接触件传导至焊料球116。例如，至少一个重分布线232可以在第一端处电气连接到晶片通孔202，并且在第二端处电气连接到焊料球116。也就是说，重分布层230上的焊料球116可以电气连接到对应的重分布线232。重分布线232可以贯穿重分布层230，并且重分布线232的至少一部分可以被定向在横向方向上。因此，重分布层230的重分布线232可以将电气信号从硅晶片106扇出到印刷电路板110上的电气接触件。
半导体封装组件100（并且更特别地，半导体封装102）的以上描述的结构提供用于将外部管芯108附接到芯片到晶片组件中的半导体封装102的集成堆叠封装结构。此外，该结构是晶片级芯片规模封装（WL-CSP），其可以减小半导体封装组件100的总尺寸而不牺牲对移动设备应用而言至关重要的功能性。如以下所描述的，WL-CSP架构可以通过可用的、低成本的制造工艺来实现。
参考图3，示出了依照实施例的制作包括硅晶片上的有源管芯和外部管芯底座的半导体封装的方法的流程图。图4A-4I图示了图3的方法中的操作，并且因此，以下组合地描述图3-4I。
以下描述的方法可以用于从初始硅晶片106制作若干WL-CSP。例如，在初始阶段，硅晶片106可以包括将第一晶片区404与邻近的第二晶片区406分开的切割沟槽（singulation trench）402。如以下所描述的，若干半导体封装102可以构建在邻近的区上，并且在制作工艺中的一点处，可以沿切割沟槽402切割半导体封装102（图4G）。因此，尽管以上将半导体封装102描述为单独的封装，但是将理解，半导体封装102的晶片级架构允许使用高量制造工艺同时制作若干半导体封装102。
在操作302处，在硅晶片106的顶部表面204上形成第一焊料凸块208。参考图4A，在实施例中，使用高产且低成本的硅技术来制作硅晶片106。硅晶片106可以是有源硅晶片106。也就是说，除了电气布线之外，硅晶片106还可以包括一个或多个集成电路以向半导体封装102提供功能性，例如I/O、存储器高速缓存等。可以使用任何已知的硅技术来制作硅晶片106和/或硅晶片106的集成电路。作为示例而非限制，可以使用22nm硅技术来制作部件。
在实施例中，硅晶片106包括从顶部表面204中途延伸到硅晶片106中的硅通孔407。例如，硅通孔407可以从顶部表面204向下延伸到80-90μm的深度。如以下所描述的，稍后可以暴露硅通孔以形成晶片通孔202。
可以在硅晶片106的顶部表面204上形成至少两组接触垫118。第一组接触垫410，例如第一组铜垫，可以位于硅通孔407之上以提供用于第一焊料凸块208和意图将有源管芯104附接到硅晶片106的其它焊料凸块的着陆处（landing）。第一焊料凸块208和意图将有源管芯104附接到硅晶片106的其它焊料凸块可以被电镀在第一组接触垫410上。因此，有源管芯104与硅晶片106之间的焊料凸块可以是经电镀的焊料凸块。
第二组接触垫412，例如第二组铜垫，可以被从第一组接触垫410横向向外布置在顶部表面204上。第二组接触垫412可以提供用于第二焊料凸块210和意图连接到芯片到晶片互连114和外部管芯108的其它焊料凸块的着陆处。
在操作304处，在硅晶片106的顶部表面204上形成第二焊料凸块210。参考图4B，第二焊料凸块210和意图连接到芯片到晶片互连114和外部管芯108的其它焊料凸块可以通过顶侧球附接（TSBA）操作来形成。TSBA操作是使用掩模和焊料球附接工艺的非电镀操作，如本领域中已知的。TSBA操作可以形成比用于制作第一焊料凸块208的电镀操作大的焊料凸块。因此，第二焊料凸块210可以是经顶侧球附接的焊料凸块，并且可以大于第一焊料凸块208。此外，倘若第二组接触垫412上的焊料凸块可以大于第一组接触垫410上的焊料凸块，结果就是第二组接触垫412可以具有比第一组接触垫410大的间隔，即间距。
尽管第二焊料凸块210可以通过TSBA操作来形成，但是这样的可能性不是限制性的，并且将理解，第二焊料凸块210可以通过电镀操作来形成。也就是说，在实施例中，在硅晶片106的顶部表面204上形成第二焊料凸块210。经电镀的第二焊料凸块210可以大于第一焊料凸块208，或者所述焊料凸块可以具有相同的尺寸。
在操作306处，将有源管芯104附接到硅晶片106。更特别地，参考图4C，可以通过第一焊料凸块208将有源管芯104附接到硅晶片106的顶部表面204。可以使用焊料回流工艺将有源管芯104上的电气接触件键合到硅晶片106的顶部表面204上的电气接触件来将各个经切割的片上***有源管芯104附接到硅晶片106。在该阶段可以将任何数目的有源管芯104和任何管芯类型（即具有特定功能性的管芯）附接到硅晶片106。作为示例，安装在硅晶片106上的有源管芯104可以包括中央处理单元管芯和调制解调器管芯。在实施例中，底部填充材料212在有源管芯104与硅晶片106之间流动以包封第一焊料凸块208。
在操作308处，将环氧树脂层216沉积在硅晶片106之上。例如，参考图4D，可以围绕有源管芯104并且在硅晶片106的顶部表面204之上沉积环氧树脂层216。环氧树脂层216可以覆盖第二焊料凸块210。可以在二次成型工艺中沉积环氧树脂层216。经二次成型的环氧树脂层216可以完全包封有源管芯104。也就是说，环氧树脂层216可以在二次成型操作完成之后覆盖有源管芯104的上表面。经二次成型的环氧树脂层216可能太厚，并且因此，可以从上表面移除材料以减薄组件。
在实施例中，有源管芯104或环氧树脂层216中的一个或多个可以被减薄到预定深度。更特别地，有源管芯104和/或环氧树脂层216可以例如通过研磨而从上表面移除材料，使得有源管芯104的上管芯表面220和环氧树脂层216的上环氧树脂表面222在第二横向平面224内共面。作为示例，经二次成型的环氧树脂层216可以具有300μm的厚度，并且减薄操作可以将经二次成型的环氧树脂层216的厚度减小到100μm。有源管芯104的功能部分可以在有源管芯104的底部表面的100μm内，并且因此，有源管芯104可以被研磨直到功能部分上方若干微米的高度。减薄可以暴露有源管芯104的上表面220，使得有源管芯104的轮廓从上方可见。减薄可能或可能未移除足够的经二次成型的环氧树脂层216来暴露第二焊料凸块210。也就是说，在实施例中，第二焊料凸块210足够大到环氧树脂层216的移除暴露第二焊料凸块210的上尖端，使得尖端从上方可见（未示出）。
在操作310处，将载体衬底414安装在有源管芯104和环氧树脂层216上。更特别地，参考图4E，载体衬底414可以安装在上管芯表面220和上环氧树脂表面222上。在实施例中，载体衬底414是由半导体、金属或塑料材料形成的无源晶片。载体衬底414可以通过介于中间的粘合层416而附接到上管芯表面220和上环氧树脂表面222。
载体衬底414可以在减薄操作期间支撑半导体组件。更特别地，半导体组件的上表面可以由载体衬底414保持，而半导体组件的底部表面206被向下研磨。底部表面206的研磨可以将硅晶片106的厚度减小到预定尺寸。更特别地，可以减薄硅晶片106直到将硅通孔407转换成晶片通孔202。也就是说，在研磨之后，晶片通孔202可以从硅晶片106的顶部表面204延伸到硅晶片106的底部表面206。因此，晶片通孔202可以从下方暴露并且可用于连接到重分布层230的重分布线232。
在操作312处，在硅晶片106的底部表面206上形成重分布层230。参考图4F，重分布层230包括重分布线232，其电气连接到从顶部表面204处的第一焊料凸块208延伸到底部表面206的晶片通孔202。重分布层230可以本质上充当附接到硅晶片106的衬底。重分布层230可以包括介电层到铜互连结构的构建，并且因此，重分布层230可以将电气信号从晶片通孔202扇出。信号扇出对于防止半导体封装102中的信号跳变和/或信号噪声而言可能是必要的。在某种意义上，重分布层230可以执行类似于有机嵌入式迹线衬底的功能。然而，重分布层230可以被以更紧凑的线宽和线间隔图案（即，更精细的L/S图案）来制造，并且因此重分布层230可以提供比有机嵌入式迹线衬底高的信号完整性。
在操作314处，将载体衬底414从上管芯表面220和上环氧树脂表面222移除。参考图4G，可以在形成环氧树脂层216中的孔218之前移除载体衬底414。类似地，可以在形成重分布层230上的焊料球116之前移除载体衬底414。在移除载体衬底414之前在重分布层230上形成焊料球116可以是可能的，然而，由于焊料的熔点可能大于粘合层416的熔点，因此可能更切实际的是首先移除载体衬底414。
在剥离载体衬底414之后，可以切割第一晶片区404和第二晶片区406。各个半导体封装102的切割可以包括切穿切割沟槽402。可以将经切割的半导体封装102放置到带和盘装备中，即如本领域中已知的带-盘管芯分类工艺，以用于进一步处理。
在操作316处，在第二焊料凸块210上方在环氧树脂层216中形成孔218。参考图4H，孔218从半导体封装102的上表面（例如，上环氧树脂表面222）竖直向下延伸，并且第二焊料凸块210通过孔218暴露。可以使用穿过成型（through-mold）钻孔操作来形成孔218，如本领域中已知的。钻孔得到的孔218可以打开在第二焊料凸块210和意图连接到芯片到晶片互连114的其它焊料凸块上方的空间。因此，第二焊料凸块210可以从通孔218上方暴露。
在操作318处，在重分布层230上形成若干焊料球116。参考图4I，焊料球116电气连接到重分布层230的重分布线232。可以在球附接工艺中形成焊料球116以创建用于半导体封装102到印刷电路板110的附接的焊料互连。因此，可以提供集成的堆叠封装结构，即具有有源管芯104和外部管芯108底座（第二焊料凸块210）的半导体封装102。
外部管芯108，例如外部存储器管芯，可以附接到图4I中所示的半导体封装102。尽管未示出外部管芯108到半导体封装102的附接操作，但是将理解，外部管芯108的I/O接触件112可以通过贯穿孔218的芯片到晶片互连114连接到第二焊料凸块210。这样的连接可以通过焊料回流工艺来做出，所述焊料回流工艺将第二焊料凸块210附接到电气连接至I/O接触件112的引脚、导线等。因此，外部管芯108到半导体封装102的附接可以形成具有WL-CSP部件的堆叠封装组件。
图5是依照实施例的计算机***的示意图。如所描绘的计算机***500（还称为电子***500）可以体现根据如在本公开中阐述的若干所公开的实施例及其等同物中的任一个的包括硅晶片上的有源管芯和外部管芯底座的半导体封装。计算机***500可以是诸如上网本计算机之类的移动设备。计算机***500可以是诸如无线智能电话之类的移动设备。计算机***500可以是台式计算机。计算机***500可以是手持阅读器。计算机***500可以是服务器***。计算机***500可以是超级计算机或高性能计算***。
在实施例中，电子***500是包括电气耦合电子***500的各种部件的***总线520的计算机***。根据各种实施例，***总线520是单个总线或总线的任何组合。电子***500包括向集成电路510提供电力的电压源530。在一些实施例中，电压源530通过***总线520向集成电路510供应电流。
根据实施例，集成电路510电气耦合到***总线520并且包括任何电路或电路的组合。在实施例中，集成电路510包括处理器512，所述处理器512可以是任何类型的。如本文中使用的，处理器512可以意味着任何类型的电路，诸如但不限于微处理器、微控制器、图形处理器、数字信号处理器或另一处理器。在实施例中，处理器512包括半导体封装或与其耦合，所述半导体封装包括硅晶片上的有源管芯和外部管芯底座，如本文中公开的那样。在实施例中，在处理器的存储器高速缓存中找到SRAM实施例。可以被包括在集成电路510中的其它类型的电路是定制电路或专用集成电路（ASIC），诸如用于在诸如蜂窝电话、智能电话、寻呼机、便携式计算机、双向无线电设备和类似的电子***之类的无线设备中使用的通信电路514，或用于服务器的通信电路。在实施例中，集成电路510包括管芯上存储器516，诸如静态随机存取存储器（SRAM）。在实施例中，集成电路510包括嵌入式的管芯上存储器516，诸如嵌入式动态随机存取存储器（eDRAM）。
在实施例中，用随后的集成电路511补充集成电路510。有用的实施例包括双处理器513和双通信电路515以及诸如SRAM之类的双管芯上存储器517。在实施例中，双集成电路511包括嵌入式的管芯上存储器517，诸如eDRAM。
在实施例中，电子***500还包括外部存储器540，所述外部存储器540进而可以包括适合于特定应用的一个或多个存储器元件，诸如以RAM的形式的主存储器542、一个或多个硬盘驱动器544，和/或处置诸如磁盘、致密盘（CD）、数字可变盘（DVD）、闪速存储器驱动器和本领域中已知的其它可移除介质之类的可移除介质546的一个或多个驱动器。根据实施例，外部存储器540还可以是嵌入式存储器548，诸如管芯堆叠中的第一管芯。
在实施例中，电子***500还包括显示设备550和音频输出560。在实施例中，电子***500包括诸如控制器570之类的输入设备，其可以是键盘、鼠标、跟踪球、游戏控制器、麦克风、语音识别设备或向电子***500中输入信息的任何其它输入设备。在实施例中，输入设备570是相机。在实施例中，输入设备570是数字声音记录器。在实施例中，输入设备570是相机和数字声音记录器。
如本文中示出的，可以在数个不同的实施例中实现集成电路510，其包括根据若干所公开的实施例及其等同物中的任一个的包括硅晶片上的有源管芯和外部管芯底座的半导体封装、电子***、计算机***、制作集成电路的一个或多个方法以及制作电子组件的一个或多个方法，所述电子组件包括根据如本文在各种实施例及其领域所认识到的等同物中阐述的若干所公开的实施例中的任一个的包括硅晶片上的有源管芯和外部管芯底座的半导体封装。元件、材料、几何形状、尺寸和操作的序列都可以被改变以适应特定I/O耦合要求，其包括用于微电子管芯的阵列接触件数量、阵列接触件配置，所述微电子管芯被嵌入在根据若干所公开的半导体封装及其等同物中的任一个的处理器安装衬底中，所述半导体封装包括硅晶片上的有源管芯和外部管芯底座。可以包括基础衬底，如通过图5的虚线所表示的。还可以包括无源器件，如同样在图5中所描绘的。
以上描述了包括硅晶片上的有源管芯和外部管芯底座的半导体封装的实施例。在实施例中，一种半导体封装包括具有从顶部表面延伸到底部表面的晶片通孔的硅晶片。该半导体封装包括顶部表面上的第一焊料凸块和第二焊料凸块。该半导体封装包括安装在硅晶片上的有源管芯。有源管芯通过第一焊料凸块而附接到硅晶片。该半导体封装包括横向围绕有源管芯并且在顶部表面之上的环氧树脂层。环氧树脂层包括从有源管芯横向向外贯穿环氧树脂层的孔。第二焊料凸块通过该孔暴露。
在一个实施例中，第一焊料凸块和第二焊料凸块在平行于顶部表面的横向平面内共面。
在一个实施例中，有源管芯包括上管芯表面。环氧树脂层包括上环氧树脂表面。上管芯表面和上环氧树脂表面在从所述横向平面竖直偏移的第二横向平面内共面。
在一个实施例中，第一焊料凸块小于第二焊料凸块。
在一个实施例中，第一焊料凸块是经电镀的焊料凸块。第二焊料凸块是经顶侧球附接的焊料凸块。
在一个实施例中，半导体封装包括安装在底部表面上的重分布层。重分布层包括若干重分布线。重分布线中的至少一个被电气连接到晶片通孔。半导体封装包括重分布层上的若干焊料球。所述若干焊料球被电气连接到所述若干重分布线。
在一个实施例中，硅晶片是具有一个或多个集成电路的有源硅晶片。
在实施例中，一种半导体封装组件包括半导体封装，其包括具有从顶部表面延伸到底部表面的晶片通孔的硅晶片、顶部表面上的第一焊料凸块和第二焊料凸块、以及安装在硅晶片上的有源管芯。有源管芯通过第一焊料凸块而附接到硅晶片。半导体封装包括横向围绕有源管芯并且在顶部表面之上的环氧树脂层。环氧树脂层包括从有源管芯横向向外贯穿环氧树脂层的孔。第二焊料凸块通过该孔暴露。半导体封装组件包括具有通过该孔而电气连接到第二焊料凸块的I/O接触件的外部存储器管芯。
在一个实施例中，第一焊料凸块和第二焊料凸块在平行于顶部表面的横向平面内共面。
在一个实施例中，有源管芯包括上管芯表面。环氧树脂层包括上环氧树脂表面。上管芯表面和上环氧树脂表面在从所述横向平面竖直偏移的第二横向平面内共面。
在一个实施例中，第一焊料凸块小于第二焊料凸块。
在一个实施例中，第一焊料凸块是经电镀的焊料凸块。第二焊料凸块是经顶侧球附接的焊料凸块。
在一个实施例中，半导体封装组件包括安装在底部表面上的重分布层。重分布层包括若干重分布线。重分布线中的至少一个电气连接到晶片通孔。半导体封装组件包括重分布层上的若干焊料球。所述若干焊料球被电气连接到所述若干重分布线。
在一个实施例中，半导体封装组件包括具有若干接触垫的印刷电路板。所述若干焊料球安装在所述若干接触垫上。
在实施例中，一种制作包括硅晶片上的有源管芯和外部管芯底座的半导体封装的方法包括在硅晶片的顶部表面上形成第一焊料凸块和第二焊料凸块。该方法包括通过第一焊料凸块将有源管芯附接到顶部表面。该方法包括横向围绕有源管芯并且在第二焊料凸块之上沉积环氧树脂层。该方法包括在第二焊料凸块上方在环氧树脂层中形成孔。第二焊料凸块通过该孔暴露。
在一个实施例中，第一焊料凸块小于第二焊料凸块。
在一个实施例中，该方法包括减薄有源管芯或环氧树脂层中的一个或多个，使得有源管芯的上管芯表面和环氧树脂层的上环氧树脂表面在横向平面内共面。
在一个实施例中，该方法包括在上管芯表面和上环氧树脂表面上安装载体衬底。该方法包括在底部表面上形成重分布层。重分布层包括若干重分布线。重分布线中的至少一个被电气连接到从顶部表面处的第一焊料凸块延伸到底部表面的晶片通孔。
在一个实施例中，该方法包括从上管芯表面和上环氧树脂表面移除载体衬底。该方法包括在重分布层上形成若干焊料球。所述若干焊料球被电气连接到所述若干重分布线。
在一个实施例中，在形成所述孔和形成所述若干焊料球之前移除载体衬底。

Claims (20)

1.一种半导体封装，包括：
具有从顶部表面延伸到底部表面的晶片通孔的硅晶片；
顶部表面上的第一焊料凸块和第二焊料凸块；
安装在硅晶片上的有源管芯，其中有源管芯通过第一焊料凸块而附接到硅晶片；以及
横向围绕有源管芯并且在顶部表面之上的环氧树脂层，其中环氧树脂层包括从有源管芯横向向外贯穿环氧树脂层的孔，并且其中第二焊料凸块通过所述孔暴露。
2.根据权利要求1所述的半导体封装，其中第一焊料凸块和第二焊料凸块在平行于顶部表面的横向平面内共面。
3.根据权利要求2所述的半导体封装，其中有源管芯包括上管芯表面，其中环氧树脂层包括上环氧树脂表面，并且其中上管芯表面和上环氧树脂表面在从所述横向平面竖直偏移的第二横向平面内共面。
4.根据权利要求1所述的半导体封装，其中第一焊料凸块小于第二焊料凸块。
5.根据权利要求4所述的半导体封装，其中第一焊料凸块是经电镀的焊料凸块，并且其中第二焊料凸块是经顶侧球附接的焊料凸块。
6.根据权利要求1所述的半导体封装，还包括：
安装在底部表面上的重分布层，其中重分布层包括多个重分布线，并且其中重分布线中的至少一个被电气连接到晶片通孔；以及
重分布层上的多个焊料球，其中所述多个焊料球被电气连接到所述多个重分布线。
7.根据权利要求1所述的半导体封装，其中硅晶片是具有一个或多个集成电路的有源硅晶片。
8.一种半导体封装组件，包括：
半导体封装，其包括
具有从顶部表面延伸到底部表面的晶片通孔的硅晶片，
顶部表面上的第一焊料凸块和第二焊料凸块，
安装在硅晶片上的有源管芯，其中有源管芯通过第一焊料凸块而附接到硅晶片，以及
横向围绕有源管芯并且在顶部表面之上的环氧树脂层，其中环氧树脂层包括从有源管芯横向向外贯穿环氧树脂层的孔，并且其中第二焊料凸块通过所述孔暴露；以及
具有通过所述孔而电气连接到第二焊料凸块的I/O接触件的外部存储器管芯。
9.根据权利要求8所述的半导体封装组件，其中第一焊料凸块和第二焊料凸块在平行于顶部表面的横向平面内共面。
10.根据权利要求9所述的半导体封装组件，其中有源管芯包括上管芯表面，其中环氧树脂层包括上环氧树脂表面，并且其中上管芯表面和上环氧树脂表面在从所述横向平面竖直偏移的第二横向平面内共面。
11.根据权利要求8所述的半导体封装组件，其中第一焊料凸块小于第二焊料凸块。
12.根据权利要求11所述的半导体封装组件，其中第一焊料凸块是经电镀的焊料凸块，并且其中第二焊料凸块是经顶侧球附接的焊料凸块。
13.根据权利要求8所述的半导体封装组件，还包括：
安装在底部表面上的重分布层，其中重分布层包括多个重分布线，并且其中重分布线中的至少一个被电气连接到晶片通孔；以及
重分布层上的多个焊料球，其中所述多个焊料球被电气连接到所述多个重分布线。
14.根据权利要求13所述的半导体封装组件，还包括具有多个接触垫的印刷电路板，其中所述多个焊料球安装在所述多个接触垫上。
15.一种方法，包括：
在硅晶片的顶部表面上形成第一焊料凸块和第二焊料凸块；
通过第一焊料凸块将有源管芯附接到顶部表面；
横向围绕有源管芯并且在第二焊料凸块之上沉积环氧树脂层；以及
在第二焊料凸块上方在环氧树脂层中形成孔，其中第二焊料凸块通过所述孔暴露。
16.根据权利要求15所述的方法，其中第一焊料凸块小于第二焊料凸块。
17.根据权利要求15所述的方法，还包括：
减薄有源管芯或环氧树脂层中的一个或多个，使得有源管芯的上管芯表面和环氧树脂层的上环氧树脂表面在横向平面内共面。
18.根据权利要求17所述的方法，还包括：
在上管芯表面和上环氧树脂表面上安装载体衬底；以及
在底部表面上形成重分布层，其中重分布层包括若干重分布线，并且其中重分布线中的至少一个被电气连接到从顶部表面处的第一焊料凸块延伸到底部表面的晶片通孔。
19.根据权利要求18所述的方法，还包括：
从上管芯表面和上环氧树脂表面移除载体衬底；以及
在重分布层上形成多个焊料球，其中所述多个焊料球被电气连接到所述多个重分布线。
20.根据权利要求19所述的方法，其中在形成所述孔和形成所述多个焊料球之前移除载体衬底。
CN201680091229.8A 2016-12-29 2016-12-29 具有晶片级有源管芯和外部管芯底座的半导体封装 Pending CN109983570A (zh)

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