CN109980056B - Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof - Google Patents

Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof Download PDF

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CN109980056B
CN109980056B CN201910152555.0A CN201910152555A CN109980056B CN 109980056 B CN109980056 B CN 109980056B CN 201910152555 A CN201910152555 A CN 201910152555A CN 109980056 B CN109980056 B CN 109980056B
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quantum well
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well layer
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CN109980056A (en
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刘旺平
乔楠
吕蒙普
胡加辉
李鹏
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

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Abstract

The invention discloses a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the technical field of semiconductors. The GaN-based light emitting diode epitaxial wafer comprises a substrate, and a low-temperature buffer layer, a three-dimensional nucleation layer, a two-dimensional recovery layer, an undoped GaN layer, an N-type layer, a stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer which are sequentially grown on the substrate, wherein the stress release layer comprises a plurality of first superlattice structures and second superlattice structures which alternately grow, the first superlattice structures are low-temperature InGaN/GaN superlattice structures, and the second superlattice structures are high-temperature InGaN/GaN superlattice structures. The light-emitting diode epitaxial wafer provided by the invention can optimize the opening size of the V-shaped pit, improve the internal quantum light-emitting efficiency of the LED and simultaneously improve the crystal quality of the epitaxial layer.

Description

Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof.
Background
An LED (Light Emitting Diode) is a semiconductor electronic component capable of Emitting Light. As a novel high-efficiency, environment-friendly and green solid-state illumination light source, the LED is being rapidly and widely applied to the fields such as traffic signal lamps, automobile interior and exterior lamps, urban landscape illumination, mobile phone backlight sources and the like.
The epitaxial wafer is a main component of the LED, and the existing GaN-based LED epitaxial wafer comprises a sapphire substrate, and a low-temperature buffer layer, a three-dimensional nucleating layer, a two-dimensional recovery layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer which are sequentially stacked on the sapphire substrate. Due to the fact that large lattice mismatch exists between the sapphire substrate and the GaN epitaxial layer, stress can be generated in the epitaxial layer, a large number of threading dislocations are generated, and the stress and the threading dislocations extend into the multiple quantum well layer along the lamination direction of the epitaxial wafer and can seriously affect the light emission of the LED. In order to improve the light emitting efficiency of the LED, a stress release layer is usually disposed between the N-type layer and the mqw layer to release the stress of the bottom layer and reduce the generation of dislocations.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the stress release layer in the prior art is usually grown under the low-temperature and constant-temperature condition so as to ensure the stress release effect. And the threading dislocation may induce the formation of V-shaped pit under low temperature condition, and the lateral epitaxial ability of GaN may be deteriorated and the opening of V-shaped pit may be gradually increased under low temperature condition. When the opening of the V-shaped pit is too large, the barrier height of the inclined surface of the V-shaped pit is reduced, the carrier limiting capability is weakened, non-radiative recombination can be carried out between electrons and holes, and the internal quantum light-emitting efficiency of the LED is reduced. Meanwhile, under the low temperature condition, the density of the formed V-shaped pits is gradually increased, thereby causing the crystal quality of the epitaxial layer to be reduced.
Disclosure of Invention
The embodiment of the invention provides a gallium nitride-based light-emitting diode epitaxial wafer and a manufacturing method thereof, which can optimize the opening size of a V-shaped pit, improve the internal quantum light-emitting efficiency of an LED and simultaneously improve the crystal quality of an epitaxial layer. The technical scheme is as follows:
in one aspect, the invention provides a gallium nitride-based light emitting diode epitaxial wafer, which comprises a substrate, and a low-temperature buffer layer, a three-dimensional nucleation layer, a two-dimensional recovery layer, an undoped GaN layer, an N-type layer, a stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer which are sequentially grown on the substrate,
the stress release layer comprises a plurality of first superlattice structures and a plurality of second superlattice structures which are alternately grown, the first superlattice structures are low-temperature InGaN/GaN superlattice structures, and the second superlattice structures are high-temperature InGaN/GaN superlattice structures.
Furthermore, the thickness of the stress release layer is 100-150 nm.
Further, the multiple quantum well layer comprises a first type multiple quantum well layer close to the N-type layer, a third type multiple quantum well layer close to the P-type layer, and a second type multiple quantum well layer between the first type multiple quantum well layer and the third type multiple quantum well layer;
the first type multi-quantum well layer consists of In with multiple periodsaGa1-aN/AlcGa1-cN superlattice, the second type multiple quantum well layer is composed of multiple periods of InaGa1-aThe third type multiple quantum well layer consists of In with multiple periodsaGa1-aN/InbGa1-bComposition of N superlattice, 0.1<a<1，0<b<0.3，b<a，0<c<0.2。
Further, In the first, second and third types of quantum well layersaGa1-aThe N layers are all equal in thickness.
Further, Al in the first-type quantum well layercGa1-cAn N layer, a GaN layer In the second type of quantum well layer, and In the third type of quantum well layerbGa1-bThe N layers are all equal in thickness.
In another aspect, the present invention provides a method for manufacturing an epitaxial wafer of a gallium nitride-based light emitting diode, the method comprising:
providing a substrate;
growing a low-temperature buffer layer, a three-dimensional nucleating layer, a two-dimensional recovery layer, an undoped GaN layer and an N-type layer on the substrate in sequence;
growing a stress release layer on the N-type layer, wherein the stress release layer comprises a plurality of first superlattice structures and second superlattice structures which are alternately grown, the first superlattice structures are low-temperature InGaN/GaN superlattice structures, and the second superlattice structures are high-temperature InGaN/GaN superlattice structures;
and sequentially growing a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer on the stress release layer.
Further, growing a stress relief layer on the N-type layer, comprising:
growing the first superlattice structure at a temperature of 780-880 ℃;
growing the second superlattice structure at a temperature of 830-930 ℃.
Further, the multiple quantum well layer comprises a first type multiple quantum well layer close to the N-type layer, a third type multiple quantum well layer close to the P-type layer, and a second type multiple quantum well layer between the first type multiple quantum well layer and the third type multiple quantum well layer;
the first type multi-quantum well layer consists of In with multiple periodsaGa1-aN/AlcGa1-cN superlattice, the second type multiple quantum well layer is composed of multiple periods of InaGa1-aThe third type multiple quantum well layer consists of In with multiple periodsaGa1-aN/InbGa1-bComposition of N superlattice, 0.1<a<1，0<b<0.3，b<a，0<c<0.2。
Further, In the first, second and third types of quantum well layersaGa1-aThe N layers are all equal in thickness.
Further, Al in the first-type quantum well layercGa1-cAn N layer, a GaN layer In the second type of quantum well layer, and In the third type of quantum well layerbGa1-bThe N layers are all equal in thickness.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
by providing the stress relieving layer to include a plurality of first superlattice structures and second superlattice structures that are alternately grown. The first superlattice structure is a low-temperature InGaN/GaN superlattice structure, and is formed by low-temperature growth, so that the stress release layer can be guaranteed to have a good stress release effect. However, the first superlattice structure can cause the formation of the V-shaped pit when grown at low temperature, so that the second superlattice structure is grown after the first superlattice structure, the second superlattice structure is a high-temperature InGaN/GaN superlattice structure, the transverse epitaxial capability of GaN is enhanced under the high-temperature condition, and the opening of the V-shaped pit can be inhibited from continuously becoming larger, so that the opening of the V-shaped pit is controlled within a proper range, and the phenomenon that the internal quantum luminous efficiency of the LED is reduced due to the fact that the opening of the V-shaped pit is too large is avoided. Meanwhile, under the high-temperature condition, the density of the formed V-shaped pits is gradually reduced, so that the crystal quality of the epitaxial layer can be improved. And the stress release layer in the invention comprises a plurality of alternately grown low-temperature InGaN/GaN superlattice structures and high-temperature InGaN/GaN superlattice structures, and compared with the stress release layer with a single-layer structure (namely only one low-temperature InGaN/GaN superlattice structure and one high-temperature InGaN/GaN superlattice structure), the control effect on the opening of the V-shaped pit is better.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of an opening structure of a V-type pit in a multiple quantum well layer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an epitaxial wafer of a gallium nitride-based light emitting diode according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a multiple quantum well layer provided by an embodiment of the present invention;
fig. 4 is a flowchart of a method for manufacturing an epitaxial wafer of a gallium nitride-based light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic view of an opening structure of a V-type pit in a multiple quantum well layer according to an embodiment of the present invention, where as shown in fig. 1, Δ L in fig. 1 represents a diffusion distance from a center of threading dislocation to an edge of the V-type pit, and Δ E represents a barrier height of a quantum well on an inclined surface of the V-type pit. Due to the fact that large lattice mismatch exists between the sapphire substrate and the GaN epitaxial layer, a large amount of threading dislocation can be generated, the threading dislocation can be used as a leakage channel of carriers, and then a small amount of carriers are captured to form a non-radiative recombination center, and therefore the luminous efficiency of the LED is reduced. The threading dislocation initiates the formation of V-pits at low temperature.
When the opening of the V-shaped pit is too small, the Delta L is smaller, and the diffusion distance from the threading dislocation center to the edge of the V-shaped pit is relatively shorter, so that carriers are more easily captured and enter the threading dislocation center; the delta E is large, the inclined surface of the V-shaped pit has a higher potential barrier and stronger carrier limiting capacity, and a non-radiation center of threading dislocation can be effectively passivated.
When the opening of the V-shaped pit is too large, the Delta L is larger, the diffusion distance from the threading dislocation center to the edge of the V-shaped pit is relatively longer, and a carrier can be inhibited from entering a non-radiative recombination center; the delta E is small, the potential barrier height of the inclined surface of the V-shaped pit is reduced, the limiting capability of a carrier is weakened, threading dislocation still can be used as a leakage channel of the carrier, and then a small part of the carrier is captured to form a non-radiative recombination center, so that the luminous efficiency of the LED is reduced.
Therefore, the light emitting efficiency of the LED is affected by the opening of the V-shaped pit being too large or too small. The embodiment of the invention provides a gallium nitride-based light-emitting diode epitaxial wafer and a manufacturing method thereof, which can optimize the opening size of a V-shaped pit, improve the internal quantum light-emitting efficiency of an LED and simultaneously improve the crystal quality of an epitaxial layer.
Fig. 2 is a schematic structural diagram of a GaN-based light emitting diode epitaxial wafer according to an embodiment of the present invention, and as shown in fig. 2, the GaN-based light emitting diode epitaxial wafer includes a substrate 1, and a low temperature buffer layer 2, a three-dimensional nucleation layer 3, a two-dimensional recovery layer 4, an undoped GaN layer 5, an N-type layer 6, a stress release layer 7, a multi-quantum well layer 8, an electron blocking layer 9, a P-type layer 10, and a P-type contact layer 11 sequentially grown on the substrate 1.
The stress release layer 7 includes a plurality of first superlattice structures 71 and second superlattice structures 72 alternately grown, the first superlattice structures 71 being low temperature InGaN/GaN superlattice structures, and the second superlattice structures 72 being high temperature InGaN/GaN superlattice structures.
Embodiments of the present invention provide for a stress relief layer to include a plurality of first and second superlattice structures that are alternately grown. The first superlattice structure is a low-temperature InGaN/GaN superlattice structure, and is formed by low-temperature growth, so that the stress release layer can be guaranteed to have a good stress release effect. However, the first superlattice structure can cause the formation of the V-shaped pit when grown at low temperature, so that the second superlattice structure is grown after the first superlattice structure, the second superlattice structure is a high-temperature InGaN/GaN superlattice structure, the transverse epitaxial capability of GaN is enhanced under the high-temperature condition, and the opening of the V-shaped pit can be inhibited from continuously becoming larger, so that the opening of the V-shaped pit is controlled within a proper range, and the phenomenon that the internal quantum luminous efficiency of the LED is reduced due to the fact that the opening of the V-shaped pit is too large is avoided. Meanwhile, under the high-temperature condition, the density of the formed V-shaped pits is gradually reduced, so that the crystal quality of the epitaxial layer can be improved. And the stress release layer in the invention comprises a plurality of alternately grown low-temperature InGaN/GaN superlattice structures and high-temperature InGaN/GaN superlattice structures, and compared with the stress release layer with a single-layer structure (namely only one low-temperature InGaN/GaN superlattice structure and one high-temperature InGaN/GaN superlattice structure), the control effect on the opening of the V-shaped pit is better.
It should be noted that, in this embodiment, a better V-pit opening size can be derived through the inversion of the light emitting efficiency, wherein the effect of controlling the opening diameter of the V-pit to be between 200 nm and 300nm is better.
Optionally, the stress relieving layer 7 includes N first superlattice structures 71 and second superlattice structures 72 alternately grown, 2 ≦ N ≦ 12. If the number of N is too large, the number of times of switching between low temperature and high temperature is large, and if the number of N is too small, the opening of the V-shaped pit cannot be effectively controlled.
Exemplarily, N-8. At the moment, the opening of the V-shaped pit can be effectively controlled, and the growth process of the stress release layer is not too complicated.
Further, the low-temperature InGaN layer 71a In the first superlattice structure 71 and the high-temperature InGaN layer 72a In the second superlattice structure 72 are both InxGa1-xN layer, 0.05<x<0.4. When the In content is within the value range, the stress releasing layer has the best effect of releasing stress.
Optionally, the thicknesses of the first superlattice structure 71 and the second superlattice structure 72 are equal to facilitate periodic control of the growth of the stress relieving layer such that the opening of the V-pits and the density of the V-pits are uniformly varied.
Illustratively, the thickness of the low-temperature InGaN layer 71a in the first superlattice structure 71 and the thickness of the high-temperature InGaN layer 72a in the second superlattice structure 72 are both 1-2 nm. The thickness of the GaN layer 71b in the first superlattice structure 71 and the thickness of the GaN layer 72b in the second superlattice structure 72 are both 10-40 nm.
In other implementations, the thicknesses of the first and second superlattice structures 71, 72 may also be unequal.
Further, the thickness of the stress release layer 7 is 100 to 150 nm. If the thickness of the stress relaxation layer 7 is too thick, the crystal quality of the stress relaxation layer 7 is deteriorated, and if the thickness of the stress relaxation layer 7 is too thick, the stress relaxation layer does not function to relax the stress. The thickness of the stress release layer 7 is set to be 100-150 nm, so that the bottom layer stress can be well released while the crystal quality of the stress release layer 7 is guaranteed.
Fig. 3 is a schematic structural diagram of a mqw layer according to an embodiment of the present invention, and as shown in fig. 3, the mqw layer 8 includes a first mqw layer 81 close to the N-type layer 6, a third mqw layer 83 close to the P-type layer 10, and a second mqw layer 82 between the first mqw layer 81 and the third mqw layer 83.
The first-type MQW layer 81 consists of multiple periods of InaGa1-aN/AlcGa1-cN-type superlattice, and the second type multiple quantum well layer 82 is composed of multiple periods of InaGa1-aN/GaN superlattice, and the third type multiple quantum well layer 83 is composed of multiple periods of InaGa1- aN/InbGa1-bComposition of N superlattice, 0.1<a<1，0<b<0.3，b<a，0<c<0.2。
Due to AlGaN, GaN, InbGa1-bThe forbidden band widths of the three materials are in the following size relationship: InGaN < GaN < AlGaN. Therefore, the growth rate of the V-shaped pit formed in the stress relaxation layer 7 is gradually reduced in the three materials of InGaN, GaN, and AlGaN. Therefore, AlGaN is used as a barrier layer in the first multi-quantum well layer 81 close to the N-type layer 6, the growth rate of the V-pit is slow, and it is possible to suppress the V-pit from being opened too quickly and becoming large from the beginning, and avoid the opening becoming too large when the V-pit extends to the multi-quantum well layer 8 close to the P-type layer 10, and then GaN and InGaN are used as barrier layers in sequence in the second multi-quantum well layer 82 and the third multi-quantum well layer 83, and it is possible to prevent the opening of the V-pit from being too small. When the opening of the V-pit is too small, the diffusion distance of threading dislocation to the edge of the V-pit is short, so that carriers are more easily trapped into the threading dislocation center.
Further, In the first, second and third type quantum well layers 81, 82 and 83aGa1-aThe thicknesses of the N layers are equal, so that the consistency of the light-emitting wavelength can be ensured.
Alternatively, In the first-type quantum well layer 81aGa1-aN layer 81a, In the second type quantum well layer 82aGa1-aN layer 82a, In the third type quantum well layer 83aGa1-aThe thickness of the N layer is 3-4 nm.
Further, Al in the first-type quantum well layer 81cGa1-cN layer 81b, GaN layer 82b In the second type quantum well layer 82, and In the third type quantum well layer 83bGa1-bThe N layers 83b are all of equal thickness to facilitate growth control of the opening size of the V-pits.
In other implementations, Al in the first-type quantum well layer 81cGa1-cN layer 81b, GaN layer 82b In the second type quantum well layer 82, and In the third type quantum well layer 83bGa1-bThe thicknesses of the N layers 83b may also be unequal.
Optionally, of the first typeAl in quantum well layer 81cGa1-cN layer 81b, GaN layer 82b In the second type quantum well layer 82, and In the third type quantum well layer 83bGa1-bThe thickness of the N layer 83b is 9-20 nm.
Alternatively, the substrate 1 may be a sapphire substrate.
Alternatively, the low-temperature buffer layer 2 may be an AlN buffer layer, or a GaN buffer layer.
Optionally, the three-dimensional nucleation layer 3 may be a GaN layer with a thickness of 400-600 nm.
Optionally, the two-dimensional recovery layer 4 may be a GaN layer with a thickness of 500-800 nm.
Optionally, the thickness of the undoped GaN layer 5 is 1-2 um.
Optionally, the N-type layer 6 can be a Si-doped GaN layer with a thickness of 1-2 um.
Optionally, the thickness of the electron blocking layer 9 may be 20 to 100 nm.
Optionally, the P-type layer 10 may be a GaN layer with a thickness of 100 to 300 nm.
Optionally, the light emitting diode epitaxial wafer may further include a P-type contact layer 11 disposed on the P-type layer 10. The P-type contact layer 11 can be a heavily Mg-doped GaN layer with a thickness of 50-100 nm.
Fig. 4 is a flowchart of a method for manufacturing an epitaxial wafer of a gallium nitride-based light emitting diode according to an embodiment of the present invention, and as shown in fig. 4, the method includes:
step 401, a substrate is provided.
Wherein the substrate can be [0001 ]]Al of crystal orientation2O3A sapphire substrate.
Further, step 401 may further include:
annealing the substrate in a hydrogen atmosphere for 1-10 min to clean the surface of the substrate, and then performing nitridation treatment on the substrate, wherein the temperature during nitridation treatment is controlled to be 1000-1200 ℃.
The annealing treatment mode of the substrate depends on the growth mode of the low-temperature buffer layer.
When PVD (Physical Vapor Deposition) method is adopted to deposit the low-temperature buffer layerIn the method, the annealing the substrate comprises the following steps: and placing the substrate into a reaction cavity of PVD equipment, vacuumizing the reaction cavity, and heating the substrate to raise the temperature while vacuumizing. When the pressure in the reaction chamber is pumped to be lower than 1 x 10-7And (3) stabilizing the heating temperature at 350-750 ℃ in torr, and baking the substrate for 2-12 min.
When the low-temperature buffer layer is deposited using a Metal-organic Chemical Vapor Deposition (MOCVD) method, annealing the substrate includes: the substrate is placed in a reaction cavity of MOCVD equipment, then annealing treatment is carried out for 10 minutes in a hydrogen atmosphere, the surface of the substrate is cleaned, the annealing temperature is between 1000 ℃ and 1100 ℃, and the pressure is between 200torr and 500 torr.
Step 402, growing a low temperature buffer layer on a substrate.
The low-temperature buffer layer may be a GaN buffer layer or an AlN buffer layer.
When the low-temperature buffer layer is a GaN buffer layer, the low-temperature buffer layer may be grown by an MOCVD method, including: firstly, adjusting the temperature in a reaction cavity of MOCVD equipment to 400-600 ℃, adjusting the pressure to 200-600 torr, and growing a GaN buffer layer with the thickness of 15-35 nm.
When the low-temperature buffer layer is an AlN buffer layer, the low-temperature buffer layer may be grown using a PVD method, including: adjusting the temperature in a reaction cavity of the PVD equipment to 400-700 ℃, adjusting the sputtering power to 3000-5000W, adjusting the pressure to 1-10 mtorr, and growing an AlN buffer layer with the thickness of 15-35 nm.
The undoped GaN layer, the N-type layer, the stress release layer, the multi-quantum well layer, the electron blocking layer, the P-type layer, and the P-type contact layer in the epitaxial layer may be grown by MOCVD. In particular implementation, the substrate is generally placed on a graphite tray and fed into the reaction chamber of the MOCVD equipment to carry out the growth of the epitaxial material, so that the temperature and the pressure controlled in the growth process actually refer to the temperature and the pressure in the reaction chamber. Specifically, trimethyl gallium or trimethyl ethyl is used as a gallium source, triethyl boron is used as a boron source, high-purity nitrogen is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, an N-type dopant is selected from silane, and a P-type dopant is selected from magnesium cyclopentadienyl.
And step 403, growing a three-dimensional nucleation layer on the low-temperature buffer layer.
In this embodiment, the three-dimensional nucleation layer may be a GaN layer.
Illustratively, the temperature of the reaction chamber is adjusted to 1000-1050 ℃, the pressure of the reaction chamber is controlled to 300-600 torr, a three-dimensional nucleation layer with the thickness of 400-600 nm is grown, and the growth time is 10-20 min.
Step 404, growing a two-dimensional buffer layer on the three-dimensional nucleation layer.
In this embodiment, the two-dimensional buffer layer may be a GaN layer.
Illustratively, the temperature of the reaction chamber is adjusted to 1050-1150 ℃, the pressure of the reaction chamber is controlled to 100-300 torr, a two-dimensional buffer layer with the thickness of 500-800 nm is grown, and the growth time is 20-40 min.
Step 405, growing an undoped GaN layer on the two-dimensional buffer layer.
Illustratively, the temperature of the reaction chamber is adjusted to 1050-1200 ℃, the pressure of the reaction chamber is controlled to 100-300 torr, and an undoped GaN layer with the thickness of 1-2 um is grown.
Step 406, an N-type layer is grown on the undoped GaN layer.
In this embodiment, the N-type layer may be a Si-doped GaN layer, and the Si doping concentration may be 1018cm-3～1020cm-3。
Illustratively, the temperature of the reaction chamber is adjusted to 1050-1200 ℃, the pressure of the reaction chamber is controlled to 100-300 torr, and an N-type layer with the thickness of 1-2 um is grown.
Step 407, grow a stress release layer on the N-type layer.
In this embodiment, the stress release layer includes a plurality of first superlattice structures and a plurality of second superlattice structures that are alternately grown, the first superlattice structures are low-temperature InGaN/GaN superlattice structures, and the second superlattice structures are high-temperature InGaN/GaN superlattice structures.
Optionally, the stress release layer comprises N first superlattice structures and N second superlattice structures which are alternately grown, and N is larger than or equal to 2 and smaller than or equal to 12.
Further, the low temperature InGaN layer In the first superlattice structure and the high temperature InGaN layer In the second superlattice structure are both InxGa1-xN layer, 0.05<x<0.4。
Optionally, the thicknesses of the first superlattice structure 71 and the second superlattice structure 72 are equal to facilitate periodic control of the growth of the stress relieving layer such that the opening of the V-pits and the density of the V-pits are uniformly varied.
Illustratively, the thickness of the low-temperature InGaN layer in the first superlattice structure and the thickness of the high-temperature InGaN layer in the second superlattice structure are both 1-2 nm. The thickness of the GaN layer in the first superlattice structure and the thickness of the GaN layer in the second superlattice structure are both 10-40 nm.
In other implementations, the thicknesses of the first and second superlattice structures 71, 72 may also be unequal.
Furthermore, the thickness of the stress release layer is 100-150 nm.
Illustratively, step 407 may include:
growing a first superlattice structure at 780-880 ℃.
Growing a second superlattice structure at a temperature of 830-930 ℃.
Illustratively, the pressure of the reaction chamber is controlled within 100-500 torr, and a stress release layer is grown.
Step 408, growing a multiple quantum well layer on the stress relief layer.
The multiple quantum well layer comprises a first multiple quantum well layer close to the N-type layer, a third multiple quantum well layer close to the P-type layer, and a second multiple quantum well layer located between the first multiple quantum well layer and the third multiple quantum well layer.
The first type of multi-quantum well layer consists of In with multiple periodsaGa1-aN/AlcGa1-cN-type superlattice, the second type multiple quantum well layer is composed of multiple periods of InaGa1-aN/GaN superlattice, and the third multiple quantum well layer is composed of multiple periods of InaGa1-aN/InbGa1-bN superlattice composition，0.1<a<1，0<b<0.3，b<a，0<c<0.2。
Further, In the first, second and third type quantum well layersaGa1-aThe thicknesses of the N layers are equal, so that the consistency of the light-emitting wavelength can be ensured.
Illustratively, In the first type quantum well layeraGa1-aN layer, In the second type quantum well layeraGa1-aN layer, In the third type quantum well layeraGa1-aThe thickness of the N layer is 3-4 nm.
Further, Al in the first type quantum well layercGa1-cN layer, GaN layer In second type quantum well layer and In third type quantum well layerbGa1-bThe N layers are all equal in thickness.
Optionally, Al in the first type quantum well layercGa1-cN layer, GaN layer In second type quantum well layer and In third type quantum well layerbGa1-bThe thickness of the N layer is 9-20 nm.
In other implementations, the Al in the first type quantum well layercGa1-cN layer, GaN layer In second type quantum well layer and In third type quantum well layerbGa1-bThe thickness of the N layers may also be unequal.
Optionally, In the first type quantum well layeraGa1-aN layer, In the second type quantum well layeraGa1-aN layer, In the third type quantum well layeraGa1-aThe growth temperature and the growth pressure of the N layer are equal.
Optionally, the AlGaN layer In the first type quantum well layer, the GaN layer In the second type quantum well layer and the In the third type quantum well layerbGa1-bThe growth temperature and the growth pressure of the N layer are equal.
Illustratively, step 408 may include:
controlling the temperature of the reaction chamber to be 750-830 ℃, the pressure of the reaction chamber to be 100-500 torr, and growing In the first type of quantum well layeraGa1-aN layer, second type quantum wellIn the layeraGa1-aN layer, In the third type quantum well layeraGa1-aN layers;
controlling the temperature of the reaction chamber to be 850-900 ℃ and the pressure of the reaction chamber to be 100-500 torr, and growing Al in the first-class quantum well layercGa1-cN layer, GaN layer In second type quantum well layer and In third type quantum well layerbGa1-bAnd N layers.
And step 409, growing an electron barrier layer on the multi-quantum well layer.
In this embodiment, the electron blocking layer may be a P-type AlGaN layer
Illustratively, the temperature of the reaction chamber is adjusted to 800-1000 ℃, the pressure of the reaction chamber is controlled to 50-500 torr, and an electron blocking layer with the thickness of 20-100 nm is grown.
Step 410, a P-type layer is grown on the electron blocking layer.
In this embodiment, the P-type layer is a GaN layer doped with Mg, and the doping concentration of Mg may be 1 × 1019～1×1020cm-3。
Illustratively, the temperature of the reaction chamber is regulated to 850-950 ℃, the pressure of the reaction chamber is controlled to 100-300 torr, and a P-type layer with the thickness of 100-300 nm is grown.
Step 411, grow a P-type contact layer on the P-type layer.
In this embodiment, the P-type contact layer may be a heavily Mg-doped GaN layer.
Illustratively, the temperature of the reaction chamber is regulated to 850-1000 ℃, the pressure of the reaction chamber is controlled to 100-300 torr, and a P-type contact layer with the thickness of 50-100 nm is grown.
After the steps are completed, the temperature of the reaction chamber is reduced to 650-850 ℃, annealing treatment is carried out for 5-15 min in a nitrogen atmosphere, then the temperature is gradually reduced to the room temperature, and the epitaxial growth of the light emitting diode is finished.
Embodiments of the present invention provide for a stress relief layer to include a plurality of first and second superlattice structures that are alternately grown. The first superlattice structure is a low-temperature InGaN/GaN superlattice structure, and is formed by low-temperature growth, so that the stress release layer can be guaranteed to have a good stress release effect. However, the first superlattice structure can cause the formation of the V-shaped pit when grown at low temperature, so that the second superlattice structure is grown after the first superlattice structure, the second superlattice structure is a high-temperature InGaN/GaN superlattice structure, the transverse epitaxial capability of GaN is enhanced under the high-temperature condition, and the opening of the V-shaped pit can be inhibited from continuously becoming larger, so that the opening of the V-shaped pit is controlled within a proper range, and the phenomenon that the internal quantum luminous efficiency of the LED is reduced due to the fact that the opening of the V-shaped pit is too large is avoided. Meanwhile, under the high-temperature condition, the density of the formed V-shaped pits is gradually reduced, so that the crystal quality of the epitaxial layer can be improved. And the stress release layer in the invention comprises a plurality of alternately grown low-temperature InGaN/GaN superlattice structures and high-temperature InGaN/GaN superlattice structures, and compared with the stress release layer with a single-layer structure (namely only one low-temperature InGaN/GaN superlattice structure and one high-temperature InGaN/GaN superlattice structure), the control effect on the opening of the V-shaped pit is better.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (7)

1. A GaN-based light emitting diode epitaxial wafer comprises a substrate, and a low-temperature buffer layer, a three-dimensional nucleation layer, a two-dimensional recovery layer, an undoped GaN layer, an N-type layer, a stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer which are sequentially grown on the substrate,
the stress release layer comprises a plurality of first superlattice structures and second superlattice structures which are alternately grown, the first superlattice structures are low-temperature InGaN/GaN superlattice structures, the second superlattice structures are high-temperature InGaN/GaN superlattice structures, the first superlattice structures are grown under the low-temperature condition of 780 ℃, the second superlattice structures are grown under the high-temperature condition of 930 ℃,
the multiple quantum well layer comprises a first type multiple quantum well layer close to the N-type layer, a third type multiple quantum well layer close to the P-type layer, and a second type multiple quantum well layer located between the first type multiple quantum well layer and the third type multiple quantum well layer;
the first type multi-quantum well layer consists of In with multiple periodsaGa1-aN/AlcGa1-cN superlattice, the second type multiple quantum well layer is composed of multiple periods of InaGa1-aThe third type multiple quantum well layer consists of In with multiple periodsaGa1-aN/InbGa1-bComposition of N superlattice, 0.1<a<1，0<b<0.3，b<a，0<c<0.2。
2. The GaN-based LED epitaxial wafer according to claim 1, wherein the stress release layer has a thickness of 100-150 nm.
3. The GaN-based LED epitaxial wafer of claim 1, wherein In the first, second, and third types of MQWsaGa1-aThe N layers are all equal in thickness.
4. The GaN-based LED epitaxial wafer of claim 3, wherein Al in the first type multiple quantum well layercGa1-cAn N layer, a GaN layer In the second type multiple quantum well layer, and In the third type multiple quantum well layerbGa1-bThe N layers are all equal in thickness.
5. A manufacturing method of a gallium nitride-based light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing a low-temperature buffer layer, a three-dimensional nucleating layer, a two-dimensional recovery layer, an undoped GaN layer and an N-type layer on the substrate in sequence;
growing a stress release layer on the N-type layer, wherein the stress release layer comprises a plurality of first superlattice structures and second superlattice structures which are alternately grown, the first superlattice structures are low-temperature InGaN/GaN superlattice structures, the second superlattice structures are high-temperature InGaN/GaN superlattice structures, the first superlattice structures are grown at 780 ℃ and the second superlattice structures are grown at 930 ℃ and the high temperature;
sequentially growing a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer on the stress release layer;
the multiple quantum well layer comprises a first type multiple quantum well layer close to the N-type layer, a third type multiple quantum well layer close to the P-type layer, and a second type multiple quantum well layer located between the first type multiple quantum well layer and the third type multiple quantum well layer;
the first type multi-quantum well layer consists of In with multiple periodsaGa1-aN/AlcGa1-cN superlattice, the second type multiple quantum well layer is composed of multiple periods of InaGa1-aThe third type multiple quantum well layer consists of In with multiple periodsaGa1-aN/InbGa1-bComposition of N superlattice, 0.1<a<1，0<b<0.3，b<a，0<c<0.2。
6. The manufacturing method according to claim 5, wherein In the first, second, and third type MQW layersaGa1-aThe N layers are all equal in thickness.
7. The method according to claim 5, wherein Al in the MQW layer of the first typecGa1-cAn N layer, a GaN layer In the second type multiple quantum well layer, and In the third type multiple quantum well layerbGa1-bThe N layers are all equal in thickness.
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