CN109979835A - The production method and semiconductor devices of aluminium liner - Google Patents

The production method and semiconductor devices of aluminium liner Download PDF

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Publication number
CN109979835A
CN109979835A CN201910279285.XA CN201910279285A CN109979835A CN 109979835 A CN109979835 A CN 109979835A CN 201910279285 A CN201910279285 A CN 201910279285A CN 109979835 A CN109979835 A CN 109979835A
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CN
China
Prior art keywords
layer
pellumina
aluminium
production method
liner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910279285.XA
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Chinese (zh)
Inventor
王亮
李志伟
冉春明
黄仁德
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Huaian Imaging Device Manufacturer Corp
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Huaian Imaging Device Manufacturer Corp
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Publication date
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Priority to CN201910279285.XA priority Critical patent/CN109979835A/en
Publication of CN109979835A publication Critical patent/CN109979835A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

Technical solution of the present invention discloses the production method and semiconductor devices of a kind of aluminium liner, and the production method of the aluminium liner includes: to form aluminum membranous layer on a semiconductor substrate；Pellumina is formed in the aluminium film layer surface；Dielectric layer is formed on the pellumina；Using dielectric layer described in fluoro-gas dry etching, until exposing the pellumina；The pellumina that wet-cleaning exposes.The pellumina of technical solution of the present invention can be effectively prevented fluorine ion and contact with aluminum membranous layer, fluorine ion is avoided to react the hydrofluoric acid corrosion aluminum membranous layer generated with vapor, advantageous condition is provided for subsequent bonded line, a possibility that considerably reducing routing failure, while also reducing the scrappage of wafer.

Description

The production method and semiconductor devices of aluminium liner
Technical field
The production method and semiconductor devices padded the present invention relates to the manufacturing field of semiconductor devices more particularly to aluminium.
Background technique
In semiconductor integrated circuit manufacturing process, usually semiconductor integrated circuit is integrated on same wafer, wafer On integrated circuit drawn by metal layer, and form liner on top metal layer, connected by padding with external circuit, Therefore, the manufacture craft of liner is most important for entire semiconductor integrated circuit.
The prior art is when making liner in wafer substrate, it will usually the dielectric layer deposited on aluminum membranous layer, then using fluorine-containing Gas dry etching dielectric layer often has showing for aluminium liner corrosion even routing failure using the method to expose aluminum membranous layer As occurring, and then whole wafer is caused to be scrapped.
Summary of the invention
When technical solution of the present invention technical problems to be solved are using prior art production aluminium liner, often there is aluminium lining Pad corrosion even routing failure, causes whole wafer to be scrapped.
In order to solve the above technical problems, technical solution of the present invention provides a kind of production method of aluminium liner, comprising: partly leading Aluminum membranous layer is formed in body substrate；Pellumina is formed in the aluminium film layer surface；Dielectric layer is formed on the pellumina；It adopts The dielectric layer described in fluoro-gas dry etching, until exposing the pellumina；The oxidation that wet-cleaning exposes Aluminium film.
Optionally, using physical gas-phase deposition or chemical vapor deposition process or metal sputter-deposition technique shape At aluminum membranous layer.
Optionally, corona treatment is carried out to the aluminum membranous layer as gas source using oxygen and forms the pellumina； Or annealing is carried out to the aluminum membranous layer as gas source using oxygen and forms the pellumina.
Optionally, the thickness of the pellumina is less than 0.1 μm.
Optionally, the dielectric layer includes silicon oxide layer, silicon nitride layer, silicon oxynitride layer, fire sand layer and oxidation of coal At least one layer in silicon layer.
Optionally, the fluoro-gas includes at least one of carbon tetrafluoride, fluoroform and sulfur hexafluoride gas.
Optionally, alkaline solution wet-cleaning is used to remove the pellumina.
Optionally, the alkaline solution is sodium hydroxide solution or ammonium hydroxide.
In order to solve the above technical problems, technical solution of the present invention also provides a kind of semiconductor devices, comprising: semiconductor die It is round, integrated circuit is formed on the semiconductor crystal wafer；The aluminium liner made of above-mentioned production method, partly leads positioned at described It is connect on body wafer and with the integrated circuit.
Compared with prior art, technical solution of the present invention has the advantages that after forming aluminum membranous layer, to described Aluminum membranous layer carries out oxidation processes, forms thickness pellumina appropriate, shape during subsequent dry etching in aluminium film layer surface At fluorine ion be blocked in pellumina surface, pellumina and remaining fluorine can thoroughly then be removed by wet-cleaning Ion effectively prevents fluorine ion and contacts with aluminum membranous layer, avoids fluorine ion and reacts the hydrofluoric acid corrosion generated with vapor A possibility that aluminum membranous layer provides advantageous condition for subsequent bonded line, considerably reduces routing failure, while also dropping The low scrappage of wafer.
Detailed description of the invention
Fig. 1 is a kind of cross section structure schematic diagram of aluminium liner；
Fig. 2 is a kind of scanning electron microscope (SEM) photograph of aluminium pad surfaces；
Fig. 3 is the flow diagram for the production method that the aluminium of technical solution of the present invention pads；
Fig. 4 to Fig. 8 is the corresponding cross section structure schematic diagram of each step of production method that the aluminium of the embodiment of the present invention pads.
Specific embodiment
As shown in Figure 1, when making aluminium liner, it will usually the metallization medium layer 12 on aluminum membranous layer 11, then using fluorine-containing Gas dry etching dielectric layer 12 is to expose aluminum membranous layer 11, after dry etching, the fluorine ion that is formed during dry etching Aluminum membranous layer 11 can be remained in.
Remaining fluorine ion, which encounters the steam in air, can generate hydrofluoric acid, cause aluminum membranous layer 11 to be corroded, in aluminum membranous layer Surface forms crystal shaped defect as shown in Figure 2, and then will affect subsequent bonded line, causes routing to lose under serious conditions It loses.
In order to solve the above technical problems, technical solution of the present invention proposes a kind of production method of aluminium liner, surface is utilized Treatment process forms the moderate pellumina of thickness in aluminium film layer surface, and the pellumina forms dry etching in the process Fluorine ion is isolated with aluminum membranous layer, avoids fluorine ion from reacting the hydrofluoric acid corrosion aluminum membranous layer generated with vapor, then by wet Method cleaning completely removes pellumina and remaining fluorine ion, and in entire technical process, the performance of aluminum membranous layer not will receive shadow It rings.
Referring to FIG. 3, the production method that the aluminium of technical solution of the present invention pads includes:
Step S11, forms aluminum membranous layer on a semiconductor substrate；
Step S12 forms pellumina in the aluminium film layer surface；
Step S13 forms dielectric layer on the pellumina；
Step S14, using dielectric layer described in fluoro-gas dry etching, until exposing the pellumina；
Step S15, the pellumina that wet-cleaning exposes.
Technical solution of the present invention is described in detail below with reference to embodiment and attached drawing.Fig. 4 to Fig. 8 is that the present invention is implemented The corresponding structural schematic diagram of each step of production method of aluminium liner in example.
Incorporated by reference to reference Fig. 3 and Fig. 4, step S11 forms aluminum membranous layer 211 on semiconductor base 200.It can usually adopt The aluminium is formed on the substrate with physical gas-phase deposition or chemical vapor deposition process or metal sputter-deposition technique Film layer 211, in the process node of the present embodiment, the thickness range of the aluminum membranous layer can be 0.3 μm~2 μm.
Incorporated by reference to reference Fig. 3 and Fig. 5, step S12 forms pellumina 212 on 211 surface of aluminum membranous layer.Specifically, Using process of surface treatment 211 surface of aluminum membranous layer formed pellumina 212, for example, can be used oxygen be gas source and with etc. from Physical and chemical reaction occurs for the form of son and 211 surface of aluminum membranous layer, forms pellumina 212.By rationally controlling Parameter of gas ions treatment process such as temperature, time etc. can be evenly distributed, fine and close oxidation in the formation of 211 surface of aluminum membranous layer Aluminium film 212.Oxygen can also be used to make annealing treatment as surface of the gas source to aluminum membranous layer 211, so that on the aluminum membranous layer 211 Grow one layer of fine and close pellumina 212.Pass through the parameter such as temperature, time etc. for rationally controlling annealing treating process, Ke Yi 211 surface of aluminum membranous layer formed be evenly distributed, fine and close pellumina 212.
Further, in order to effective barrier against fluorine contacted with ions aluminium film layer surface and make subsequent wet cleaning can be thorough Pellumina 212 and remaining fluorine ion are removed, the thickness of pellumina 212 needs in an appropriate range, in this implementation In the process node of example, the thickness range of pellumina 212 can be less than 0.1 μm.
Incorporated by reference to reference Fig. 3 and Fig. 6, step S13 forms dielectric layer 213 on the pellumina 212.The medium The material of layer 213 can be suitable as dielectric layer for silicon oxynitride, silicon nitride, silica, fire sand, silicon oxide carbide etc. Material.Dielectric layer 213 may include in silicon oxide layer, silicon nitride layer, silicon oxynitride layer, fire sand layer and silicon oxycarbide layer It is at least one layer of, that is to say, that the dielectric layer 213 of the embodiment of the present invention is either single layer structure, or MULTILAYER COMPOSITE knot Structure.
In the present embodiment, the dielectric layer 213 is composite layer, and it successively includes silica that autoxidation aluminium film 212 rises upwards Layer 213a and silicon nitride layer 213b, wherein silicon oxide layer 213a can be formed by chemical vapor deposition, silicon nitride layer 213b It can be formed by chemical vapor deposition.
Incorporated by reference to reference Fig. 3 and Fig. 7, step S14, using dielectric layer 213 described in fluoro-gas dry etching, until exposure The pellumina 212 out, the fluorine ion of formation are blocked in 212 surface of pellumina.Specifically, etch media layer 213 can To include the following steps: to be formed mask layer, and the graphical mask layer, such as the mask layer on the dielectric layer 213 It can be photoresist, uniformly be applied to the surface of silicon nitride 213b, and graphical by photoetching development；Then, with patterned Mask layer is exposure mask, is successively performed etching to the silicon nitride 213b, silicon dioxide layer 213a, until exposing pellumina 212, finally remove mask layer.
The fluoro-gas may include at least one of carbon tetrafluoride, fluoroform and sulfur hexafluoride etc. gas, example Such as, the fluoro-gas can be carbon tetrafluoride, fluoroform or sulfur hexafluoride etc., or be also possible to the mixing of these gases Gas.
Incorporated by reference to reference Fig. 3 and Fig. 8, the pellumina 212 that wet-cleaning exposes.The embodiment of the present invention uses alkali The pellumina 212 that property solution wet-cleaning exposes, to remove the pellumina 212.The alkaline solution can be with For example, sodium hydroxide (NaOH) solution or ammonium hydroxide (NH4OH) etc..
By taking sodium hydroxide solution as an example, at normal temperature, sodium hydroxide can be chemically reacted with pellumina 212, Reaction equation is as follows: NaOH+Al2O3=2NaAlO2+H2The sodium metaaluminate of O, generation are highly soluble in water, it is easy to cleaned to go It removes.And aluminium and sodium hydroxide reaction are heating reaction, in two steps: (1) 2Al+6H2O=2Al (OH)3+3H2, (2) Al (OH)3+ NaOH=NaAlO2+2H2O, net reaction are as follows: 2Al+2NaOH+2H2O=2NaAlO2+3H2.But the reaction of aluminium and water is extremely It is faint, it is reversible reaction, in alkaline solution, balances to promoting the direction of reaction mobile, and reaction speed and solution concentration, The factors such as temperature are related, so aluminium and sodium hydroxide solution reaction are very slow.Therefore, joined by rationally controlling the technique of wet-cleaning Number, such as temperature, time, can have substantially no effect on aluminum membranous layer with the pellumina of fully erased aluminium film layer surface.
Based on the production method of above-mentioned aluminium liner, the present invention also provides a kind of semiconductor devices, the semiconductor devices Include: semiconductor base, is formed with integrated circuit on semiconductor base；Aluminium liner, be located at the semiconductor base on and with institute State integrated circuit connection.
There is no crystal shaped defects for the aluminium liner formed through the foregoing embodiment, have provided for subsequent bonded line The condition of benefit considerably reduces a possibility that routing fails, while also reducing the scrappage of wafer.
Although the present invention discloses as above in a preferred embodiment thereof, it is not for limiting the present invention, any ability Field technique personnel without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this Inventive technique scheme makes possible variation and modification, therefore, anything that does not depart from the technical scheme of the invention, according to this hair Bright technical spirit belongs to the technology of the present invention to any simple modifications, equivalents, and modifications made by embodiment of above The protection scope of scheme.

Claims (9)

1. a kind of production method of aluminium liner characterized by comprising
Aluminum membranous layer is formed on a semiconductor substrate；
Pellumina is formed in the aluminium film layer surface；
Dielectric layer is formed on the pellumina；
Using dielectric layer described in fluoro-gas dry etching, until exposing the pellumina；
The pellumina that wet-cleaning exposes.
2. the production method of aluminium liner as described in claim 1, which is characterized in that use physical gas-phase deposition or change It learns gas-phase deposition or metal sputter-deposition technique forms the aluminum membranous layer.
3. the production method of aluminium liner as described in claim 1, which is characterized in that using oxygen as gas source to the aluminium film Layer carries out corona treatment and forms the pellumina；Or the aluminum membranous layer is carried out at annealing as gas source using oxygen Reason forms the pellumina.
4. the production method of aluminium liner as described in claim 1, which is characterized in that the thickness of the pellumina is less than 0.1 μ m。
5. the production method of aluminium liner as described in claim 1, which is characterized in that the dielectric layer includes silicon oxide layer, nitrogen At least one layer in SiClx layer, silicon oxynitride layer, fire sand layer and silicon oxycarbide layer.
6. the production method of aluminium as described in claim 1 liner, which is characterized in that the fluoro-gas include carbon tetrafluoride, At least one of fluoroform and sulfur hexafluoride gas.
7. the production method of aluminium liner as described in claim 1, which is characterized in that use alkaline solution wet-cleaning to remove The pellumina.
8. the production method of aluminium liner as claimed in claim 7, which is characterized in that the alkaline solution is sodium hydroxide solution Or ammonium hydroxide.
9. a kind of semiconductor devices characterized by comprising
Semiconductor base is formed with integrated circuit on the semiconductor base；
Using the aluminium liner of claim 1 to 8 described in any item production methods production, be located on the semiconductor base and with The integrated circuit connection.
CN201910279285.XA 2019-04-09 2019-04-09 The production method and semiconductor devices of aluminium liner Pending CN109979835A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005353663A (en) * 2004-06-08 2005-12-22 Seiko Epson Corp Semiconductor device and manufacturing method thereof
CN102800575A (en) * 2011-05-26 2012-11-28 中芯国际集成电路制造(上海)有限公司 Method for removing crystal defects of aluminum liner
CN105810631A (en) * 2014-12-31 2016-07-27 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and formation method thereof
CN105826162A (en) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for reducing fluorine crystal of Al pad and semiconductor device manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005353663A (en) * 2004-06-08 2005-12-22 Seiko Epson Corp Semiconductor device and manufacturing method thereof
CN102800575A (en) * 2011-05-26 2012-11-28 中芯国际集成电路制造(上海)有限公司 Method for removing crystal defects of aluminum liner
CN105810631A (en) * 2014-12-31 2016-07-27 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and formation method thereof
CN105826162A (en) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for reducing fluorine crystal of Al pad and semiconductor device manufacturing method

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