CN109976815B - Method and system for accelerating Nandboot - Google Patents
Method and system for accelerating Nandboot Download PDFInfo
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- CN109976815B CN109976815B CN201910214571.8A CN201910214571A CN109976815B CN 109976815 B CN109976815 B CN 109976815B CN 201910214571 A CN201910214571 A CN 201910214571A CN 109976815 B CN109976815 B CN 109976815B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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Abstract
The invention relates to a method and a system for accelerating Nandboot; the method for accelerating Nandboot comprises the following steps: s1, starting a chip, and configuring NFC and PHY at low speed; s2, completing the configuration of the NandFlash particles in a low-speed state; s3, reading a Header of the boot file in the NandFlash; s4, analyzing the Header, and initializing the NFC and PHY restart to high speed by using parameters in the Header; s5, reading the rest boot files at high speed; and S6, loading the boot file and running. According to the invention, through special processing of the boot file, corresponding NFC and PHY configuration parameters are added, when the chip is started, the NFC and PHY are reconfigured by reading the parameters to improve the Nandboot speed, and meanwhile, because the high-speed configuration parameters are written in later period, the high-speed configuration parameters can be changed at any time, the condition that the time sequence does not meet the requirement is avoided, so that the whole starting speed is improved, the time is saved, and the scene with higher requirement on the starting time of the chip is met.
Description
Technical Field
The invention relates to the technical field of solid state disk chips, in particular to a method and a system for accelerating Nandboot.
Background
When a chip is started by using a Nandboot, the conventional mode at present adopts a starting process with constant speed, namely, a low-speed NandFlah controller (NFC) and PHY parameters are used for operating NandFlah. Although the low-speed configuration has low requirements on PHY parameters and the like, so that the whole chip can have good compatibility with NandFlash, the low speed is more suitable for initializing Nand particles, the later read-write operation on the particles is not dominant, and the scheme of firstly low speed and then high speed has great risk.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method and a system for accelerating Nandboot.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method of accelerating Nandboot, comprising the steps of:
s1, starting a chip, and configuring NFC and PHY at low speed;
s2, completing the configuration of the NandFlash particles in a low-speed state;
s3, reading a Header of the boot file in the NandFlash;
s4, analyzing the Header, and initializing the NFC and PHY restart to high speed by using parameters in the Header;
s5, reading the rest boot files at high speed;
and S6, loading the boot file and running.
The further technical scheme is as follows: in S1, the NFC and the PHY are initialized to low-speed configuration.
The further technical scheme is as follows: in S2, the method further includes: and loading the boot file for the Nandboot, and processing.
The further technical scheme is as follows: in S2, the method further includes: and adding a Header at the initial position of the boot file, wherein the Header comprises NandFlash particle information and configuration parameters of NFC and PHY.
The further technical scheme is as follows: in S2, the method further includes: and writing the whole boot file into the NandFlash particles for use by the Nandboot.
The further technical scheme is as follows: in S4, the parsing Header includes configuration information parameters of the high-speed NFC and the PHY.
A Nandboot acceleration system comprises a starting unit, a configuration unit, a first reading unit, an analysis unit, a second reading unit and a loading unit;
the starting unit is used for starting a chip and configuring NFC and PHY at a low speed;
the configuration unit is used for completing the configuration of the NandFlash particles in a low-speed state;
the first reading unit is used for reading a Header of a boot file in the NandFlash;
the analysis unit is used for analyzing the Header and initializing the restart of the NFC and the PHY to be high speed by using parameters in the Header;
the second reading unit is used for reading the rest boot files at a high speed;
and the loading unit is used for loading and running the boot file.
The further technical scheme is as follows: and in the starting unit, performing initial low-speed configuration on the NFC and the PHY.
The further technical scheme is as follows: and in the configuration unit, loading and processing a Nandboot file, adding a Header at the initial position of the boot file, wherein the Header comprises NandFlash particle information and configuration parameters of NFC and PHY, and writing the whole boot file into NandFlash particles for use by the Nandboot.
The further technical scheme is as follows: in the analysis unit, the analysis Header comprises configuration information parameters of high-speed NFC and PHY.
Compared with the prior art, the invention has the beneficial effects that: through carrying out special treatment to the boot file, add corresponding NFC and PHY configuration parameter, when the chip starts, improve Nandboot speed through reading these parameters and reconfiguring NFC and PHY, simultaneously, because the configuration parameter of high-speed is write in the later stage, can change at any time, has removed the not satisfied condition of requirement of chronogenesis from to improve whole boot speed, save time, can satisfy the demand better.
The invention is further described below with reference to the accompanying drawings and specific embodiments.
Drawings
FIG. 1 is a schematic flow diagram of a prior art method for accelerating Nandboot;
FIG. 2 is a flow chart of a method of accelerating a Nandboot according to the present invention;
FIG. 3 is a schematic diagram illustrating an application of a boot file according to the present invention;
fig. 4 is a block diagram of a Nandboot acceleration system according to the present invention.
10 starting unit 20 configuration unit
30 first reading unit 40 parsing unit
50 second reading unit 60 loading unit
Detailed Description
In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.
In the embodiments shown in fig. 1 to 4, as in the prior art shown in fig. 1, during the whole process of loading and running the boot file, for stable boot of the chip, the NandFlash controller (NFC) is configured to be at a low speed; after the initialization of the chip is completed, the NFC/PHY is configured to be at a low speed, then the NandFlash is operated at the low speed all the time, and the file is loaded and run.
As shown in fig. 2 to 3, the present invention discloses a method for accelerating Nandboot, which comprises the following steps:
s1, starting a chip, and configuring NFC and PHY at low speed;
s2, completing the configuration of the NandFlash particles in a low-speed state;
s3, reading a Header of the boot file in the NandFlash;
s4, analyzing the Header, and initializing the NFC and PHY restart to high speed by using parameters in the Header;
s5, reading the rest boot files at high speed;
and S6, loading the boot file and running.
In S1, initializing low-speed configuration of NFC and PHY.
Wherein, in S2, the method further includes: and loading the boot file for the Nandboot, and processing.
Further, in S2, the method further includes: and adding a Header at the initial position of the boot file, wherein the Header comprises NandFlash particle information and configuration parameters of NFC and PHY.
Further, in S2, the method further includes: and writing the whole boot file into the NandFlash particles for use by the Nandboot.
In S4, the Header is parsed to include configuration information parameters of the high-speed NFC and PHY, and then the NFC and PHY are reconfigured using these parameters to operate in a high-speed state, so as to speed up reading of the remaining boot files, thereby saving time.
According to the invention, high-speed configuration information of NFC, PHY and the like is added in the binary file to be loaded, when the chip is started, the purpose of increasing the speed is achieved by analyzing and using the high-speed configuration information, so that the chip is started at a low speed, the risk that the NFC and the PHY are operated at a high speed after the chip is powered on (parameters in bootrom are not matched with the reality) is avoided, and meanwhile, the high-speed configuration information read in the later period is easier to maintain, so that the chip is more stable.
As shown in fig. 4, the present invention discloses a Nandboot acceleration system, which includes a starting unit 10, a configuration unit 20, a first reading unit 30, an analysis unit 40, a second reading unit 50, and a loading unit 60;
the starting unit 10 is used for starting a chip and configuring NFC and PHY at a low speed;
the configuration unit 20 is configured to complete configuration of the NandFlash particles in a low-speed state;
the first reading unit 30 is configured to read a Header of a boot file in the NandFlash;
the parsing unit 40 is configured to parse the Header, and initialize the restart of the NFC and the PHY to a high speed by using parameters in the Header;
the second reading unit 50 is configured to read the remaining boot files at a high speed;
the loading unit 60 is configured to load a boot file and run the boot file.
In the starting unit 10, the NFC and the PHY are initially configured at a low speed.
In the configuration unit 20, a boot file is loaded and processed on the Nandboot, a Header is added to the start position of the boot file, the Header includes NandFlash particle information, and configuration parameters of NFC and PHY, and the whole boot file is written into the NandFlash particles for the Nandboot to use.
In the parsing unit 40, the parsing Header includes configuration information parameters of the high-speed NFC and the PHY.
According to the invention, through special processing of the boot file, corresponding NFC and PHY configuration parameters are added, when the chip is started, the NFC and PHY are reconfigured by reading the parameters to improve the Nandboot speed, and meanwhile, because the high-speed configuration parameters are written in later period, the high-speed configuration parameters can be changed at any time, the condition that the time sequence does not meet the requirement is avoided, so that the whole starting speed is improved, the time is saved, and the scene with higher requirement on the starting time of the chip is met.
The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (9)
1. A method of accelerating a Nandboot, comprising the steps of:
s1, starting a chip, and configuring NFC and PHY at low speed;
s2, completing the configuration of the NandFlash particles in a low-speed state;
s3, reading a Header of the boot file in the NandFlash;
s4, parsing the Header, and initializing the NFC and PHY restart to high speed by using configuration parameters in the Header;
s5, reading the rest boot files at high speed;
and S6, loading the boot file and running.
2. The method of claim 1, wherein in S1, the NFC and PHY are initialized to low-speed configuration.
3. The method for accelerating Nandboot as claimed in claim 1, wherein in the step S2, further comprising: and adding a Header at the initial position of the boot file, wherein the Header comprises NandFlash particle information and configuration parameters of NFC and PHY.
4. The method for accelerating Nandboot as claimed in claim 3, wherein the step S2 further comprises: and writing the whole boot file into the NandFlash particles for use by the Nandboot.
5. The method of claim 1, wherein in the S4, parsing the Header comprises obtaining high-speed configuration parameters of NFC and PHY.
6. A Nandboot acceleration system is characterized by comprising a starting unit, a configuration unit, a first reading unit, an analysis unit, a second reading unit and a loading unit;
the starting unit is used for starting a chip and configuring NFC and PHY at a low speed;
the configuration unit is used for completing the configuration of the NandFlash particles in a low-speed state;
the first reading unit is used for reading a Header of a boot file in the NandFlash;
the analysis unit is used for analyzing the Header and initializing the restart of the NFC and the PHY to be high speed by using configuration parameters in the Header;
the second reading unit is used for reading the rest boot files at a high speed;
and the loading unit is used for loading and running the boot file.
7. The system of claim 6, wherein the boot unit is configured to initialize the NFC and the PHY for low speed configuration.
8. The system according to claim 6, wherein in the configuration unit, a Header is added to a start position of the boot file, the Header contains NandFlash particle information, and configuration parameters of NFC and PHY, and the entire boot file is written into the NandFlash particles for use by the nandfoot.
9. The system of claim 6, wherein the parsing unit is configured to parse a Header including obtaining high-speed configuration parameters of the NFC and the PHY.
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| CN201910214571.8A CN109976815B (en) | 2019-03-20 | 2019-03-20 | Method and system for accelerating Nandboot |
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| CN201910214571.8A CN109976815B (en) | 2019-03-20 | 2019-03-20 | Method and system for accelerating Nandboot |
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| CN109976815B true CN109976815B (en) | 2022-03-29 |
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| CN104239077A (en) * | 2013-06-13 | 2014-12-24 | 北京赛科世纪数码科技有限公司 | Method and device for starting boot program and CPU |
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