CN109976272B

CN109976272B - Distributed peripheral bus system with strict access and sampling time and control method thereof

Info

Publication number: CN109976272B
Application number: CN201910192896.0A
Authority: CN
Inventors: 朱磊
Original assignee: Individual
Current assignee: Individual
Priority date: 2018-10-08
Filing date: 2019-03-14
Publication date: 2021-08-31
Anticipated expiration: 2039-03-14
Also published as: CN109976272A

Abstract

The invention discloses a distributed peripheral bus system with strict access and sampling time and a control method thereof, wherein the system comprises a single bus master station and at least one bus slave station; the physical layer of the system adopts a dual-redundancy low-voltage differential signaling (LVDS) bus technology; the data link layer is realized by a Field Programmable Gate Array (FPGA) or a FASTDP-BUS protocol control chip for realizing a FASTDP-BUS link protocol, and the FASTDP-BUS protocol control chip is realized by adopting an Application Specific Integrated Circuit (ASIC) mode; the application layer adopts FASTDP-BUS application layer protocol specification, and the FPGA or FASTDP-BUS control chip is mapped to the CPU of the internal address space through an Industry Standard Architecture (ISA) BUS. By adopting the method and the device, the data access time certainty and the time certainty of analog quantity sampling based on the bus can be effectively improved, and a bus data mechanism is simplified.

Description

Distributed peripheral bus system with strict access and sampling time and control method thereof

Technical Field

The invention relates to a field bus intelligent control technology, in particular to a distributed peripheral bus system with strict access and sampling time and a control method thereof.

Background

The field bus interconnects sensors, measurement and control units, an automatic control system and the like which are distributed on the field, realizes the intercommunication of Input and Output (IO) data, and provides powerful support for information transmission and information control of the industrial automatic control system. The kinds of field buses are hundreds, and many of them become international standards, for example: PROFIBUS, Controller Area Network (CAN), Device Net, INTERBUS, Foundation Field Bus (FF), etc., each play an important role in the control system.

The PROFIBUS bus adopts master station token time slice rotation, high-priority data of the PROFIBUS bus considers multi-segment transmission and a master-slave polling mechanism, has the highest transmission speed of 12Mbps, has a standard field bus function, is mainly used in the field of industrial control including process control and the like, but cannot be used in a complex relay protection device of a power system at present; the CAN bus multi-master station non-destructive transmission conflict arbitration mechanism has the highest speed of 1Mbps and the message within 8B bytes, and other standard field bus functions, and is mainly used for controlling automobile electronic equipment. The INTERBUS bus adopts a ring forwarding mechanism controlled by a master station, the length of transmitted data does not exceed 512 bits, the transmission speed is not higher than 10Mbps, and the INTERBUS bus is mainly used for industrial production lines; the other buses have their own features and are not described in detail herein.

In recent years, with the continuous expansion of the application fields of control devices such as DCS, PLC, PAC, and the like, for example, the expansion of the application fields to the fields of power systems, relay protection, and the like, the data transmission types are correspondingly expanded. On the one hand, current buses have not been able to fully meet the data transfer capabilities required in these areas; on the other hand, with the development of electronic communication technology, a plurality of novel electronic and communication devices emerge in the market, and the current field bus technology is still somewhat behind to be improved urgently. The current fieldbus technology is urgently to be promoted and solved from the following aspects:

1) the transfer speed is to be increased. The rapid automatic control devices for complex industrial production control, high-voltage relay protection, emergency braking and the like need to realize microsecond (mu s) level data sampling speed of a large number of IO, and the requirement on board level speed is about 100Mbps or even higher. The prevailing fieldbus speeds, especially board-level fieldbus speeds, are low today, with Profibus-DP representing one of the highest speeds in the field, but not higher than 12 Mbps.

2) The transmission time certainty is to be improved. Under the requirement of equivalent dotted capacity, the complex high-speed industrial production control, the high-voltage relay protection and other rapid automatic devices require IO data synchronous sampling, the error is less than 1 mu second, and the current field bus cannot achieve the precision, so that the application in the fields is limited. Meanwhile, the related data are various, such as real-time IO data, emergency control data, historical curve data, historical event data, wave recording data, IO management data, diagnosis data and the like, the transmission time certainty and priority control of the data are different, and the current field bus technology has great defects.

3) The data transfer mechanism is to be simplified. The current field bus has defects in transmission data classification, arbitration of the use right of the serial bus and interaction mechanism of data; the FF bus adopts a transmission token to arbitrate the use right of the bus, the PROFIBUS adopts master station token time slice rotation, high-priority data of the PROFIBUS considers multi-segment transmission, a master-slave polling mechanism, a CAN bus multi-control-domain field and a short data frame mode and the like, so that the bus scheduling is complex, and the effective use rate of the bus bandwidth is reduced.

Disclosure of Invention

In view of the above, the main objective of the present invention is to provide a distributed peripheral bus system with strict access and sampling time and a control method thereof, so as to effectively increase the data transmission speed, improve the certainty of the transmission time and simplify the data transmission mechanism.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a strict access and sample time distributed peripheral bus system comprising:

a single bus master and at least one bus slave; the physical layer of the system adopts a dual-redundancy low-voltage differential signal LVDS bus technology; the data link layer is realized by adopting a field programmable gate array FPGA or a FASTDP-BUS protocol control chip for realizing a FASTDP-BUS link protocol, and the FASTDP-BUS protocol control chip is realized by adopting a special integrated circuit ASIC mode; the application layer adopts FASTDP-BUS application layer data specification, and the FPGA or FASTDP-BUS protocol control chip is mapped to the CPU of the internal address space through an industry standard system structure ISA BUS.

In the DATA link layer, DATA link frames of the DATA link layer are divided into link layer DATA frames containing application DATA APP DATA fields and link layer DATA frames without the application DATA APP DATA fields; wherein, the link layer DATA frame containing the application DATA APP DATA comprises application layer DATA; the link layer DATA frame without the application DATA APP DATA comprises an LLC DATA field indicating the field length; the application layer data comprises the following fields: sending an application layer DATA message in a cache, wherein the application layer DATA message comprises a Dest Addr field, a DUn field, a field with the whole length LE3 of an FCS field, a destination address Dest Addr field, an APP DATA field and a sum check FCS field; the APP DATA field contains a plurality of DATA fields DU; each DU is 1 byte in length;

the link layer DATA frame containing the application DATA APP DATA comprises the following fields:

a frame synchronization header (Sync) Head field, a target address Dest Addr field, a source address Src Addr field, a link layer transmission Channel (CMD) field, a transmission frame control byte (FC) field, a length LE2 indication mark field of a link frame APP DATA field with application DATA, an APP DATA field, a cyclic redundancy check code (CRC) field and a frame synchronization Tail (Sync) Tail field;

the link layer DATA frame without the application DATA APP DATA comprises the following fields: a frame synchronization header (Sync) Head field, a target address Dest Addr field, a source address Src Addr field, a link layer transmission Channel (CMD) field, a transmission frame control byte (FC) field, a link frame (LE 1) indication mark field representing no application DATA, a length of field (LLC DATA) field, a cyclic redundancy check code (CRC) field, and a frame synchronization Tail (Sync) Tail field.

The application layer data transmission channel of the distributed peripheral bus comprises an FC control field for identifying the application layer channel arranged at the head of a link frame, and the identification of a URG channel, a NORM channel, a WAVE channel and an MNG channel is realized; wherein:

the NORM channel is used for transmitting coverable distributed IO slave station real-time data, and the data comprises AI, DI and other sampling input data in the coverable and interruptible loss and other situations; and output control data such as DO, AO, etc. that CPU periodically and continuously outputs; the FASTDP-BUS BUS sets independent receiving cache and sending cache for each distributed IO slave station of the channel to form a sub-channel of the NORM channel;

the URG channel is used for transmitting the channel of the distributed IO emergency operation data which can be transmitted by the pluggable team; the FASTDP-BUS BUS only sets a common receiving buffer and a common receiving buffer for the channel, and the buffer is shared by the emergency data of all the distributed IO slave stations;

a WAVE channel, a channel for transmitting data of values of distributed IO points which cannot be covered, the data including data of AI points which cannot be covered, lost and the like, DI point values, SOE data of DI, EVENT data and the like; the FASTDP-BUS only sets a public receiving cache for the channel, and the cache is shared by all the emergency data of the distributed IO slave stations;

the MNG channel is used for transmitting the channel of the distributed IO slave station configuration management data, and the data comprises query and configuration commands of data such as equipment self-description information, IO slave station operation parameters and the like; all distributed IO slave stations share the channel, and only one common receiving cache and one common receiving cache are shared

The distributed IO slave station real-time data transmission channel specifically comprises the following steps:

the bus sets an independent real-time NORM data channel for each IO slave station and obtains bus access right according to an access cycle set by an application layer; and the channel corresponding to each IO slave station is a sub-channel of the NORM channel class.

The link data transmission channel of the data link layer comprises the following components: the link layer creates and manages a time setting channel, a synchronous channel, a new searching channel and a diagnosis channel; the data channel of the link layer is not provided with a transceiving cache and is directly processed by the data link layer; wherein:

the time setting channel is used for transmitting a channel for setting time setting data of the distributed IO and activating the channel to set time according to a set period;

the synchronous channel is used for transmitting a channel for synchronously sampling commands of the distributed IO, and activating the channel according to a set synchronous calibration period to realize sampling step sequence calibration;

a new channel for transmitting a distributed IO inquiry command of a new access bus; during the idle period of the BUS, activating the channel according to the inquiry period of the IO slave station of the new access system, and inquiring and initializing the newly operated distributed IO on the FASTDP-BUS;

and the diagnosis channel is used for transmitting the channel of the link layer aiming at the link diagnosis command, and activating the channel to realize diagnosis according to the set diagnosis period.

Each channel of the bus carries out bus access according to a channel access ready table mechanism, wherein the channel access ready table is of a two-dimensional structure and consists of a row unit corresponding to a row and a channel, and the row unit corresponds to a channel; the method comprises fixed priority channel control, access time uncertainty channel control, NORM and IO slave station channel control and also comprises cycle ready mark refreshing control time slot cycle ready mark control.

The channel access time certainty criterion is divided into: when the channel period of the IO slave station in the ready list does not exist, a sequential access mechanism with equal opportunity is adopted by default; and when the channel period of the IO slave station is configured in the ready list, adopting a priority access control mechanism of the ready list.

The arbitration mechanism of the channel access priority is as follows: and the channel priority arbitration is realized by the aid of the ready zone bit set by the channel access ready table.

The channel switching control mechanism is as follows: after the channel obtains the bus use right, in the specified exchange time slot, in the uplink and downlink data transmission, the data exchange between the main station and the slave station transmission data in the corresponding channel is realized through the mutual mapping of the channel address, the attribute, the channel data, the target address of the link data frame, the FC control domain and the data field.

A method for realizing a distributed peripheral bus system with strict access and sampling time comprises the following steps:

setting a single bus master station and at least one bus slave station;

the physical layer of the bus system adopts a dual-redundancy low-voltage differential signal LVDS bus technology;

the data link layer of the BUS system is realized by adopting a field programmable gate array FPGA or a FASTDP-BUS protocol control chip for realizing a FASTDP-BUS link protocol, and the FASTDP-BUS protocol control chip is realized by adopting a special integrated circuit ASIC mode;

the application layer of the BUS system adopts FASTDP-BUS application layer data specification, and the FPGA or FASTDP-BUS protocol control chip is mapped to the CPU of the internal address space through an industry standard system structure ISA BUS to realize the purpose.

Compared with the prior art, the distributed peripheral bus system with strict access and sampling time and the control method thereof have the following beneficial effects:

1) the data transmission speed of the FASTDP-BUS is greatly improved. The FASTDP-BUS adopts hardware circuits such as FPGA or ASIC to improve the access Time slot to 1-20 microseconds, adopts LVDS technology to improve the field BUS speed to 100Mbps, and can realize 1 microsecond level strict Time certainty (Firm Real-Time). Far exceeding the highest speed of the PROFIBUS bus of 12Mbps, the CAN bus of 1Mbps and the FF bus of 31.25Kbps of the field bus of level H1. The method provides a foundation for the application of the high-speed field bus in other protection null fields such as electric power and the like.

2) The FASTDP-BUS achieves strict certainty of access and sampling time. Different from the high-low two-gear priority of the PROFIBUS BUS, a rough access control mechanism of a token time slice rotation mechanism, priority control based on information of an FF BUS, a data exchange mode of a token mode, an uncertainty mechanism caused by conflict rejection of Ethernet and the like, the FASTDP-BUS BUS adopts a default opportunity equal sequence access mechanism, and a channel access ready table mechanism realizes strict time certainty of channel access and sampling control of IO slave stations according to the priority of data. The method provides key support for the application of the field in key control systems such as power relay protection, emergency control systems, safety nuclear power control and the like.

3) The FASTDP-BUS implements an efficient data transfer mechanism. The FASTDP-BUS gives a comprehensive channel classification to data on the BUS according to the characteristics of importance, time certainty and the like; an access ready list mechanism is designed for the channel; under the control of a priority arbitration mechanism, a channel switching mechanism is adopted, and data is efficiently switched and transmitted between the master station channel and the slave station channel; particularly, an emergency multiplexing mechanism and an idle multiplexing mechanism, a token transmission process that an FF bus wastes bus bandwidth is omitted, and the transmission inefficiency of a polling response mechanism of a PROFIBUS bus is overcome; meanwhile, the FASTDP-BUS provides a random data transmission channel, large data such as waveform data, historical data and file data are transmitted by using the idle BUS bandwidth; therefore, the FASTDP-BUS supports the increasing comprehensive data transmission requirement of the field BUS while realizing the strict time certainty of the acquisition control of the IO slave station.

Drawings

FIG. 1 is a schematic diagram of a distributed peripheral bus system with strict access and sampling times according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a data link frame format of the FASTDP-BUS according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an application layer data transmission channel of the FASTDP-BUS BUS according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a real-time data transmission channel of a FASTDP-BUS distributed IO slave station according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a data transmission path of a FASTDP-BUS link layer according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating FASTDP-BUS BUS access ready according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating downlink switching control of a FASTDP-BUS master station channel according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of the uplink switching control of the FASTDP-BUS master station channel according to the embodiment of the present invention;

fig. 9 is a schematic diagram of uplink switching control of the FASTDP-BUS slave channel according to the embodiment of the present invention.

Detailed Description

The present invention will be described in further detail below with reference to the accompanying drawings and embodiments thereof.

FIG. 1 is a diagram of a distributed peripheral bus system with strict access and sampling times according to an embodiment of the present invention.

As shown in FIG. 1, the strict access and sample time distributed peripheral bus system, i.e.

The FASTDP-BUS system includes a single BUS master station and one or more BUS slave stations. The physical layer of the bus system adopts a dual-redundancy low-voltage differential signaling (LVDS) bus technology, and the data transmission rate can reach 100 Mbps; the data link layer is realized by a Field Programmable Gate Array (FPGA) or a FASTDP-BUS protocol control chip for realizing a FASTDP-BUS link protocol, and the protocol control chip is realized by adopting an Application Specific Integrated Circuit (ASIC) mode; the application layer adopts FASTDP-BUS application layer data specification, and uses FPGA or ISA BUS

The FASTDP-BUS controls the CPU implementation of the chip mapping to the internal address space.

FIG. 2 is a diagram illustrating a data link frame format of the FASTDP-BUS according to an embodiment of the present invention.

As shown in FIG. 2, in the FASTDP-BUS data link frame format, the fields have the following meanings:

sync Head: a frame synchronization header;

sync Tail: frame synchronization tail;

dest Addr: a target address;

src Addr: a source address;

FC: transmitting a frame control byte;

CMD: a link layer transmission channel;

LE 1: a link frame representing no application data;

LLC DATA: the length of the field;

LE 2: length of link frame APP DATA field with application DATA;

LE 3: sending an application layer data message in the cache, wherein the application layer data message contains all the lengths of a Dest Addr field, a DUn field and an FCS field;

DU: the DATA field is completely filled in the DATA field position of the link layer by the CMD field and the DATA DATA of the application layer;

FCS: the sum check is 8-bit accumulation sum of all application data fields after the LE field of the application layer data and before the FCS; when the link frame is packed, the field is lost and does not exist;

CRC: a cyclic redundancy check code field.

FIG. 3 is a diagram of an application layer data transfer path of the FASTDP-BUS BUS according to an embodiment of the present invention.

As shown in fig. 3, in the application layer data transfer path of the FASTDP-BUS, the application layer data refers to data or commands that are generated by the application layer function and are transferred to the application layer. And setting an FC control field for identifying the application layer channel at the head of the link frame to realize the identification of the URG channel, the NORM channel, the WAVE channel and the MNG channel. Wherein:

a NORM channel for the passage of coverable distributed IO slave station real-time data, including AI, DI, etc. sampled input data for coverable, intermittently lost, etc. situations; and DO, AO output control data that CPU periodic continuous output; the FASTDP-BUS BUS sets independent receiving cache and sending cache for each distributed IO slave station of the channel to form a sub-channel of the NORM channel.

-a URG channel for the transmission of emergency operation data of distributed IO that can be transmitted by pluggable queues; the FASTDP-BUS provides only one common receive buffer and one common receive for the channel and this buffer is shared by all the distributed IO slave's emergency data.

A WAVE channel for transmitting data of values of distributed IO points that cannot be covered, including data of AI points that cannot be covered, lost, etc., DI point values, SOE data of DI, and EVENT data, etc.; the FASTDP-BUS sets only one common receive buffer for this channel and this buffer is shared by all the distributed IO slave's emergency data.

The MNG channel is used for transmitting distributed IO slave station configuration management data, and the data comprises equipment self-description information, query and configuration commands of data such as IO slave station operation parameters and the like; all the distributed IO slave stations share the channel, and only one pair of common receiving cache and one common receiving cache are arranged.

Fig. 4 is a schematic diagram of a real-time NORM data transmission channel of a FASTDP-BUS distributed IO slave station according to an embodiment of the present invention.

As shown in fig. 4, the FASTDP-BUS sets an independent real-time NORM data channel for each IO slave station, and obtains BUS access right according to an access cycle set by an application layer. The channel corresponding to each IO slave station is a sub-channel of the NORM channel. Wherein:

each IO slave station has its own independent IO real-time NORM data uplink buffer and downlink buffer;

-the FC control field is carried out identifying the NORM channel when real-time data of each IO slave station is exchanged on the bus;

real-time NORM data of all IO slave stations themselves, constituting the entirety of NORM channel data;

all IO slave stations independently own real-time NORM data transceiving caches, which form all NORM channel caches;

-real-time NORM data transmission sub-channels independently owned by all IO slave stations, constituting the entirety of the NORM channel.

FIG. 5 is a diagram of a data transmission path of a FASTDP-BUS link layer link according to an embodiment of the present invention.

As shown in FIG. 5, the FASTDP-BUS link layer data refers to data or commands that are generated by link layer functions and that are intended to transfer or service data or commands that end at the link layer. The FC at the head of the link frame clears the control bits of the application layer data channel to identify the link layer data channel, and the specific channel distinguishes that the link layer command identifies a time setting channel, a synchronous channel, a new searching channel and a diagnosis channel. The data channel of the link layer is not provided with a transceiving cache and is directly processed by the FASTDP-BUS link layer. Wherein:

-channel-on-time: transmitting a channel for time synchronization data of the distributed IO, and activating the channel for time synchronization in the whole second according to a set period;

-a synchronization channel: the channel for transmitting the synchronous sampling command to the distributed IO activates the channel according to the set synchronous calibration period to realize the sampling step sequence calibration;

-a new channel: a channel for transmitting a distributed IO inquiry command of a new access bus; during the idle period of the BUS, activating the channel according to the inquiry period of the IO slave station of the new access system, and inquiring and initializing the newly operated distributed IO on the FASTDP-BUS;

-a diagnostic channel: and the transmission link layer activates the channel for commands such as link diagnosis and the like according to a set diagnosis period to realize diagnosis.

FIG. 6 is a diagram illustrating FASTDP-BUS BUS access ready according to an embodiment of the present invention.

As shown in FIG. 6, the access to the ready table by the FASTDP-BUS BUS is as follows:

1) two-dimensional structure of ready list:

the ready table is a two-dimensional table consisting of rows corresponding to the access cycles and row units corresponding to the channels; the method specifically comprises three parts, namely a fixed priority channel, NORM and IO slave station channels and a time uncertainty channel;

-a ready table for each row header field storing a unique period value corresponding to the row; the method is characterized in that: the corresponding periodic field value of the emergency channel and the random data channel is 0;

the ready table may contain a maximum of 127 channel units after each row period field, each unit containing the channel ID and a ready flag;

the channel units of each row of the ready list are arranged consecutively from left to right in the row, with the channel ID numbers from small to large.

2) Fixed priority channel portion of ready list:

the fixed priority channel portion occupies the first three rows of the ready list, each row having a fixed priority, the channel access time of which is strictly determined;

the first row of the ready list is fixedly occupied by the synchronization channel alone; the period of the synchronous register is determined by the value of the sampling synchronous register, and the ready mark is set by the refreshing operation of the period ready mark (the mark is 1);

the second row of the ready table is fixedly occupied by the emergency channel alone, with a period of 0, and the ready flag bit is set by the emergency data transmission request (flag ═ 1) and cleared after the emergency data transmission buffer is empty (flag ═ 0);

the third row of the ready table is fixedly occupied by the time channel alone, its period is set by the time period register value, its ready flag is set by the period ready flag refresh operation (flag ═ 1).

3) Access time uncertainty channel part of ready list:

the time uncertainty channel part is arranged in the last two rows of the ready list, and the bus access of a restrictive periodic or random time slot rotation mechanism is carried out by using the idle time slots except the time slots occupied by the bus certainty time access channel, and the access time of the channel has uncertainty;

the penultimate row of the ready table is a restricted data cycle channel, fixedly occupied by the refresh channel and the diagnostic channel, whose cycle is set by the link management cycle register, whose ready flag is controlled by the cycle ready flag refresh operation, whose access point in time is limited by the bus idle opportunities;

the last row of the ready table is a random data channel, which is occupied by the MNG channel and all WAVE channels together, and has a period of 0, and uses an idle slot cycle access bus, and its ready flag is controlled by the slot cycle ready flag operation;

-a random data channel row, the WAVE channels being dynamically configured by the application layer, except that the first cell is fixedly occupied by the MNG channel; each WVAE channel ID corresponds to the ID of an IO slave station that requires WAVE data transmission.

4) NORM and IO slave channel part of ready table:

the NORM and IO slave station channels occupy rows other than the first three and the last two rows in the ready list, the channel access needs to be strictly determined according to time;

sequencing all nonrepetitive access cycles of the IO slave stations from small to large, respectively using the sequencing as a row cycle field, and generating each row corresponding to the part of the ready list from top to bottom;

and storing IO slave stations in the same period in rows corresponding to the period from left to right continuously according to the channel ID size.

5) Periodic ready flag refresh operation:

-every 1 microsecond (μ s) of the ready table, determining and setting a ready flag of each channel in the table that has reached a set period and a period other than 0 (flag ═ 1);

the ready channel of the periodic channel (i.e. with a period other than 0) has access to the bus immediately after the end of the bus, the ready flag is cleared (flag-0);

6) slotted wheel ready flag operation

No bit (flag ═ 1) in the ready table, the random data channel gets a slot rotation operation;

after the current channel bus access time slot is finished, completing one idle bus time slot rotation by clearing (flag ═ 0) the ready flag of the channel and setting (flag ═ 1) the ready flag of the next channel unit;

for the first MNG channel unit in the random data channel row, the ready flag bit is initialized to set (flag 1), and the slot rotation is forced to start from the MNG channel unit.

As shown in FIG. 6, the priority arbitration mechanism is accessed for the FASTDP-BUS channel. All data of the FASTDP-BUS need to share a unique physical channel to realize BUS access, so that each data channel needs to obtain the access right of the BUS according to different priorities according to different data characteristics.

The FASTDP-BUS realizes channel priority arbitration by means of a ready zone bit set by a channel access ready table, and the specific arbitration rules are as follows:

-specifying the channel in the ready list for which any ready flag is set (flag-1), the bus access priority being higher than the channel that is not set;

-specifying the channel with the highest priority in the ready list to give priority to exclusive ownership of a bus;

-specifying a ready list in which the priority is decremented row by row as the row number increases if all rows and channel ready flags are set; the first row, the sync channel, has the highest bus access priority; the last row, namely the random data channel, only has the lowest bus access priority;

-specifying all channels in the same row of the ready list, the channel access priorities being equal; the smaller channel ID value gets bus access priority first because of the preceding cell in the row.

The following is a description of the criterion for determining access time to the FASTDP-BUS channel.

Channel bus access time slot: the method comprises the steps that channel data of a master station are transmitted to slave stations from the master station, the channel data of the slave stations are received by the master station until the master station is stopped, and the elapsed time is an exchange time slot; the switch slot is fixedly defined to be 19 microseconds (μ s), and two slot gaps are defined to be 1 microsecond (μ s);

the IO slave station channel periods in the ready list do not exist, an opportunistic equal sequence access mechanism is adopted by default, and the strict certainty criterion at this time is as follows:

where Δ T is the maximum time slot, T is the access period of all channels, N is the total number of channels, T_ctrlIs the control period.

Under the condition, the channel access time and the sampling control time of the IO slave station are strictly determined by taking the time spent by all the channels to access in sequence once as a period. Examples are: the maximum time slot is 20 microseconds, the total time consumption T of 127 slave stations is 2.54 milliseconds, and the control period needs to be more than 5.08 milliseconds, so that the access time of each channel and the sampling control time of each IO slave station are strictly determined;

if the channel period of the IO slave station is configured in the ready list, priority access control of the ready list is adopted, and the strict time certainty criterion at this time is as follows:

where Δ T is the maximum time slot, Ti is the strict time deterministic channel period N is the strict time deterministic channel total number, and C is the time slot constant.

The time slot constant C is used for reserving a certain time slot for the access time non-deterministic channel so as to meet the random data access requirement; and if the sum of the access frequencies of the channels strictly determined by all the access time is less than the bus time slot bandwidth after deducting the time slot constant, acquiring all the access requirements of the channels at the moment of the least common multiple of the cycle. For example, C equals 1000, leaving the non-deterministic channel at least 1000 slots, so long as: the sum of the access frequencies of all the periodic channels is less than 499000, the access time of the channels on the bus and the acquisition control time of the IO slave station realize the certainty that the time strictness is from high to low according to the priority.

FIG. 8 is a schematic diagram of the uplink switching control of the FASTDP-BUS master station channel according to the embodiment of the present invention; fig. 9 is a schematic diagram of uplink switching control of the FASTDP-BUS slave channel according to the embodiment of the present invention.

The FASTDP-BUS channel exchange control mechanism is as follows: after the channel obtains the bus use right, in the specified exchange time slot, in the uplink and downlink data transmission, the data exchange between the main station and the slave station transmission data in the corresponding channel is realized through the mutual mapping of the channel address, the attribute, the channel data, the target address of the link data frame, the FC control domain and the data field;

primary station channel downlink switching control: the main station reads the downlink cache data of the channel obtained by arbitration as a link frame data field, takes the channel address as the target address of the link data frame, takes the channel type as the attribute of an FC control domain, generates a downlink data frame and forwards the downlink data frame to the bus;

primary station channel uplink switching control: the main station takes the original address of the data frame as a channel address and the FC control domain attribute as a channel type aiming at the received link data frame, finds the uplink data cache corresponding to the link data frame and stores and writes the uplink data cache;

-channel uniform precedence: after the main station downlink channel data is exchanged to the slave station, the slave station has the priority uplink channel data consistent with the channel;

-a channel multiplexing mechanism: after the data of the downlink channel of the master station is exchanged to the slave station, the slave station multiplexes the data of the time slot uplink which is inconsistent with the channel;

-idle multiplexing mechanism: after the downlink channel data of the master station is exchanged to the slave station, when the data of the slave station corresponding to the channel is not ready, starting a channel multiplexing mechanism, and uploading other channel data with inconsistent channels;

-an emergency reuse mechanism: after the main station downlink channel data is exchanged to the slave station, if the emergency channel data of the slave station is ready, a channel multiplexing mechanism is started immediately, and the emergency channel data is preferentially uploaded;

-slave channel uplink switching control: the slave station arbitrates the access channels according to the sequence of the emergency data to the consistent channel and then to the inconsistent channel aiming at the received downlink data channel of the master station; and respectively starting an emergency multiplexing mechanism, a channel consistent priority mechanism and an idle multiplexing mechanism according to the arbitrated channel attributes, and mapping channel data to link data frames.

The data transmission control process of the FASTDP-BUS link is as follows:

the master station application layer writes the downlink data into the channel downlink data cache;

the master station refreshes the access ready flag to be set through the channel access ready table;

the master station arbitrates the currently unique data channel with the highest priority by a channel priority arbitration mechanism;

the master station realizes the forwarding of channel downlink data to the bus in a downlink data frame manner through a master station channel downlink exchange control mechanism;

-the slave station, after receiving and processing the master station downlink data frame, immediately transmitting a slave station uplink data frame to the bus by using a slave station channel uplink switching control mechanism;

after receiving the uplink data frame of the slave station on the bus, the master station realizes the exchange from the slave station channel to the master station channel by adopting a bus master station channel uplink exchange control mechanism;

the master application layer reads the upstream data from the channel upstream data buffer.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A strictly access and sample time distributed peripheral bus system, comprising: a single bus master and at least one bus slave; the physical layer of the system adopts a dual-redundancy low-voltage differential signal LVDS bus technology; the data link layer is realized by adopting a field programmable gate array FPGA or a FASTDP-BUS protocol control chip for realizing a FASTDP-BUS link protocol, and the FASTDP-BUS protocol control chip is realized by adopting a special integrated circuit ASIC mode; the application layer adopts FASTDP-BUS application layer protocol specification, and the FPGA or FASTDP-BUS protocol control chip is mapped to the CPU of the internal address space through an industry standard system structure ISA BUS; a channel access ready table mechanism is adopted for channel access, and strict time certainty of channel access and sampling control of the distributed IO slave station is realized according to the priority of data;

the DATA link layer is divided into a link layer DATA frame containing an application DATA APP DATA field and a link layer DATA frame without the application DATA APP DATA field;

the application layer data transmission channel of the distributed peripheral bus comprises an FC control field for identifying the application layer channel arranged at the head of a link frame, and the identification of a URG channel, a NORM channel, a WAVE channel and an MNG channel is realized;

the link data transmission channel of the data link layer comprises the following components: the link layer creates and manages a time setting channel, a synchronous channel, a new searching channel and a diagnosis channel; the link layer link data channel is not provided with a transceiving cache and is directly processed by the data link layer; wherein: the time setting channel is used for transmitting a channel for setting time setting data of the distributed IO and activating the channel to set time according to a set period; the synchronous channel is used for transmitting a channel for synchronously sampling commands of the distributed IO, and activating the channel according to a set synchronous calibration period to realize sampling step sequence calibration; a new channel for transmitting a distributed IO inquiry command of a new access bus; during the idle period of the BUS, activating the channel according to the inquiry period of the IO slave station of the new access system, and inquiring and initializing the newly operated distributed IO on the FASTDP-BUS; the diagnosis channel is used for the link layer to transmit a link diagnosis command, and the channel is activated to realize diagnosis according to a set diagnosis period;

each channel of the bus carries out bus access according to a channel access ready table mechanism, wherein the channel access ready table is of a two-dimensional structure and consists of a row unit corresponding to a row and a channel, and the row unit corresponds to a channel; the method comprises fixed priority channel control, access time uncertainty channel control, NORM and IO slave station channel control; the method also comprises the steps of refreshing and controlling a time slot cycle ready flag to control the time slot cycle ready flag;

the channel access time certainty criterion is divided into: when the channel period of the IO slave station in the ready list does not exist, a sequential access mechanism with equal opportunity is adopted by default; when the channel period of the IO slave station is configured in the ready list, a priority access control mechanism of the ready list is adopted;

the arbitration mechanism of the channel access priority is as follows: the channel priority arbitration is realized by the aid of a ready zone bit set by a channel access ready table;

2. The strict access and sample time distributed peripheral bus system as recited in claim 1, wherein said link layer DATA frame containing application DATA APP DATA comprises application layer DATA; the link layer DATA frame without the application DATA APP DATA comprises an LLC DATA field indicating the field length; the application layer data comprises the following fields: sending an application layer DATA message in a cache, wherein the application layer DATA message comprises a Dest Addr field, a DUn field, a field with the whole length LE3 of an FCS field, a destination address Dest Addr field, an APP DATA field and a sum check FCS field; the APP DATA field contains a plurality of DATA fields DU; each DU is 1 byte in length;

3. The strict access and sample time distributed peripheral bus system of claim 1, wherein:

the NORM channel is used for transmitting coverable distributed IO slave station real-time data, and the data comprises sampling input data of AI and DI under the coverable and discontinuous loss condition; and the output control data of DO and AO which are periodically and continuously output by the CPU; the FASTDP-BUS BUS sets independent receiving cache and sending cache for each distributed IO slave station of the channel to form a sub-channel of the NORM channel;

the URG channel is used for transmitting the channel of the distributed IO emergency operation data which can be transmitted by the pluggable team; the FASTDP-BUS BUS only sets a common receiving cache and a common receiving cache for the channel, and the cache is shared by the emergency data of all the distributed IO slave stations;

the WAVE channel is used for transmitting data of values of the distributed IO points which cannot be covered, and the data comprises data of AI points which cannot be covered and lost, DI points SOE and EVENT data; the FASTDP-BUS only sets a public receiving cache for the channel, and the cache is shared by all the emergency data of the distributed IO slave stations;

the MNG channel is used for transmitting the channel of the distributed IO slave station configuration management data, and the data comprises equipment self-description information, query and configuration commands of data of the IO slave station operation parameters; all the distributed IO slave stations share the channel, and only one common receiving cache is shared with one common receiving cache.

4. The strict access and sampling time distributed peripheral bus system of claim 3, wherein the distributed IO slave station real-time NORM data transmission channel is specifically:

5. A method for implementing a strict access and sampling time distributed peripheral bus system, comprising:

setting a single bus master station and at least one bus slave station;

the application layer of the BUS system adopts FASTDP-BUS application layer data specification, and the FPGA or FASTDP-BUS protocol control chip is mapped to the CPU of the internal address space through an industry standard system structure ISA BUS to realize;

a channel access ready table mechanism is adopted for channel access, and strict time certainty of channel access and sampling control of the distributed IO slave station is realized according to the priority of data;