CN109962107A - The nanostructure transistor and preparation method that silicon wafer face relies on - Google Patents
The nanostructure transistor and preparation method that silicon wafer face relies on Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 193
- 239000010703 silicon Substances 0.000 title claims abstract description 193
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 191
- 239000002086 nanomaterial Substances 0.000 title claims abstract description 96
- 238000002360 preparation method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000013078 crystal Substances 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000010276 construction Methods 0.000 claims abstract description 5
- YCISZOVUHXIOFY-HKXOFBAYSA-N Halopredone acetate Chemical compound C1([C@H](F)C2)=CC(=O)C(Br)=C[C@]1(C)[C@]1(F)[C@@H]2[C@@H]2CC[C@](OC(C)=O)(C(=O)COC(=O)C)[C@@]2(C)C[C@@H]1O YCISZOVUHXIOFY-HKXOFBAYSA-N 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 76
- 239000002070 nanowire Substances 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052681 coesite Inorganic materials 0.000 claims description 16
- 229910052906 cristobalite Inorganic materials 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 16
- 229910052682 stishovite Inorganic materials 0.000 claims description 16
- 229910052905 tridymite Inorganic materials 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052451 lead zirconate titanate Inorganic materials 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 240000007594 Oryza sativa Species 0.000 claims description 2
- 235000007164 Oryza sativa Nutrition 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 229910000765 intermetallic Inorganic materials 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims description 2
- 235000009566 rice Nutrition 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 description 17
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 10
- 238000005260 corrosion Methods 0.000 description 7
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000003518 caustics Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
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- 239000007788 liquid Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 230000000750 progressive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nanotechnology (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of nanostructure transistors that the silicon wafer face based on silicon substrate on insulating layer relies on, which includes: silicon substrate；Oxide insulating layer, production is on a silicon substrate；The nanostructure that silicon wafer face relies on, is produced on oxidation insulating layer；The silicon conductance table top of source region and drain region, it is produced on oxide insulating layer, it is located at the both ends of the nanostructure of silicon wafer face dependence and the nanostructure both ends relied on silicon wafer face is connect, the nanostructure which relies on forms similar I-shape construction with the silicon conductance table top in source region, drain region；Thin oxide layer is wrapped in the surface for the nanostructure that source region, drain region silicon conductance table top and silicon wafer face rely on；Gate Electrode Conductive item is wrapped in the thin oxide layer of the nanostructure of silicon wafer face dependence, and perpendicular to the nanostructure that silicon wafer face relies on.The present invention discloses a kind of methods for relying on production nanostructure transistor using crystal face.
Description
Technical field
The present invention relates to nanostructure transistor fabrication fields, more particularly to one kind is based on silicon (SOI) substrate on insulating layer
The nanostructure transistor arrangement and preparation method thereof that relies on of silicon wafer face.
Background technique
With being constantly progressive for ic manufacturing technology, metal-oxide semiconductor fieldeffect transistor at present
(MOSFET) characteristic size has been carried out 14nm, and physics grid length is even already less than 20nm.Transistor size is by mole fixed
Rule, which continues to reduce, faces huge challenge, therefore the electronic device based on nano wire has become a hot topic of research.
Anisotropic etch refers to that the different crystal orientations of silicon have different corrosion rates.The corrosion rate of silicon in addition to crystalline substance
Face has outside the Pass, is also influenced by corrosive agent type, proportion, reaction temperature.According to these characteristics, suitable crystal face can choose
Oneself desired device architecture is manufactured, electricity can regulate and control corrosion by selecting different corrosive agent types, proportion, reaction temperature
Rate finally corrodes ideal crystal orientation section out.
The essence for the silicon corrosion technology that crystal orientation relies on is the anisotropic etch of silicon.A kind of mode of the prior art is to pass through
The angle for adjusting facet and { 111 } plane, using silicon wafer, anisotropic etch manufacture has small flash of light angle in KOH aqueous solution
The triangular groove of degree (being lower than 5 °)；The another way of the prior art utilizes etching characteristic of { 110 } silicon wafer in KOH solution
The inclined electrode of the sub-micron capacitive gaps of edge (111) plane of generation realizes orthogonal tuning, and having made has inclination orthogonal
Tune the New Resonance gyroscope of electrode.
Summary of the invention
(1) technical problems to be solved
In view of this, the main purpose of the present invention is to provide a kind of silicon wafer faces for being based on Silicon-on-insulator (SOI) substrate
The nanostructure transistor and preparation method of dependence, keep silicon nanostructure surface more smooth, effectively control the table of channel region
Face state, to realize more preferably threshold value, subthreshold swing and current on/off ratio.
(2) technical solution
In order to achieve the above objectives, it is relied on the present invention provides a kind of silicon wafer face based on Silicon-on-insulator (SOI) substrate
Nanostructure transistor, comprising:
One silicon substrate；
Monoxide insulating layer makes on a silicon substrate；
The Fabrication of nanostructures that one silicon wafer face relies on is on oxide insulating layer；
The silicon conductance table top in one source region and a drain region is produced on oxide insulating layer, is located at receiving for silicon wafer face dependence
The both ends of rice structure are simultaneously connect, the nanostructure and source region, leakage which relies on the nanostructure both ends of silicon wafer face dependence
The silicon conductance table top in area forms one kind like I-shape construction；
Monoxide thin layer is wrapped in the surface for the nanostructure that source region, drain region silicon conductance table top and silicon wafer face rely on；
One polycrystalline grid is wrapped in the thin oxide layer of the nanostructure of silicon wafer face dependence, and perpendicular to silicon wafer face
The nanostructure of dependence；
One source electrode and drain electrode is produced in source region and drain region silicon conductance table top；
One fabrication is in polycrystalline grid.
The nanostructure that wherein the silicon wafer face relies on, which is silicon { 100 } crystal face, and silicon { 111 } crystal face connects surrounds isosceles
The silicon nanowire structure of trapezoid cross section or isoceles triangle tee section.
SiO is produced on described in wherein2Source region, drain region silicon conductance table top on insulating layer, the nanometer relied on silicon wafer face
Structure can be same doping type, or different doping types.
Silicon (SOI) in the thin oxide layer and insulating layer that the nanostructure that wherein the silicon wafer face relies on is covered with surface
Buried oxide layer is the protective layer of dry etching and anisotropic chemical attacks.
There are five types of situations for the cross section for the nanostructure that wherein the silicon wafer face relies on: isosceles trapezoid；What upper bottom was connected
Two isosceles trapezoids；Isosceles triangle；Two connected isosceles triangles of vertex；Two isosceles triangles of vertex separation.
The material that wherein oxide film layer uses is SiO2, can also be using following material as dielectric
Layer: nitrogen oxides, HfO2、Si3N4、ZrO2、Ta2O5, BST or PZT etc..
Wherein the material of the Gate Electrode Conductive item is polysilicon, polysilicon/germanium, metal, metallic compound or its mixing
Structure.
Wherein the source region and drain region metal electrode are the Ni/Al alloy material of annealing, and gate electrode is polysilicon or gold
Belong to Ti/Al.
The present invention also provides a kind of nanostructure transistors that the silicon wafer face based on Silicon-on-insulator (SOI) substrate relies on
Preparation method includes the following steps:
Step 1: taking the SOI Substrate on (100) surface；
Step 2: depositing SiO on the top silicon thin layer of the SOI Substrate2After mask layer, N-type or the p-type for injecting high concentration are miscellaneous
Matter, quick thermal annealing process；
Step 3: the SiO deposited on the SOI Substrate2Covering for region meas, drain region table top and nano wire is produced on layer
Mould figure；
Step 4 (selection): pass through dry etching, mask graph is transferred in SOI top layer silicon；
Step 5: by anisotropic chemical attacks, obtain the nanostructure that silicon wafer face relies on so that silicon { 100 } crystal face and
Silicon { 111 } crystal face, which connects, surrounds the silicon nanowire structure in isosceles trapezoid section or isoceles triangle tee section；
Step 6: by the SiO of surface of silicon nanowires and source region, the covering of drain region silicon conductance mesa surfaces2Mask layer removal, warp
Thermal oxide forms SiO2Wrapping layer；
Step 7: depositing conductive material produces the Gate Electrode Conductive item perpendicular to silicon nanowires；
Step 8: preparing source electrode, leakage respectively on source region silicon conductance table top, drain region silicon conductance table top and Gate Electrode Conductive item
Electrode and gate electrode complete the preparation of device.
(3) beneficial effect
It can be seen from the above technical proposal that the invention has the following advantages:
(1) nanostructure transistor that silicon wafer face provided by the invention based on Silicon-on-insulator (SOI) substrate relies on
Preparation method can accurately control the width of nano wire relatively, keep silicon nanostructure surface more smooth, effectively control channel region
The surface state in domain improves grid to the control ability of channel, to realize more preferably threshold value, subthreshold swing and current switch
Than.
(2) nanostructure transistor that silicon wafer face provided by the invention based on Silicon-on-insulator (SOI) substrate relies on
Preparation method, there are five types of situations in the section for the nanostructure for relying on silicon wafer face: isosceles trapezoid；Isosceles triangle；Upper bottom is connected
Two isosceles trapezoids；Two connected isosceles triangles of vertex；Two isosceles triangles of vertex separation.
Detailed description of the invention
To further illustrate technology contents of the invention, detailed description are as follows with attached drawing in conjunction with the embodiments, in which:
Fig. 1 is the nanostructure that the silicon wafer face provided in an embodiment of the present invention based on Silicon-on-insulator (SOI) substrate relies on
The schematic perspective view of transistor；
Fig. 2 is the nanostructure that the silicon wafer face provided in an embodiment of the present invention based on Silicon-on-insulator (SOI) substrate relies on
The planar structure schematic diagram of transistor；
Fig. 3 is the nanostructure that the silicon wafer face provided in an embodiment of the present invention based on Silicon-on-insulator (SOI) substrate relies on
Transistor does not carry out the SOI schematic cross-section of chemical attack；
Fig. 4 is the nanostructure that the silicon wafer face provided in an embodiment of the present invention based on Silicon-on-insulator (SOI) substrate relies on
Transistor is along A-A ' extent of corrosion sectional view；
Fig. 5 A-5G is respectively that the silicon wafer face provided in an embodiment of the present invention based on Silicon-on-insulator (SOI) substrate relies on
Nanostructure transistor varying cross-section nanowire structure stereochemical structure；
Fig. 6 is the nanostructure that the silicon wafer face provided in an embodiment of the present invention based on Silicon-on-insulator (SOI) substrate relies on
Transistor preparation method flow chart.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
The embodiment of the present invention utilizes etching characteristic of { 100 } silicon wafer in tetramethyl ammonium hydroxide solution (TMAH), passes through
It utilizes the biggish corrosion in { 100 }, { 111 } face to select ratio, has made the silicon that cross section has isosceles triangle and isosceles trapezoid to constitute
Nanowire structure.
For the method for traditional production nano wire using electron beam lithography, electronics art photoetching technique cannot get 10nm
Within width.The technology used herein is combined based on electron beam lithography and chemical attack, obtained crystal-facet-dependent
Silicon nanostructure surface it is more smooth, the surface state of channel region is effectively controlled, to realize more preferably threshold value, subthreshold
It is worth the amplitude of oscillation and current on/off ratio.
The embodiment of the present invention proposes a kind of method of nanostructure that the dependence of silicon wafer face is prepared using chemical attack technology,
Accurate corrosion can be realized by controlling its crystal orientation, open a technical strategies for the preparation of nanostructure transistor.
Please refer to shown in Fig. 1-6, the embodiment of the present invention provide it is a kind of based on the silicon wafer face of Silicon-on-insulator (SOI) substrate according to
Bad nanostructure transistor, comprising:
One silicon substrate 10；
Monoxide thin layer 11 is produced on silicon substrate 10；
Nanostructure 12 that one silicon wafer face relies on (silicon wafer face rely on the nanostructure of growth that refers to according to specific crystal face into
Row growth), it is produced on oxide insulating layer 11, the cross section of the nanostructure can be there are five types of situation: isosceles trapezoid, isosceles
Two isoceles triangles that two connected isosceles triangles of two connected isosceles trapezoids of triangle, upper bottom, vertex, vertex separate
Shape；
The silicon conductance table top 14 of one source region silicon conductance table top 13 and a drain region, is produced on oxide insulating layer 11, respectively
Positioned at silicon wafer face rely on nanostructure 12 both ends simultaneously with silicon wafer face rely on 12 both ends of nanostructure connect, the silicon wafer face according to
Bad nanostructure 12 forms a similar I-shape construction, source region with the silicon conductance table top 14 in source region silicon conductance table top 13, drain region
The nanostructure 12 that table top 13, drain region table top 14 and crystal face rely on can be same doping type: N-type or p-type are also possible to not
Same doping type, doping concentration are 1 × 1019-1×1021cm-3；
Monoxide thin layer (being not drawn into figure) is wrapped in source region silicon conductance table top 13, drain region silicon conductance table top 14 and silicon wafer
The surface for the nanostructure 12 that face relies on, wherein the material of thin oxide layer can be nitrogen oxides, HfO2、ZrO2、Ta2O5,
It can be insulating dielectric materials Si3N4, BST or PZT；
One Gate Electrode Conductive item 15 is wrapped in the thin oxide layer of the nanostructure 12 of silicon wafer face dependence, and perpendicular to silicon
The nanostructure 12 that crystal face relies on, wherein the material of the Gate Electrode Conductive item 15 is polysilicon, polysilicon/germanium, metal, metal
Compound or its mixed structure；
One source electrode 16 and drain electrode 17 are produced on source region silicon conductance table top 13 and drain region silicon conductance table top 14,
In the source electrode 16 and drain electrode 17 and source electrode table top 13 and the drain electrode realization Ohmic contact of table top 14；
One gate electrode 18 is produced on Gate Electrode Conductive item 15, and wherein the gate electrode 18 and Gate Electrode Conductive item 15 realize that ohm connects
Touching.
Referring again to shown in Fig. 1-6, the embodiment of the present invention provides a kind of silicon wafer face for being based on Silicon-on-insulator (SOI) substrate
The production method for relying on nanostructure transistor, includes the following steps:
Step 1: taking Silicon-on-insulator (SOI, silicon substrate 10- buried oxide layer 11- the push up silicon thin layer) substrate on (100) surface；
Step 2: depositing SiO on the top silicon thin layer of the SOI Substrate2After mask layer, N-type or the p-type for injecting high concentration are miscellaneous
Matter, quick thermal annealing process wherein SiO2Mask layer with a thickness of 10-50nm, doping concentration is 1 × 1019-1×1021cm-3, move back
500 DEG C -1000 DEG C of fiery temperature, annealing time 10-20s；
Step 3: passing through photoetching and SiO2Etching, the SiO deposited on the SOI Substrate2Region meas is produced on hard exposure mask
131, the mask graph of drain region table top 141 and nano wire 121；
Step 4 (selection): pass through dry etching, mask graph is transferred in SOI top layer silicon, obtain region meas 13,
Drain region table top 14, nano wire 122；
Step 5: by anisotropic chemical attacks, the nanostructure 12 that silicon wafer face relies on is obtained, so that silicon { 100 } crystal face
Connect with silicon { 111 } crystal face and surrounds the silicon nanowire structure in isosceles trapezoid section or isoceles triangle tee section；
In the step, there are five types of situations for the cross section of nanostructure: two connected isosceles trapezoids of isosceles trapezoid, upper bottom,
Two isosceles triangles that two connected isosceles triangles of isosceles triangle, vertex, vertex separate.
If in Silicon-on-insulator top layer silicon with a thickness of H, with SiO2Depth for hard mask etching top layer silicon is h, SiO2For
Hard exposure mask width is w, then:
(1) as h=0, the cross section of nanostructure is isosceles trapezoid or isosceles triangle；
(a) when w >=H, the cross section of nanostructure is isosceles trapezoid；
(b) when w < H, the cross section of nanostructure is isosceles triangle；
(2) as 0 < h < H, the cross section of nanostructure is two isosceles trapezoids that upper bottom is connected；
(a) (h1 is etching depth, and h2 is non-etching depth) when 0 < h < H/2, the cross section of nanostructure is h1 < h2
Connected two isosceles trapezoids in upper bottom；
(b) when h=H/2, two connected isosceles trapezoids of the upper bottom that the cross section of nanostructure is h1=h2；
(c) when H/2 < h < H, two connected isosceles trapezoids of the upper bottom that the cross section of nanostructure is h1 > h2；
(3) when h=H=w × tan54.7 °, the cross section of nanostructure is two isosceles triangles that vertex is connected；
(4) as h=H > w × tan54.7 °, the cross section of nanostructure is two isosceles triangles of vertex separation；
Step 6: 12 surface of silicon nanostructure and source region silicon conductance table top 13, drain region silicon conductance mesa surfaces 14 are covered
SiO2Mask layer is removed with hydrofluoric acid solution, forms SiO through thermal oxide2Wrapping layer；
Step 7: depositing conductive material produces the Gate Electrode Conductive item 15 perpendicular to silicon nanowires；
Step 8: making source electricity respectively on source region silicon conductance table top 13, drain region silicon conductance table top 14 and Gate Electrode Conductive item 15
Pole 16, drain electrode 17 and gate electrode 18, complete the preparation of device.
Embodiment
Please refer to shown in Fig. 1-6, the embodiment of the present invention provide it is a kind of based on the silicon wafer face of Silicon-on-insulator (SOI) substrate according to
Bad nanostructure transistor, comprising:
One silicon substrate 10, wherein silicon substrate with a thickness of 725nm；
Monoxide thin layer 11 is produced on silicon substrate 10, and wherein SiO2 layers with a thickness of 145nm,；
The nanostructure 12 that one silicon wafer face relies on, is produced on oxide insulating layer 11, the nano junction which relies on
Structure is 2 μm long, and cross section is that bottom is the isosceles triangle that a height of two vertex 88nm 62.31nm are connected；
The silicon conductance table top 14 of one source region silicon conductance table top 13 and a drain region, is produced on oxide insulating layer 11, respectively
Positioned at silicon wafer face rely on nanostructure 12 both ends simultaneously with silicon wafer face rely on 12 both ends of nanostructure connect, the silicon wafer face according to
Bad nanostructure 12 forms a similar I-shape construction with the silicon conductance table top 14 in source region silicon conductance table top 13, drain region, wherein
The nanostructure 12 that region meas 13, drain region table top 14 and crystal face rely on is p-type boron doping, and doping concentration is 1 × 1020cm-3,
Source region and drain region silicon conductance table top with a thickness of 88nm；
Monoxide thin layer (being not drawn into figure) is wrapped in source region silicon conductance table top 13, drain region silicon conductance table top 14 and silicon wafer
The surface for the nanostructure 12 that face relies on, wherein the material of thin oxide layer is SiO2, with a thickness of 20nm；
One Gate Electrode Conductive item 15 is wrapped in the thin oxide layer of the nanostructure 12 of silicon wafer face dependence, and perpendicular to silicon
The nanostructure 12 that crystal face relies on, wherein Gate Electrode Conductive strip material is polysilicon；
One source electrode 16 and drain electrode 17 are produced on source region silicon conductance table top 13 and drain region silicon conductance table top 14, should
The making material of source electrode 16 and drain electrode 17 is Ni/Al, realizes Ohmic contact with source electrode table top 13 and drain electrode table top 14；
One gate electrode 18 is produced in polycrystalline grid 15, and the making material of the grid 18 is Ti/Al, with polycrystalline grid
15 realize Ohmic contact.
Refering to what is shown in Fig. 6, the embodiment of the present invention proposes that the crystal face based on SOI substrate relies on the production of nanostructure transistor
Method specifically comprises the following steps:
Step 1: take Silicon-on-insulator (SOI) substrate on (100) surface, top layer silicon with a thickness of 88nm, buried oxide layer 11
With a thickness of 145nm, silicon substrate 10 with a thickness of 725nm；
Step 2: plasma enhanced chemical vapor deposition (PECVD) technology is utilized on the top silicon thin layer of the SOI Substrate
Deposit SiO2After mask layer, the p-type boron impurity of high concentration is injected, quick thermal annealing process, wherein SiO2Mask layer with a thickness of
20nm, doping concentration are 1 × 1020cm-3, 1000 DEG C of annealing temperature, annealing time 20s；
Step 3: passing through photoetching and SiO2Etching, the SiO deposited on the SOI Substrate2Region meas is produced on hard exposure mask
131, the mask graph of drain region table top 141 and nano wire 121；
Step 4 (selection): pass through dry etching, mask graph is transferred in SOI top layer silicon, obtain region meas 13,
Drain region table top 14, nano wire 122, three with a thickness of 88nm；
Step 5: using tetramethylammonium hydroxide (TMAH) solution, by anisotropic chemical attacks, it is brilliant to obtain silicon { 100 }
Face connects with silicon { 111 } crystal face surrounds the silicon nanowire structure 12 for the isoceles triangle tee section that two vertex are connected, wherein transversal
It is 62.31nm, the tetramethyl hydrogen-oxygen that a height of 44nm, TMAH are 10% by 20ml mass fraction that two etc., which are wanted the bottom of triangle, in face
Change ammonium, 60ml deionized water and 10ml isopropanol to be formulated, the temperature of corrosive liquid is maintained using 50 DEG C of water-baths；
Step 6: 12 surface of silicon nanostructure and source region silicon conductance table top 13, drain region silicon conductance mesa surfaces 14 are covered
SiO2Mask layer is removed with hydrofluoric acid solution, and thermal oxide forms the SiO of 20nm thickness under the conditions of 900 DEG C2Wrapping layer, SiO2Thickness
Degree is 20nm；
Step 7: by low-pressure chemical vapor deposition (LPCVD) depositing conductive material, producing perpendicular to silicon nanowires
Gate Electrode Conductive item 15, with a thickness of 200nm；
Step 8: by photoetching, evaporated metal, removing, annealing, in source region silicon conductance table top 13, drain region silicon conductance table top 14
With source electrode 16, drain electrode 17 and gate electrode 18 are made on Gate Electrode Conductive item 15 respectively, complete the preparation of device.
Particular embodiments described above, to the purpose of the embodiment of the present invention, technical scheme and beneficial effects carried out into
One step is described in detail, it should be understood that the above is only a specific embodiment of the present invention, is not limited to this hair
Bright, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done are all contained in of the invention
In protection scope.
Claims (10)
1. a kind of nanostructure transistor that the silicon wafer face based on silicon substrate on insulating layer relies on, which is characterized in that
Include:
One silicon substrate；
Monoxide insulating layer makes on a silicon substrate；
The nanostructure that one silicon wafer face relies on, is produced on oxide insulating layer；
The silicon conductance table top of one source region and a drain region, is produced on oxide insulating layer, is located at receiving for silicon wafer face dependence
The both ends of rice structure are simultaneously connect, the nanostructure and source region, leakage which relies on the nanostructure both ends of silicon wafer face dependence
The I-shape construction that the silicon conductance table top in area forms a source region and drain region is wide and nanostructure is narrow
Monoxide thin layer is wrapped in the surface for the nanostructure that source region, drain region silicon conductance table top and silicon wafer face rely on；
One Gate Electrode Conductive item is wrapped in the thin oxide layer of the nanostructure of silicon wafer face dependence, and rely on perpendicular to silicon wafer face
Nanostructure；
One source electrode and drain electrode is produced in source region and drain region silicon conductance table top；
One fabrication is on Gate Electrode Conductive item.
2. the nanostructure transistor that the silicon wafer face according to claim 1 based on silicon substrate on insulating layer relies on, special
Sign is, wherein the oxide insulating layer is produced on (100) surface of silicon substrate, the nanostructure that the silicon wafer face relies on
For connect from silicon { 100 } crystal face along a section in epitaxial growth direction and silicon { 111 } crystal face surround isosceles trapezoid section or
The silicon nanowire structure of isoceles triangle tee section.
3. the nanostructure transistor that the silicon wafer face according to claim 1 based on silicon substrate on insulating layer relies on, special
Sign is, wherein the source region being produced on oxide insulating layer, drain region silicon conductance table top, the nanometer relied on silicon wafer face
Structure is same doping type, or different doping types.
4. the nanostructure transistor that the silicon wafer face according to claim 1 based on silicon substrate on insulating layer relies on, special
Sign is that the buried oxide layer of silicon is dry in the thin oxide layer and insulating layer that the nanostructure that wherein silicon wafer face relies on is covered with surface
The protective layer of method etching and anisotropic chemical attacks.
5. the nanostructure transistor that the silicon wafer face according to claim 1 based on silicon substrate on insulating layer relies on, special
Sign is that the section for the nanostructure that silicon wafer face relies on includes following situations:
Isosceles trapezoid；Isosceles triangle；Two connected isosceles trapezoids of upper bottom；Two connected isosceles triangles of vertex；Vertex
Two isosceles triangles of separation.
6. the nanostructure transistor that the silicon wafer face according to claim 1 based on silicon substrate on insulating layer relies on, special
Sign is, wherein the material that the oxide film layer uses is SiO2, can also be using following material as dielectric
Layer: nitrogen oxides, HfO2、Si3N4、ZrO2、Ta2O5, BST or PZT etc..
7. the nanostructure transistor that the silicon wafer face according to claim 6 based on silicon substrate on insulating layer relies on, special
Sign is, wherein the material of the Gate Electrode Conductive item includes one or more of:
Polysilicon, polysilicon/germanium, metal and metallic compound.
8. the nanostructure transistor that the silicon wafer face according to claim 1 based on silicon substrate on insulating layer relies on, special
Sign is, wherein the metal electrode of the source region and drain region is the Ni Al alloy material of annealing, gate electrode is polysilicon or gold
Belong to Ti Al.
9. a kind of preparation method for the nanostructure transistor that the silicon wafer face based on silicon substrate on insulating layer relies on, including walk as follows
It is rapid:
Take the SOI Substrate on (100) surface；
SiO is deposited on the top silicon thin layer of the SOI Substrate2After mask layer, N-type or p type impurity, thermal anneal process are injected；
The SiO deposited on the SOI Substrate2The mask graph of region meas, drain region table top and nano wire is produced on layer；
By anisotropic chemical attacks, the nanostructure that silicon wafer face relies on is obtained, so that silicon { 100 } crystal face and silicon { 111 } are brilliant
Face, which connects, surrounds the silicon nanowire structure in isosceles trapezoid section or isoceles triangle tee section；
The SiO of nanostructured surface and source region, the covering of drain region silicon conductance mesa surfaces that silicon wafer face is relied on2Mask layer removal, warp
Thermal oxide forms SiO2Wrapping layer；
Depositing conductive material produces the Gate Electrode Conductive item of the nanostructure relied on perpendicular to silicon wafer face；
Make source electrode, drain electrode and grid electricity respectively on source region silicon conductance table top, drain region silicon conductance table top and Gate Electrode Conductive item
The preparation of device is completed in pole.
10. preparation method according to claim 9, which is characterized in that further include turning mask graph by dry etching
It moves on in SOI top layer silicon.
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