CN109962019A - A kind of fan-out-type wafer level packaging structure and method - Google Patents
A kind of fan-out-type wafer level packaging structure and method Download PDFInfo
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- CN109962019A CN109962019A CN201711401013.XA CN201711401013A CN109962019A CN 109962019 A CN109962019 A CN 109962019A CN 201711401013 A CN201711401013 A CN 201711401013A CN 109962019 A CN109962019 A CN 109962019A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of fan-out-type wafer level packaging structure and method, includes at least: re-wiring layer；It is formed in the metal coupling of the re-wiring layer upper surface, the metal coupling is electrically connected with the re-wiring layer；It is formed in the non-conductive flexible layer of the re-wiring layer upper surface；It is inverted at least one chip of non-conductive flexible layer upper surface, chip, which is bonded to be electrically connected with metal coupling, is routed through the non-conductive flexible layer；It is formed in the plastic packaging layer of non-conductive flexible layer upper surface and the encapsulation chip.Since non-conductive flexible layer of the invention has the function of deformation under stress, therefore, when being bonded the chip of multiple and different types, different height on non-conductive flexible layer, under downward pressure, non-conductive flexible layer can generate deformation, make to expose embedded in metal coupling therein, so as to once be bonded being electrically connected with corresponding metal coupling by all chips using same technique, it does not need to separate and carries out technological operation, enormously simplify technique.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of fan-out-type wafer level packaging structure and side
Method.
Background technique
With the fast development of integrated circuit manufacturing industry, requirement of the people to the encapsulation technology of integrated circuit is also constantly mentioned
Height, existing encapsulation technology include BGA Package (BGA), chip size packages (CSP), wafer level packaging (WLP), three
Dimension encapsulation (3D) and system encapsulation (SiP)) etc..Wherein, wafer level packaging (WLP) is since its outstanding advantage is gradually by big portion
The semiconductor manufacturers divided are used, its wholly or largely processing step is complete on the silicon wafer of process before being completed
At, disk is finally cut directly into the individual devices of separation.Wafer level packaging (WLP) has the advantages that its uniqueness: encapsulation
It is high in machining efficiency, it can be with multiple disk simultaneous processings；Has the advantages that Flip-Chip Using, i.e., gently, thin, short, small；With preceding work
Sequence is compared, and only increases two processes of pin rewiring (RDL) and stud bump making, remaining is entirely traditional handicraft；It reduces
Multiple test in conventional package.Therefore each large-scale IC package company puts into the research of this kind of WLP, exploitation one after another in the world
And production.
Fan-out-type wafer-level packaging (Fan-out wafer level packaging, FOWLP) due to have miniaturization,
The advantages that low cost and high integration, in the manufacturers such as mobile device manufacturer, attention rate with higher.Fan-out-type wafer
Movement/wireless market of grade encapsulation most suitable high request at present, and to the markets of other concern high-performance and small size,
With very strong attraction.
In the prior art, fan-out-type wafer-level packaging generally comprises the steps: sequentially forming first in carrier surface viscous
Close layer, re-wiring layer；Then it is coated with to form a cured layer in rewiring layer surface, litho machine then is carried out to cured layer
The logical techniques such as etching, form through-hole in cured layer, fill convex block in through-holes later；Again by multiple chips and bump bond；
Carrier and adhesive layer are finally removed, carries out planting ball reflux technique.It but if is different type, no with the chip of bump bond
Level semiconductor chip and electronic component since cured layer is the one layer of hard layer formed after solidifying, then are solidifying
Convex block is formed in layer, this process and structure will lead to the semiconductor for needing different technique to come to different type, different height
Chip and electronic component are bonded respectively, complex process.
Therefore it provides a kind of new fan-out-type wafer level packaging structure and method are the classes that art technology needs to solve
Topic.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of fan-out-type wafer-level packaging knots
Structure and method, for solving the problems, such as that chip bonding process is complicated in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of fan-out-type wafer-level packaging method, described
Method at least includes the following steps:
1) carrier is provided, Yu Suoshu carrier upper surface forms adhesive layer；
2) Yu Suoshu adhesive layer upper surface forms re-wiring layer；
3) Yu Suoshu re-wiring layer upper surface forms metal coupling, the metal coupling and re-wiring layer electricity
Even；
4) Yu Suoshu re-wiring layer upper surface forms the non-conductive flexible layer for covering the metal coupling；
5) at least one chip is provided, by the chip upside down in non-conductive flexible layer upper surface, and to the core
Piece applies certain pressure, so that the non-conductive flexible layer is generated deformation, so that the chip be made to be bonded with the metal coupling
It is electrically connected；
6) the plastic packaging layer of the encapsulation chip is formed in non-conductive flexible layer upper surface.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention, the method also includes following steps
It is rapid:
7) carrier and adhesive layer are removed, the lower surface of the re-wiring layer is exposed；
8) soldered ball is formed in the lower surface of the re-wiring layer.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention, the material of the carrier include glass
One kind of glass, silicon, silica, metal and ceramic material.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention, the adhesive layer include adhesive tape, lead to
Cross one of adhesive glue or the epoxy resin of spin coating proceeding production.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention, the re-wiring layer include medium
Layer and at least one layer of metal wiring layer being formed in the dielectric layer, wherein the metal coupling and the metal wiring layer
It is electrically connected.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention, the non-conductive flexible layer include poly-
Close one of object or glue.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention, the non-conductive flexible layer pass through rotation
Turn coating or tape paste method is formed in the re-wiring layer upper surface.
The scheme of a kind of optimization as fan-out-type wafer-level packaging method of the present invention, in the step 4), in described heavy
New route layer upper surface forms the non-conductive flexible layer for covering the metal coupling, comprising:
The non-conductive flexible layer surface or the metal coupling are exposed at the top of the metal coupling by described non-
Conductive flexible layer is completely covered.
The scheme of a kind of optimization as fan-out-type wafer-level packaging method of the present invention, when the metal coupling is by described non-
When conductive flexible layer is completely covered, the non-conductive flexible layer beyond the metal coupling thickness range between 10um~
Between 500um, in the step 5), under an applied pressure, the non-conductive flexible layer generates deformation, keeps the metal convex
The top of block, which passes through, the non-conductive flexible layer and exposes the non-conductive flexible layer surface, thus make the chip with it is described
Metal coupling bonding is electrically connected.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention, the chip include semiconductor chip
At least one of with electronic component；The preparation method of the semiconductor chip includes:
The wafer that a surface has metal pad 5-1) is provided, Yu Suoshu crystal column surface forms passivation layer；
5-2) the graphical passivation layer, exposes the metal pad；
5-3) sliver obtains the independent semiconductor chip with the pad and the passivation layer, wherein the metal
Pad is bonded with the metal coupling and is electrically connected.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention in the step 6), forms encapsulation
The technique of the plastic packaging layer of the chip includes: Shooting Technique, compressing and forming process, printing technology, transfer modling technique, liquid
One of sealant cures moulding process, vacuum lamination process and spin coating proceeding.
A kind of scheme of optimization as fan-out-type wafer-level packaging method of the present invention, fan according to claim 1
Type wafer-level packaging method out, it is characterised in that: the plastic packaging layer includes one in polyimides, silica gel and epoxy resin
Kind.
The present invention also provides a kind of fan-out-type wafer level packaging structure, the structure is included at least:
Re-wiring layer；
It is formed in the metal coupling of the re-wiring layer upper surface, the metal coupling and re-wiring layer electricity
Even；
It is formed in the non-conductive flexible layer of the re-wiring layer upper surface；
It is inverted at least one chip of non-conductive flexible layer upper surface, the chip is bonded with the metal coupling
It is electrically connected and is routed through the non-conductive flexible layer；
It is formed in the plastic packaging layer of non-conductive flexible layer upper surface and the encapsulation chip.
A kind of scheme of optimization as fan-out-type wafer level packaging structure of the present invention, the structure further include being formed in institute
State the soldered ball of the lower surface of re-wiring layer.
A kind of scheme of optimization as fan-out-type wafer level packaging structure of the present invention, the re-wiring layer include medium
Layer and at least one layer of metal wiring layer being formed in the dielectric layer, wherein the metal coupling and the metal wiring layer
It is electrically connected.
A kind of scheme of optimization as fan-out-type wafer level packaging structure of the present invention, the non-conductive flexible layer include poly-
Close one of object or glue.
A kind of scheme of optimization as fan-out-type wafer level packaging structure of the present invention, the chip include semiconductor chip
At least one of with electronic component；The semiconductor chip includes:
Surface has the wafer of metal pad；
It is formed in the crystal column surface and exposes the passivation layer of the metal pad, wherein the pad and the gold
Belong to bump bond to be electrically connected.
A kind of scheme of optimization as fan-out-type wafer level packaging structure of the present invention, the plastic packaging layer include polyamides Asia
One of amine, silica gel and epoxy resin.
As described above, fan-out-type wafer level packaging structure of the invention and method, have the advantages that of the invention first
The re-wiring layer upper surface formed metal coupling, re-form the non-conductive flexible layer for covering the metal coupling, when
Be bonded on the non-conductive flexible layer multiple and different types, the semiconductor chip of different height, electronic component or other
When the device of what type, in the case where applying certain pressure, the non-conductive flexible layer is made to generate deformation, so as to using same
All semiconductor chips, electronic component and other devices and corresponding metal coupling are once carried out key by one technique
Conjunction is electrically connected, and does not need separately to be operated, and simplifies technique.Structure of the invention and method are simple, have in field of semiconductor manufacture
Broad application prospect.
Detailed description of the invention
Fig. 1 is the flow diagram of fan-out-type wafer-level packaging method of the present invention.
The structural schematic diagram that Fig. 2 is presented for the step S1 of fan-out-type wafer-level packaging method of the present invention.
The structural schematic diagram that Fig. 3 is presented for the step S2 of fan-out-type wafer-level packaging method of the present invention.
The structural schematic diagram that Fig. 4 is presented for the step S3 of fan-out-type wafer-level packaging method of the present invention.
The structural schematic diagram that Fig. 5 a~5b is presented for the step S4 of fan-out-type wafer-level packaging method of the present invention.
The structural schematic diagram that Fig. 6 is presented for the step S5 of fan-out-type wafer-level packaging method of the present invention.
The structural schematic diagram that Fig. 7 is presented for the step S6 of fan-out-type wafer-level packaging method of the present invention.
The structural schematic diagram that Fig. 8 is presented for the step S7 of fan-out-type wafer-level packaging method of the present invention.
The structural schematic diagram that Fig. 9 is presented for the step S8 of fan-out-type wafer-level packaging method of the present invention.
The knot that Figure 10 is presented for the step 5-1 for preparing semiconductor chip in fan-out-type wafer-level packaging method of the present invention)
Structure schematic diagram.
The knot that Figure 11 is presented for the step 5-2 for preparing semiconductor chip in fan-out-type wafer-level packaging method of the present invention)
Structure schematic diagram.
The knot that Figure 12 is presented for the step 5-3 for preparing semiconductor chip in fan-out-type wafer-level packaging method of the present invention)
Structure schematic diagram.
Component label instructions
1 carrier
2 adhesive layers
3 re-wiring layers
31 dielectric layers
32 metal wiring layers
4 metal couplings
5 non-conductive flexible layers
6 chips
61 semiconductor chips
611 wafers
612 metal pads
613 passivation layers
62 electronic components
7 plastic packaging layers
8 soldered balls
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also be by addition different specific
Embodiment is embodied or practiced, and the various details in this specification can also not carried on the back based on different viewpoints and application
From carrying out various modifications or alterations under spirit of the invention.
Please refer to attached drawing.It should be noted that only the invention is illustrated in a schematic way for diagram provided in the present embodiment
Basic conception, only shown in schema then with related component in the present invention rather than component count, shape when according to actual implementation
Shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its component
Being laid out kenel may also be increasingly complex.
As shown in Figure 1, the present invention provides a kind of fan-out-type wafer-level packaging method, the method includes at least following step
It is rapid:
Step S1 is first carried out, as shown in Fig. 2, providing a carrier 1,1 upper surface of Yu Suoshu carrier forms adhesive layer 2.
The carrier 1 can provide rigid structure or matrix for subsequent production adhesive layer 2.As an example, the carrier 1
Material include glass, silicon, silica, metal and ceramic material one kind.In the present invention, the carrier 1 can be round, side
Shape or other any required shapes, it is unlimited herein.In the present embodiment, the carrier 1 selects silicon material and is round.
The adhesive layer 2 is preferably selected in the subsequent process as the separating layer between re-wiring layer 3 and carrier 1
Jointing material with smooth finish surface is made, and must have certain binding force with re-wiring layer 3, to guarantee cloth again
Line layer 3 will not generate situations such as mobile in the subsequent process, in addition, it also has stronger binding force with carrier 1, it is general next
It says, the binding force of the adhesive layer 2 and carrier 1 should be greater than the binding force with the re-wiring layer 3, in order to subsequent described
Adhesive layer 2 and the carrier 1 are separated with the re-wiring layer 3.As an example, the adhesive layer 2 can select for adhesive tape,
One of adhesive glue or epoxy resin for being made by spin coating proceeding.Preferably, in the present embodiment, the adhesive layer 2 is selected
For adhesive tape, for example, UV adhesive tape.
Then step S2 is executed, as shown in figure 3, forming re-wiring layer 3 in 2 upper surface of adhesive layer.
Specifically, as shown in figure 3, the re-wiring layer 3 includes dielectric layer 31 and is formed in the dielectric layer 31
At least one layer of metal wiring layer 32, wherein the metal coupling 4 is electrically connected with the metal wiring layer 32.
It should be noted that making the metal wiring layer 32 that the re-wiring layer 3 includes may include one layer of metal, two
Layer metal or multiple layer metal is separated with dielectric layer 31 between every layer of metal wiring layer 32.It should be noted that for the side of diagram
Just, it is not attached to together between multi-layer metal wiring layer 32 shown in attached drawing 3, still, those skilled in the art should know
Know, for the relationship that is electrically connected between each layer of metal wiring layer 32, the metal coupling 4 being subsequently formed and the metal wiring layer 32
In top layer be electrically connected, the lowest level of the soldered ball 8 being subsequently formed and the metal wiring layer 32 is electrically connected.
As an example, the metal wiring layer 3 can use one of copper, aluminium, nickel, gold, silver, titanium material or two kinds with
On combined material, and physical vaporous deposition (PVD), chemical vapour deposition technique (CVD), sputtering method, plating and change can be selected
At least one of plating method is learned to be formed.
The dielectric layer 31 can use low k dielectric.As an example, the dielectric layer 31 can use asphalt mixtures modified by epoxy resin
One of rouge, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass material, and can using such as spin coating,
The techniques such as CVD, plasma enhanced CVD form dielectric layer.
Then step S3 is executed, as shown in figure 4, forming metal coupling 4, the gold in 3 upper surface of re-wiring layer
Belong to convex block 4 to be electrically connected with the re-wiring layer 3.
As an example, the metal coupling 4 is preferably column structure, the material of the metal coupling 4 includes but is not limited to
Cu or Ni.The metal coupling 4 can be formed by techniques such as conventional thick photoresist photoetching, development, metal deposits, can also passed through
The techniques such as micro-embossing, metal deposit form the metal coupling 4.
Then step S4 is executed, as shown in Fig. 5 a or 5b, 3 upper surface of Yu Suoshu re-wiring layer, which is formed, covers the metal
The non-conductive flexible layer 5 of convex block 4.
The metal coupling 4 and non-conductive flexible layer 5 form damascene structures, and the metal coupling 4 non-is led embedded in described
In electric flexible layer 5, the requirement of non-conductive flexible layer 5 under pressure can be with deformation occurs, in order to subsequent chip 6
The metal coupling 4 in the non-conductive flexible layer 5 can be smoothly contacted under stress.As an example, described non-conductive soft
Property layer 5 may include one of flexible polymer or glue, it may for example comprise but it is not limited to polyimides, epoxy resin, polyester
(PET) etc..
As an example, the non-conductive flexible layer 5 can be formed in by rotary coating or tape paste method it is described heavy
3 upper surface of new route layer.
As an example, the structural relation of the metal coupling 4 and non-conductive flexible layer 5, comprising:
The top of the metal coupling 4 is exposed to 5 surface of non-conductive flexible layer (as shown in Figure 5 b) or the gold
Belong to convex block 4 and (as shown in Figure 5 a) is completely covered by the non-conductive flexible layer 5.
If the top of the metal coupling 4 is exposed to 5 surface of non-conductive flexible layer, subsequent chip 6 connects in bonding
When touching, chip 6 can be pressed down against the non-conductive flexible layer 5 under stress, so that the non-conductive flexible layer 5 is generated deformation, directly
It is bonded and is electrically connected with the metal coupling 4 to the chip 6；If the metal coupling 4 is covered completely by the non-conductive flexible layer 5
(thickness range of the non-conductive flexible layer beyond the metal coupling is between 10um~500um) is covered, then subsequent chip
6 in bond contact, and chip 6 can squeeze downwards under stress (pressure size is related with the size of non-conductive flexible layer and chip)
The non-conductive flexible layer 5 is pressed, so that the non-conductive flexible layer 5 is generated deformation, institute is first exposed at the top of the metal coupling 4
It states non-conductive flexible layer 5 and exposes 5 surface of non-conductive flexible layer, be then bonded and be electrically connected with the chip 6.
The present invention first makes metal coupling 4, re-forms the non-conductive flexible layer 5 for covering the metal coupling 4, is subsequent core
The bonding of piece 6 lays the foundation.
Step S5 is executed again, as shown in fig. 6, providing at least one chip 6, the chip 6 is inverted in described non-conductive
5 upper surface of flexible layer, and certain pressure is applied to the chip 6, so that the non-conductive flexible layer 5 is generated deformation, to make
The chip 6 is bonded with the metal coupling 4 and is electrically connected.
It should be noted that the chip that the chip 6 can be same type is also possible to different types of chip, Ge Gexin
The height of piece can be equal, can not also wait.As an example, the chip 6 includes semiconductor chip 61 and electronic component 62
At least one of (such as surface mount device SMD), however, it is not limited to this can also encapsulate other devices simultaneously, such as deposit
Memory device, display device, input module, power supply, voltage-stablizer etc..
As an example, the preparation method of the semiconductor chip 61 includes the following steps:
As shown in Figure 10, step 5-1 is carried out), the wafer 611 that a surface has metal pad 612, Yu Suoshu wafer are provided
611 surfaces form passivation layer 613.
As an example, the passivation layer 613 may include in silica, phosphorosilicate glass, silicon oxide carbide, silicon carbide etc.
It is a kind of.
As an example, can be using spin-coating method, chemical vapour deposition technique or plasma reinforced chemical vapour deposition method in institute
It states 611 surface of wafer and forms passivation layer 613.
As shown in figure 11, step 5-2 is carried out), the graphical passivation layer 613 exposes the metal pad 612.
As shown in figure 12, step 5-3 is carried out), the arrow direction sliver along figure obtains independent with the pad 612
With the semiconductor chip 61 of the passivation layer 613, wherein by 61 face down of semiconductor chip, make the metal pad
612 are bonded with the metal coupling 4 and are electrically connected.
In the present embodiment, two semiconductor chips 61 as shown in figure 12 and an electronic component 62 (SMD) are inverted
In 5 upper surface of non-conductive flexible layer, under an applied pressure, the non-conductive flexible layer 5 generates deformation, makes the gold
The top for belonging to convex block 4, which passes through, the non-conductive flexible layer 5 and exposes 5 surface of non-conductive flexible layer, to make described partly to lead
Body chip 61 and electronic component 62 are bonded with the metal coupling 4 to be electrically connected.
Due to non-conductive flexible layer 5 of the invention have flexibility, have the function of deformation under stress, therefore, when
Multiple and different types, the semiconductor chip 61 of different height, electronic component 62, Huo Zheqi are bonded on the non-conductive flexible layer 5
When his any kind of device, under downward pressure, the non-conductive flexible layer 5 can generate deformation, make embedded in gold therein
Belong to convex block 4 expose, so as to using same technique once by all semiconductor chips 61, electronic component 62 and its
He be bonded being electrically connected at device with corresponding metal coupling 4, does not need separately to be operated, enormously simplifies technique.
Step S6 is finally executed, encapsulates the chip 6 as shown in fig. 7, being formed in 5 upper surface of non-conductive flexible layer
Plastic packaging layer 7.
As an example, the technique for forming the plastic packaging layer 7 of the encapsulation chip 6 includes: Shooting Technique, compressing and forming process
(compressive molding), printing technology (paste printing), transfer modling technique (transfer
Molding), fluid sealant cure process (liquid encapsulant molding), vacuum lamination process
One of (vacuum lamination) and spin coating proceeding (spin coating) etc..
As an example, the plastic packaging layer 7 uses thermosetting material, it may for example comprise polymer material, resin-based materials, polyamides
One of imines, silica gel and epoxy resin etc..Chip can also be effectively ensured not by outside contamination in the plastic packaging layer 7.
In addition, also needing to be implemented step S7, as shown in figure 8, removing the carrier 1 and adhesive layer 2, expose described heavy
The lower surface of new route layer 3.
The adhesive layer 2 and carrier 1 are removed as an example, can use and the modes such as tear or be thinned, so that described
Adhesive layer 1 is separated with the re-wiring layer 3, exposes the lower surface of the re-wiring layer 3.In the present embodiment, using tearing
The mode split removes carrier 1 and adhesive layer 2, and this method is simple to operation.
Step S8 is executed again, as shown in figure 9, forming soldered ball 8 in the lower surface of the re-wiring layer 3.
As an example, the material of the soldered ball 8 includes Sn.
As shown in figure 9, the structure includes at least as follows the present invention also provides a kind of fan-out-type wafer level packaging structure:
Re-wiring layer 3；
It is formed in the metal coupling 4 of 3 upper surface of re-wiring layer, the metal coupling 4 and the re-wiring layer 3
It is electrically connected；
It is formed in the non-conductive flexible layer 5 of 3 upper surface of re-wiring layer；
It is inverted at least one chip 6 of 5 upper surface of non-conductive flexible layer, the chip 6 and the metal coupling 4
Bonding, which is electrically connected, is routed through the non-conductive flexible layer 5；
It is formed in the plastic packaging layer 7 of 5 upper surface of non-conductive flexible layer and the encapsulation chip 6.
As an example, the structure further includes the soldered ball 8 for being formed in the lower surface of the re-wiring layer 3.
As an example, the re-wiring layer 3 includes dielectric layer 31 and at least one layer being formed in the dielectric layer 31
Metal wiring layer 32, wherein the metal coupling 4 is electrically connected with the metal wiring layer 32.
As an example, the non-conductive flexible layer 5 includes one of polymer or glue.
As an example, the chip 6 includes at least one of semiconductor chip 61 and electronic component 62；The semiconductor
Chip 61 includes:
Surface has the wafer 611 of metal pad 612；
It is formed in 611 surface of wafer and exposes the passivation layer 613 of the metal welding 611, wherein the pad
612 are bonded with the metal coupling 4 and are electrically connected.
As an example, the plastic packaging layer 7 includes one of polyimides, silica gel and epoxy resin.
In conclusion the present invention provides a kind of fan-out-type wafer level packaging structure and method, include at least: rewiring
Layer；It is formed in the metal coupling of the re-wiring layer upper surface, the metal coupling is electrically connected with the re-wiring layer；Shape
Re-wiring layer upper surface described in Cheng Yu and the non-conductive flexible layer at the top of the exposure metal coupling；It is inverted in described non-lead
At least one chip of electric flexible layer upper surface, the chip are bonded with the metal coupling and are electrically connected；It is formed in described non-conductive
The plastic packaging layer of flexible layer upper surface and the encapsulation chip.Since non-conductive flexible layer of the invention has deformation under stress
Function, therefore, when being bonded the chip of multiple and different types, different height on the non-conductive flexible layer, downward
Under pressure, the non-conductive flexible layer can generate deformation, make to expose embedded in metal coupling therein, so as to using same
All chips once be bonded being electrically connected by one technique with corresponding metal coupling, do not need to separate progress technique behaviour
Make, enormously simplifies technique.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, those of ordinary skill in the art institute without departing from the spirit and technical ideas disclosed in the present invention such as
All equivalent modifications or change completed, should be covered by the claims of the present invention.
Claims (18)
1. a kind of fan-out-type wafer-level packaging method, which is characterized in that the method at least includes the following steps:
1) carrier is provided, Yu Suoshu carrier upper surface forms adhesive layer；
2) Yu Suoshu adhesive layer upper surface forms re-wiring layer；
3) Yu Suoshu re-wiring layer upper surface forms metal coupling, and the metal coupling is electrically connected with the re-wiring layer；
4) Yu Suoshu re-wiring layer upper surface forms the non-conductive flexible layer for covering the metal coupling；
5) at least one chip is provided, by the chip upside down in non-conductive flexible layer upper surface, and the chip is applied
Add certain pressure, so that the non-conductive flexible layer is generated deformation, be electrically connected so that the chip be made to be bonded with the metal coupling；
6) the plastic packaging layer of the encapsulation chip is formed in non-conductive flexible layer upper surface.
2. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: the method also includes following steps
It is rapid:
7) carrier and adhesive layer are removed, the lower surface of the re-wiring layer is exposed；
8) soldered ball is formed in the lower surface of the re-wiring layer.
3. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: the material of the carrier includes glass
One kind of glass, silicon, silica, metal and ceramic material.
4. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: the adhesive layer include adhesive tape,
One of adhesive glue or epoxy resin for being made by spin coating proceeding.
5. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: the re-wiring layer includes being situated between
Matter layer and at least one layer of metal wiring layer being formed in the dielectric layer, wherein the metal coupling and the metal line
Layer is electrically connected.
6. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: the non-conductive flexible layer includes
One of polymer or glue.
7. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: the non-conductive flexible layer passes through
Rotary coating or tape paste method are formed in the re-wiring layer upper surface.
8. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: in the step 4), Yu Suoshu
Re-wiring layer upper surface forms the non-conductive flexible layer for covering the metal coupling, comprising:
The non-conductive flexible layer surface or the metal coupling are exposed at the top of the metal coupling by described non-conductive
Flexible layer is completely covered.
9. fan-out-type wafer-level packaging method according to claim 8, it is characterised in that: when the metal coupling is by described
When non-conductive flexible layer is completely covered, thickness range of the non-conductive flexible layer beyond the metal coupling is between 10~500 μ
Between m, in the step 5), under an applied pressure, the non-conductive flexible layer generates deformation, makes the top of the metal coupling
Portion passes through the non-conductive flexible layer and exposes the non-conductive flexible layer surface, to make the chip and the metal coupling
Bonding is electrically connected.
10. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: the chip includes semiconductor
At least one of chip and electronic component；Wherein, the preparation method of the semiconductor chip includes:
The wafer that a surface has metal pad 5-1) is provided, Yu Suoshu crystal column surface forms passivation layer；
5-2) the graphical passivation layer, exposes the metal pad；
5-3) sliver obtains the independent semiconductor chip with the pad and the passivation layer, wherein the metal pad
It is bonded and is electrically connected with the metal coupling.
11. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: in the step 6), form envelope
The technique for filling the plastic packaging layer of the chip includes Shooting Technique, compressing and forming process, printing technology, transfer modling technique, liquid
One of sealant cures moulding process, vacuum lamination process and spin coating proceeding.
12. fan-out-type wafer-level packaging method according to claim 1, it is characterised in that: the plastic packaging layer includes polyamides
One of imines, silica gel and epoxy resin.
13. a kind of fan-out-type wafer level packaging structure, which is characterized in that the structure includes at least:
Re-wiring layer；
It is formed in the metal coupling of the re-wiring layer upper surface, the metal coupling is electrically connected with the re-wiring layer；
It is formed in the non-conductive flexible layer of the re-wiring layer upper surface；
It is inverted at least one chip of non-conductive flexible layer upper surface, the chip is bonded with the metal coupling and is electrically connected
It is routed through the non-conductive flexible layer；
It is formed in the plastic packaging layer of non-conductive flexible layer upper surface and the encapsulation chip.
14. fan-out-type wafer level packaging structure according to claim 13, it is characterised in that: the structure further includes being formed
Soldered ball in the lower surface of the re-wiring layer.
15. fan-out-type wafer level packaging structure according to claim 13, it is characterised in that: the re-wiring layer includes
Dielectric layer and at least one layer of metal wiring layer being formed in the dielectric layer, wherein the metal coupling and the hardware cloth
Line layer is electrically connected.
16. fan-out-type wafer level packaging structure according to claim 13, it is characterised in that: the non-conductive flexible layer packet
Include one of polymer or glue.
17. fan-out-type wafer level packaging structure according to claim 13, it is characterised in that: the chip includes semiconductor
At least one of chip and electronic component；Wherein, the semiconductor chip includes:
Surface has the wafer of metal pad；
It is formed in the crystal column surface and exposes the passivation layer of the metal pad, wherein the pad and the metal are convex
Block bonding is electrically connected.
18. fan-out-type wafer level packaging structure according to claim 13, it is characterised in that: the plastic packaging layer includes polyamides
One of imines, silica gel and epoxy resin.
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