CN109961811B - Reading circuit of spin transfer torque MRAM - Google Patents
Reading circuit of spin transfer torque MRAM Download PDFInfo
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- CN109961811B CN109961811B CN201711405188.8A CN201711405188A CN109961811B CN 109961811 B CN109961811 B CN 109961811B CN 201711405188 A CN201711405188 A CN 201711405188A CN 109961811 B CN109961811 B CN 109961811B
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- G11—INFORMATION STORAGE
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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Abstract
The invention discloses a reading circuit of a spin transfer torque MRAM, which adopts a first reading branch circuit and a second reading branch circuit to read MTJ information by adopting the first reading branch circuit and store the read information in a data capacitor, then writes the MTJ into a preset state, and then adopts the second reading branch circuit to read the MTJ information and store the read information in a reference capacitor. And finally, comparing the voltage values of the data capacitor and the reference capacitor through a comparator, judging the real state information of the MTJ, and ensuring that the MTJ information is set to be in an initial state. The reading circuit can accurately read the real information of the MTJ bit.
Description
Technical Field
The invention belongs to the technical field of Magnetic Random Access Memories (MRAM), and particularly relates to a reading circuit of a spin transfer torque (MRAM).
Background
Spin transfer torque magnetic random access memory ST-mram (spin transfer torque mram) is a new type of memory with great potential. However, to replace or partially replace the existing mainstream memory, a large-capacity MRAM of Megabyte (MB) to Gigabyte (GB) level must be implemented. This means that the difference in characteristics between a large number of memory bits in an MRAM, i.e., Magnetic Tunnel Junctions (MTJs), must be very small.
The MTJ basic unit is composed of a magnetic pinned layer, an insulating layer, and a magnetic free layer, and the magnetization direction of the free layer can be changed by a magnetic field or a spin-polarized current. The parallel and antiparallel magnetization directions of the free and fixed layers correspond to low and high resistance states, respectively, and can be used to record information 0 or 1.
However, the MTJ of the actual product includes several tens of metal layers with a thickness of about 1 nm and 1 to 2 insulating layers, and the variation of the thickness of each layer by 0.1 nm may significantly affect the properties of the MTJ. Therefore, high capacity MRAM has very stringent process stability and uniformity requirements.
Reading of information in a single MTJ depends on the parallel state resistance (R)p) And an antiparallel state resistance (R)ap) Difference between or TMR ═ Rap-Rp)/Rp. And an MRAM consisting of an MTJ array, and further needsWith a sufficiently small RpAnd RapStatistical distribution standard deviation of (a) (R)pAnd RapThe profiles do not overlap). Namely satisfy Rap-Rp>N*(σ(Rp)+σ(Rap) Where N is determined by the capacity and soft error correction current, typically large capacity MRAM requires N>5, so that by choosing a suitable reference resistance RrefThe information stored in the bit can be accurately determined. However, under the current industry process conditions, the σ of the MTJ is difficult to reduce below 5%; because MTJ is very sensitive to defects, the resistance distribution curve is not necessarily normally distributed, taking into account the factors such as TMR reduction to about 120 at high temperature, MOS transistor fluctuation, and read circuit sensitivity, for example, where σ is 10%, R p、RapThere is an overlap in the 1Gbit array. Due to Rp、RapThe distributions have overlap, and a reference resistance R is usedrefThe determination of the MTJ state inevitably has a high error rate.
Disclosure of Invention
The invention aims to provide a reading circuit of a spin transfer torque MRAM (magnetic random access memory), which is used for solving the problem of high error rate when the state of the MTJ is judged in the prior art.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a reading circuit of a spin transfer torque MRAM (magnetic random access memory) is used for reading information of an MTJ bit cell, the MTJ bit cell comprises an MTJ and a bit selection tube N5, the upper plate of the MTJ is connected with a bit line BL, the drain of the bit selection tube N5 is connected with the lower plate of the MTJ, the gate is connected with a word line WL, and the source is connected with a source line SL, the reading circuit of the spin transfer torque MRAM comprises: a write driver, a comparator, and a first read branch and a second read branch connected to the MTJ bit cell through a first column select transistor N4, a gate terminal of the first column select transistor N4 being connected to a column select line CSL, wherein:
the first reading branch comprises a data capacitor C1, and a first PRE-charge transistor P0, a first reading voltage selection switch tube N0 and a first reading voltage clamp tube N2 which are connected in sequence, wherein the source end of the first PRE-charge transistor P0 is connected with a power supply voltage VDD, the gate end of the first PRE-charge transistor P0 is connected with a PRE-charge inversion signal PRE _ N, the drain end of the first PRE-charge transistor P0 is connected with a data capacitor C1, the gate end of the first reading voltage selection switch tube N0 is connected with a first reading selection signal RD1, the gate end of the first reading voltage clamp tube N2 is connected with a first reading voltage VR1, and the source end of the first reading voltage clamp tube N2 is connected with the drain end of a first column selection tube N4;
The second reading branch comprises a reference capacitor C2, a second PRE-charge transistor P1, a second reading voltage selection switch N1 and a second reading voltage clamp N3 which are connected in sequence, the source end of the second PRE-charge transistor P1 is connected with a power supply voltage VDD, the gate end of the second PRE-charge transistor P1 is connected with a PRE-charge inverted signal PRE _ N, the drain end of the second PRE-charge transistor P3632 is connected with the reference capacitor C2, the gate end of the second reading voltage selection switch N1 is connected with a second reading selection signal RD2, the gate end of the second reading voltage clamp N3 is connected with a second reading voltage VR2, and the source end of the second reading voltage clamp N3 is connected with the drain end of the first column selection transistor N4;
the input end of the write driver is respectively connected with a write enable WE and a comparator output OUT, and the two outputs are respectively connected with a bit line BL and a source line SL;
the two input terminals of the comparator are respectively connected with the data capacitor C1 and the reference capacitor C2, and the output OUT of the comparator is connected with one input terminal of the write driver.
Further, a precharge inverse signal PRE _ N of the read circuit of the spin transfer torque MRAM activates the first precharge transistor P0 and the second precharge transistor P1, precharges the data capacitor C1 and the reference capacitor C2 to the power supply voltage VDD, and then floats the data capacitor C1 and the reference capacitor C2; then starting a column selection line and a word line, and accessing the selected MTJ into a reading circuit; then starting a first read selection signal RD1 to perform a first read; after the first reading, starting a write enable WE signal, and writing the MTJ into a low resistance state or a high resistance state by a write driver; the second read select signal RD2 is then enabled for the second read.
In one implementation of the present invention, the data capacitor C1 is the same as the reference capacitor C2, the pulse time T1 of the first read select signal RD1 is the same as the pulse time T2 of the second read select signal RD2, the write driver writes the MTJ to a low resistance state, and the second read voltage VR2 is equal to the difference between the first read voltage VR1 and the preset additional voltage value VOFFSET.
In yet another embodiment of the present invention, the data capacitor C1 is the same as the reference capacitor C2, the first read select signal RD1 has the same pulse time T1 as the second read select signal RD2 has the same pulse time T2, the write driver writes the MTJ to a high resistive state, and the second read voltage VR2 is equal to the sum of the first read voltage VR1 and the preset additional voltage value VOFFSET.
In yet another embodiment of the present invention, the data capacitor C1 is the same as the reference capacitor C2, the first read voltage VR1 is the same as the second read voltage VR2, the MTJ is written to the low-resistance state by the write driver, and the pulse time T2 of the second read select signal RD2 is equal to the difference between the pulse time T1 of the first read select signal RD1 and the predetermined additional time value TOFFSET.
In yet another embodiment of the present invention, the data capacitor C1 is the same as the reference capacitor C2, the first read voltage VR1 is the same as the second read voltage VR2, the MTJ is written to a high resistance state by the write driver, and the pulse time T2 of the second read select signal RD2 is equal to the sum of the pulse time T1 of the first read select signal RD1 and the predetermined additional time value TOFFSET.
In yet another implementation manner of the present invention, the first reading voltage VR1 is the same as the second reading voltage VR2, the pulse time T1 of the first reading selection signal RD1 is the same as the pulse time T2 of the second reading selection signal RD2, the MTJ is written by the write driver in a low resistance state, and the reference capacitor C2 is the sum of the reference capacitor C1 and a preset additional capacitance COFFSET.
In yet another implementation manner of the present invention, the first reading voltage VR1 is the same as the second reading voltage VR2, the pulse time T1 of the first reading selection signal RD1 is the same as the pulse time T2 of the second reading selection signal RD2, the MTJ is written by the write driver in a high impedance state, and the reference capacitor C2 is a difference between the reference capacitor C1 and a preset additional capacitance value COFFSET.
In another implementation manner of the present invention, a first offset resistor ROFFSET1 is added between the source terminal of the second read voltage clamp N3 and the drain terminal of the first column select transistor N4, the data capacitor C1 is the same as the reference capacitor C2, the first read voltage VR1 is the same as the second read voltage VR2, the pulse time T1 of the first read select signal RD1 is the same as the pulse time T2 of the second read select signal RD2, the write driver writes the MTJ into a low-resistance state, and the value of the first offset resistor ROFFSET1 is smaller than the difference between the high resistance and the low resistance of the MTJ. In another implementation manner of the present invention, a second offset resistor ROFFSET2 and a second offset resistor gate tube N7 are added between the source end of the second read voltage clamp tube N3 and the ground line, the gate end of the second offset resistor gate tube N7 is connected to a second read selection signal RD2, the data capacitor C1 is the same as the reference capacitor C2, the first read voltage VR1 is the same as the second read voltage VR2, the pulse time T1 of the first read selection signal RD1 is the same as the pulse time T2 of the second read selection signal RD2, the write driver writes the MTJ into a high resistance state, and the value of the second offset resistor ROFFSET2 is greater than twice the high resistance value of the MTJ.
The reading circuit of the spin transfer torque MRAM provided by the invention adopts the first reading branch circuit to read the MTJ information by arranging the first reading branch circuit and the second reading branch circuit, stores the read information in the data capacitor, then writes the MTJ into a preset state, and adopts the second reading branch circuit to read the MTJ information and stores the read information in the reference capacitor. And finally, comparing the voltage values of the data capacitor and the reference capacitor through a comparator, judging the real state information of the MTJ, and ensuring that the MTJ information is set to be in an initial state. The reading circuit can accurately read the real information of the MTJ bit.
Drawings
FIG. 1 is a circuit diagram of a read circuit of a spin transfer torque MRAM of the present invention;
FIG. 2 is a diagram of various signal pulses in the read circuit of the present invention;
FIG. 3 is a circuit diagram of one embodiment of a read circuit for a spin transfer torque MRAM in accordance with the present invention;
FIG. 4 is a circuit diagram of another embodiment of a read circuit of a spin transfer torque MRAM in accordance with the present invention.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the drawings and examples, which should not be construed as limiting the present invention.
As shown in fig. 1, the read circuit of the spin transfer torque MRAM of the present embodiment is used for reading information of MTJ bits, where the MTJ bits include an MTJ and a bit selection tube N5, an upper plate of the MTJ is connected to a bit line BL, a drain of the bit selection tube N5 is connected to a lower plate of the MTJ, a gate is connected to a word line WL, and a source is connected to a source line SL. The spin transfer torque MRAM of the present embodiment includes: a write driver, a comparator, and a first read branch and a second read branch connected to the MTJ bit cell through a first column select transistor N4, a gate terminal of the first column select transistor N4 being connected to a column select line CSL, wherein:
The first reading branch comprises a data capacitor C1, and a first PRE-charge transistor P0, a first reading voltage selection switch tube N0 and a first reading voltage clamp tube N2 which are connected in sequence, wherein the source end of the first PRE-charge transistor P0 is connected with a power supply voltage VDD, the gate end of the first PRE-charge transistor P0 is connected with a PRE-charge inversion signal PRE _ N, the drain end of the first PRE-charge transistor P0 is connected with a data capacitor C1, the gate end of the first reading voltage selection switch tube N0 is connected with a first reading selection signal RD1, the gate end of the first reading voltage clamp tube N2 is connected with a first reading voltage VR1, and the source end of the first reading voltage clamp tube N2 is connected with the drain end of a first column selection tube N4;
the second reading branch comprises a reference capacitor C2, a second PRE-charge transistor P1, a second reading voltage selection switch N1 and a second reading voltage clamp N3 which are connected in sequence, the source end of the second PRE-charge transistor P1 is connected with a power supply voltage VDD, the gate end of the second PRE-charge transistor P1 is connected with a PRE-charge inverted signal PRE _ N, the drain end of the second PRE-charge transistor P3632 is connected with the reference capacitor C2, the gate end of the second reading voltage selection switch N1 is connected with a second reading selection signal RD2, the gate end of the second reading voltage clamp N3 is connected with a second reading voltage VR2, and the source end of the second reading voltage clamp N3 is connected with the drain end of the first column selection transistor N4;
the input end of the write driver is respectively connected with a write enable WE and a comparator output OUT, and the two outputs are respectively connected with a bit line BL and a source line SL;
Two input ends of the comparator are respectively connected with the data capacitor C1 and the reference capacitor C2.
Specifically, in this embodiment, the source terminals of P0 and P1 are connected to the power supply voltage VDD, the gate terminal is connected to the PRE-charge bar signal PRE _ N, the drain terminals are respectively connected to two inputs of the comparator, and the drain terminals are respectively connected to the drain terminals of N0 and N1. One end of the data capacitor C1 is grounded, and the other end is connected to one input end of the comparator (or the drain end of P0); the reference capacitor C2 has one end connected to ground and the other end connected to the other input terminal of the comparator (or the drain terminal of P1).
In this embodiment, the gate terminals of N0 and N1 are respectively connected to the first read select signal RD1 and the second read select signal RD2, and the source terminals are respectively connected to the drain terminals of the clamp transistors N2 and N3. The gate terminals of N2 and N3 are respectively connected with the first reading voltage VR1 and the second reading voltage VR2, and the source terminals are connected with the drain terminal of N4. The gate terminal of N4 is connected to column select line CSL, and the source terminal of N4 is connected to bit line BL.
In addition, the source end of the N5 in this embodiment is further connected to a second column selection tube N6, the gate end of N6 is connected to the column selection line CSL, and the drain end and the source end of N6 are respectively connected to the source line SL and the ground line.
When the reading circuit of this embodiment operates, waveforms of the driving signals are as shown in fig. 2, and the operating process is as follows:
first, precharge bar signal PRE _ N is at low level, precharge transistors P0 and P1 operate to charge C1 and C2, and charge the voltage across C1 and C2 to VDD. Subsequently, the precharge bar signal PRE _ N is at a high level, the precharge transistors P0, P1 are turned off, and the C1, C2 are floated.
Then the column selection signal CSL, word line WL is at high level, N4, N5, N6 are turned on, and the selected MTJ is switched into the reading circuit.
Then the first read select signal RD1 is at high level, N0 is turned on, and the pulse width of the read select signal RD1 is T1; the first reading voltage VR1 at the gate of N2 may be always high, or the waveform may be consistent with RD1, and N2 is also turned on. The MTJ is read beginning, this time the first read. The current IRD1 generated on the MTJ for the first read discharges C1, causing the voltage on C1 to drop from VDD to Vread, and:
vread is held on capacitor C1 and the first read is complete. The first read select signal RD1 goes low and the MTJ is disengaged from the read circuit.
Then, the write enable WE is at high level, and the write driver writes a preset state into the MTJ, at which time the MTJ can be written into a low resistance (P) state or into a high resistance (AP) state. After writing, the write enable WE is again at low level, and the write driver stops operating.
Then the second read select signal RD2 is at high level, N1 is turned on, and the pulse width of the read select signal RD2 is T2; the second reading voltage VR2 of the gate of N3 may be always at a high level, and may have a waveform consistent with RD2, and N3 is also turned on. The MTJ is read beginning, this time a second read. The current IRD2 generated on the MTJ for the second read discharges C2, so that the voltage on C2 drops from VDD to Vref, and:
Vref is stored on capacitor C2 and the second read is complete. The second read select signal RD2 goes low and the MTJ is disengaged from the read circuit.
It will be readily appreciated that the specific values of Vread and Vref are related to the currents, read times, capacitances on the first and second read branches, and the currents are related to the voltages and resistances on the read branches, according to the above equations, and therefore significant differences between Vread and Vref can be achieved by varying the first and second read voltages VR1 and VR2, or by varying the pulse time T1 of the first read select signal RD1, the pulse time T2 of the second read select signal RD2, or by varying C1 and C2. So that the real state of the MTJ read for the first time can be judged by the comparator.
The comparative process is illustrated below by means of several examples:
example 1, before the second read, the MTJ was written in the P state, VR 2-VR 1-VOFFSET, T1-T2, and C1-C2.
In this case, Vread and Vref are inputted to the comparator for comparison, and if Vread > Vref, the MTJ is in a high resistance state (AP), and if Vread < Vref, the MTJ is in a low resistance state (P).
Example 2, before the second read, the MTJ is written in the AP state, VR 2-VR 1+ VOFFSET, T1-T2, and C1-C2.
In this case, Vread and Vref are inputted to the comparator for comparison, and if Vread > Vref, the MTJ is in a high resistance state (AP), and if Vread < Vref, the MTJ is in a low resistance state (P).
Through the two embodiments, it can be seen that by changing the second read voltage (adding or subtracting a VOFFSET voltage from the first read voltage), the original state of the MTJ can be determined to be a low resistance state or a high resistance state through comparison, thereby implementing reading of information of the MTJ.
In example 3, VR1 is VR2, and C1 is C2, but the pulse time T1 of the first read select signal RD1 is different from the pulse time T2 of the second read select signal RD 2.
At this time, if the MTJ is written to the P-state before the second read, the pulse time of T2 is reduced, i.e., T2 — T1-TOFFSET; if the MTJ is written to the AP state before the second read, the pulse time of T2 is increased, T2 ═ T1+ TOFFSET.
Example 4, VR1 is VR2 and T1 is T2, but the data capacitance C1 and the reference capacitance C2 are different.
At this time, if the MTJ is written to the P state before the second read, the capacitance of C2 is increased, i.e., C2> C1 in the circuit, C2 ═ C1+ COFFSET; if the MTJ is written to the AP state before the second read, the capacity of C2 is reduced, i.e., C2< C1, C2-C1-COFFSET in the circuit.
In the above embodiment, the VOFFSET voltage is a predetermined additional voltage, and similarly, for the difference TOFFSET between T2Y and T1, the difference COFFSET between C2 and C1 can be obtained through experiments or calculation, and all values are positive and straight. So that Vread and Vref have a significant difference, the real state of the MTJ read for the first time can be judged by the comparator.
Similarly, an additional resistor may be disposed in the read branch to change Vread and Vref, and the same technical effect may be achieved.
In embodiment 5, VR1 is VR2, C1 is C2, and T1 is T2, a first offset resistance ROFFSET1 is added between the source terminal of the second read voltage clamp N3 and the drain terminal of the first column select transistor N4, as shown in fig. 3, when reading for the second time, the write driver writes the MTJ into a low resistance state, and the value of the first offset resistance ROFFSET1 is smaller than the difference between the high resistance and the low resistance of the MTJ, at this time, the Vread and the Vref may have a significant difference, so that the real state of the MTJ read for the first time may be determined by the comparator.
Or, a second offset resistor ROFFSET2 and a second offset resistor gate tube N7 are added between the source end of the second read voltage clamp tube N3 and the ground, as shown in fig. 4, the gate of the second offset resistor gate tube N7 is connected to RD2, the MTJ is written to a high resistance state by the write driver, and the value of ROFFSET2 is greater than twice the high resistance value of the MTJ. Significant differences between Vread and Vref can also be achieved. So that the real state of the MTJ read for the first time can be judged by the comparator.
It should be noted that, before the second read, the MTJ is written in the high resistance state or the low resistance state, and after the actual state of the MTJ is obtained through the judgment, the output (actual state) of the comparator needs to be connected to the input of the write driver, so as to compare the actual state with the state written before the second read and write, if the actual state is the same as the state written before the second read and write, the operation is not performed, the read process is ended, and if the actual state of the MTJ is not the same as the state written before the second read and write, the read process is ended by writing the actual state of the MTJ.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, but these corresponding changes and modifications should fall within the protection scope of the appended claims.
Claims (9)
1. A reading circuit of a spin transfer torque MRAM (magnetic random access memory) is used for reading information of an MTJ bit, the MTJ bit comprises an MTJ and a bit selection tube (N5), an upper plate of the MTJ is connected with a bit line BL, a drain end of the bit selection tube (N5) is connected with a lower plate of the MTJ, a gate end is connected with a word line WL, and a source end is connected with a source line SL, and the reading circuit of the spin transfer torque MRAM comprises: a write driver, a comparator, and a first read branch and a second read branch connected to the MTJ bit cell through a first column select transistor (N4), a gate terminal of the first column select transistor (N4) being coupled to a column select line CSL, wherein:
The first reading branch comprises a data capacitor (C1), and a first PRE-charge transistor (P0), a first reading voltage selection switch tube (N0) and a first reading voltage clamp tube (N2) which are connected in sequence, wherein the source end of the first PRE-charge transistor (P0) is connected with a power supply voltage VDD, the gate end of the first PRE-charge transistor is connected with a PRE-charge inverse signal PRE _ N, the drain end of the first PRE-charge transistor is connected with the data capacitor (C1), the gate end of the first reading voltage selection switch tube (N0) is connected with a first reading selection signal RD1, the gate end of the first reading voltage clamp tube (N2) is connected with a first reading voltage VR1, and the source end of the first reading voltage clamp tube (N2) is connected with the drain end of a first column selection tube (N4);
the second reading branch comprises a reference capacitor (C2), a second PRE-charge transistor (P1), a second reading voltage selection switch tube (N1) and a second reading voltage clamp tube (N3) which are connected in sequence, wherein the source end of the second PRE-charge transistor (P1) is connected with a power supply voltage VDD, the gate end of the second PRE-charge transistor is connected with a PRE-charge inverse signal PRE _ N, the drain end of the second PRE-charge transistor is connected with the reference capacitor (C2), the gate end of the second reading voltage selection switch tube (N1) is connected with a second reading selection signal RD2, the gate end of the second reading voltage clamp tube (N3) is connected with a second reading voltage VR2, and the source end of the second reading voltage clamp tube (N3) is connected with the drain end of the first column selection tube (N4;
The input end of the write driver is respectively connected with a write enable WE and a comparator output OUT, and the two outputs are respectively connected with a bit line BL and a source line SL;
the two input ends of the comparator are respectively connected with a data capacitor (C1) and a reference capacitor (C2), and the output OUT of the comparator is connected to one input end of the write driver;
a precharge inverse signal PRE _ N of the read circuit of the spin transfer torque MRAM firstly starts a first precharge transistor (P0) and a second precharge transistor (P1), precharges a data capacitor (C1) and a reference capacitor (C2) to a power supply voltage VDD, and then floats the data capacitor (C1) and the reference capacitor (C2); then starting a column selection line and a word line, and accessing the selected MTJ into a reading circuit; then starting a first read selection signal RD1 to perform a first read; after the first reading, starting a write enable WE signal, and writing the MTJ into a low resistance state or a high resistance state by a write driver; then starting a second read select signal RD2 for a second read;
by changing the first reading voltage VR1 and the second reading voltage VR2, or changing the pulse time T1 of the first reading selection signal RD1 and the pulse time T2 of the second reading selection signal RD2, or changing the data capacitor (C1) and the reference capacitor (C2), the voltage on the data capacitor (C1) and the reference capacitor (C2) is compared by the comparator to judge the real state of the MTJ of the first reading.
2. The read circuit of a spin transfer torque MRAM of claim 1 wherein the data capacitor (C1) is the same as the reference capacitor (C2), the first read select signal RD1 has a pulse time T1 that is the same as the second read select signal RD2 has a pulse time T2, the write driver writes the MTJ to a low resistance state, and the second read voltage VR2 is equal to the difference between the first read voltage VR1 and the preset additional voltage value VOFFSET.
3. The read circuit of a spin transfer torque MRAM of claim 1 wherein the data capacitor (C1) is the same as the reference capacitor (C2), the first read select signal RD1 has a pulse time T1 that is the same as the second read select signal RD2 has a pulse time T2, the write driver writes the MTJ to a high resistance state, and the second read voltage VR2 is equal to the sum of the first read voltage VR1 and a preset additional voltage value VOFFSET.
4. The read circuit of the spin-transfer torque MRAM of claim 1 wherein the data capacitor (C1) is the same as the reference capacitor (C2), the first read voltage VR1 is the same as the second read voltage VR2, the write driver writes the MTJ to a low resistance state, and the pulse time T2 of the second read select signal RD2 is equal to the difference between the pulse time T1 of the first read select signal RD1 and the preset additional time value TOFFSET.
5. The read circuit of the spin-transfer torque MRAM of claim 1 wherein the data capacitance (C1) is the same as the reference capacitance (C2), the first read voltage VR1 is the same as the second read voltage VR2, the write driver writes the MTJ in a high resistance state, and the pulse time T2 of the second read select signal RD2 is equal to the sum of the pulse time T1 of the first read select signal RD1 and the preset additional time value TOFFSET.
6. The read circuit of a spin transfer torque MRAM of claim 1 wherein the first read voltage VR1 is the same as the second read voltage VR2, the first read select signal RD1 has a pulse time T1 is the same as the second read select signal RD2 has a pulse time T2, the write driver writes the MTJ to a low resistance state, and the reference capacitance (C2) is the sum of a reference capacitance (C1) and a predetermined additional capacitance value COFFSET.
7. The read circuit of the spin-transfer torque MRAM of claim 1 wherein the first read voltage VR1 is the same as the second read voltage VR2, the first read select signal RD1 has a pulse time T1 is the same as the second read select signal RD2 has a pulse time T2, the write driver writes the MTJ to a high resistance state, and the reference capacitance (C2) is the difference between the reference capacitance (C1) and a predetermined additional capacitance value COFFSET.
8. The read circuit of the spin transfer torque MRAM of claim 1, wherein a first offset resistor (ROFFSET1) is added between the source terminal of the second read voltage clamp (N3) and the drain terminal of the first column select transistor (N4), the data capacitor (C1) is the same as the reference capacitor (C2), the first read voltage VR1 is the same as the second read voltage VR2, the pulse time T1 of the first read select signal RD1 is the same as the pulse time T2 of the second read select signal RD2, the write driver writes the MTJ to a low impedance state, and the value of the first offset resistor (ROFFSET1) is smaller than the difference between the MTJ and the low impedance.
9. The reading circuit of the spin transfer torque MRAM of claim 1, wherein a second offset resistor (ROFFSET2) and a second offset resistor gate transistor (N7) are added between the source terminal and the ground of the second reading voltage clamp (N3), the gate of the second offset resistor gate transistor (N7) is connected to a second reading selection signal RD2, the data capacitor (C1) is the same as a reference capacitor (C2), the first reading voltage VR1 is the same as the second reading voltage VR2, the pulse time T1 of the first reading selection signal RD1 is the same as the pulse time T2 of the second reading selection signal RD2, the writing driver writes the MTJ to a high resistance state, and the value of the second offset resistor (ROFFSET2) is greater than twice the high resistance value of the MTJ.
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| CN201711405188.8A CN109961811B (en) | 2017-12-22 | 2017-12-22 | Reading circuit of spin transfer torque MRAM |
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