CN109950158B - 高导热dfn封装器件的制备方法 - Google Patents

高导热dfn封装器件的制备方法 Download PDF

Info

Publication number
CN109950158B
CN109950158B CN201910131685.6A CN201910131685A CN109950158B CN 109950158 B CN109950158 B CN 109950158B CN 201910131685 A CN201910131685 A CN 201910131685A CN 109950158 B CN109950158 B CN 109950158B
Authority
CN
China
Prior art keywords
parts
packaging device
chip
conductivity
dfn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910131685.6A
Other languages
English (en)
Other versions
CN109950158A (zh
Inventor
马磊
党鹏
杨光
彭小虎
王新刚
庞朋涛
任斌
王妙妙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xi'an Hangsi Semiconductor Co ltd
Original Assignee
Xi'an Hangsi Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xi'an Hangsi Semiconductor Co ltd filed Critical Xi'an Hangsi Semiconductor Co ltd
Priority to CN202011403562.2A priority Critical patent/CN112420532B/zh
Priority to CN202011426172.7A priority patent/CN112701054B/zh
Priority to CN201910131685.6A priority patent/CN109950158B/zh
Publication of CN109950158A publication Critical patent/CN109950158A/zh
Application granted granted Critical
Publication of CN109950158B publication Critical patent/CN109950158B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明公开了一种高导热DFN封装器件的制备方法，包括以下步骤：S1.先将硅微粉和阻燃剂与3‑氨基丙基三乙氧基硅烷混合均匀，进行表面处理；S2.再加入环氧树脂、线型酚醛树脂、液体丁腈橡胶、焦碳酸二乙酯、聚乙二醇单辛基苯基醚、醋酸丁酸纤维素、5‑氟‑2‑甲氧基苯胺、2,4,6‑三(二甲氨基甲基)苯酚和脱模剂，混合均匀；S3.将混合物于90~110℃混炼3~5分钟，产物冷却后粉碎过筛；该方法制备得到的高导热DFN封装器件内部气孔的发生率低，有效避免了气孔导致的导热性能降低进而引起电性方面的失效的问题。

Description

高导热DFN封装器件的制备方法
技术领域
本发明属于无引脚封装技术领域，尤其涉及一种高导热DFN封装器件的制备方法。
背景技术
DFN是一种无引脚封装，呈正方形或矩形，封装底部中央位置有一个大面积裸露焊盘用来导热，围绕大焊盘的封装***四周有实现电气连结的导电焊盘。由于DFN封装不像传统的SOIC与TSOP封装那样具有鸥翼状引线，内部引脚与焊盘之间的导电路径短，自感系数以及封装体内布线电阻很低，所以它能提供卓越的电性能，而得到广泛应用。
由于在封装过程中环氧树脂组成物流动性差或固化不均一，易导致内部的气体未被完全赶走而产生气孔，进而导致封装器件吸湿导致可靠性失效，且内部气孔的产生还可能会导致导热性能降低从而引起电性方面的失效或热量损耗。因此，如何提供一种导热性能好，内部气孔的发生率低的DFN封装器件，成为本领域技术人员努力的方向。
发明内容
本发明目的在于提供一种高导热DFN封装器件的制备方法，该方法制备得到的高导热DFN封装器件内部气孔的发生率低，有效避免了气孔导致的导热性能降低进而引起电性方面的失效的问题。
为达到上述目的，本发明采用的技术方案是：一种高导热DFN封装器件的制备方法，所述高导热DFN封装器件包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘，所述芯片位于散热焊盘上，位于散热焊盘周边设有若干个导电焊盘，所述导电焊盘和芯片通过一引线连接；
所述散热焊盘的中央区开有一供芯片嵌入的沉槽，从而在散热焊盘的边缘区形成一围堰部，所述沉槽的底部和围堰部与芯片的下表面和侧壁之间均设置有银浆层，所述沉槽的底部开有若干个延伸至散热焊盘内的换热盲孔，所述换热盲孔中具有银浆填充部；
所述环氧绝缘体的原料的制备方法包括以下步骤：
S1. 先将硅微粉65~90份和阻燃剂10~25份与3-氨基丙基三乙氧基硅烷2~5份混合均匀，进行表面处理；
S2. 再加入环氧树脂80~100份、线型酚醛树脂50~70份、液体丁腈橡胶12~18份、焦碳酸二乙酯3~8份、聚乙二醇单辛基苯基醚0.1~1.5份、醋酸丁酸纤维素2~6份、5-氟-2-甲氧基苯胺0.3~2份、2,4,6-三(二甲氨基甲基)苯酚0.5~5份和脱模剂1~5份，混合均匀；
S3. 将混合物于90~110℃混炼3~5分钟，产物冷却后粉碎过筛，以上份数均为重量份。
上述技术方案中进一步改进的技术方案如下：
1. 上述方案中，所述沉槽深度不大于芯片厚度设置。
2. 上述方案中，所述换热盲孔为锥形盲孔，所述换热盲孔靠近芯片一端端口的孔径大于换热盲孔远离芯片一端端口的孔径。
3. 上述方案中，所述换热盲孔延伸至散热焊盘中下部。
4. 上述方案中，所述围堰部内侧上开有阶梯部。
5. 上述方案中，所述脱模剂选自硬脂酸、硬脂酸盐或者氧化聚乙烯蜡中的至少一种。
6. 上述方案中，所述阻燃剂为硼酸盐和/或钼酸盐。
7. 上述方案中，步骤S3中，混炼温度为100℃。
由于上述技术方案的运用，本发明与现有技术相比具有下列优点：
1、本发明高导热DFN封装器件的制备方法，其在散热焊盘的中部开设与芯片匹配的沉槽，从而使得在贴装芯片时，工作人员将银浆置于沉槽中，并将对应的芯片安装进沉槽即可；此时，芯片下部嵌于沉槽中，不仅其底部能够通过形成的银浆层与沉槽底部粘结，芯片下部的侧壁也能与沉槽外部的围堰部的内壁通过银浆层相互粘结，不仅芯片与银浆层的接触面积有所增加，而且银浆层与散热焊盘的接触面积也有所增加，从而使得单位时间内，更多的热量在芯片与银浆层之间、银浆层与散热焊盘之间传导，进而改善DFN封装半导体器件的散热效果。
2、本发明高导热DFN封装器件的制备方法，在散热焊盘的中央区设置有沉槽，能方便工作人员校准芯片的安装位置，实现芯片的精确安装，提高芯片封装质量；同时，将芯片嵌装于沉槽中，能够定位芯片位置，配合银浆的设置保护芯片和与芯片连接的引线，提高封装质量；此外，沉槽底部开设换热盲孔，换热盲孔的设置能够容纳部分银浆，避免多余的银浆溢出沉槽，待换热盲孔中具有银浆填充部后，银浆与散热焊盘的接触面积进一步增加，封装散热效果得到进一步的提升。
3. 本发明高导热DFN封装器件的制备方法，其环氧绝缘体配方在环氧树脂体系中加入了液体丁腈橡胶12~18份，采用2,4,6-三(二甲氨基甲基)苯酚0.5~5份作为固化促进剂，并额外添加了焦碳酸二乙酯3~8份和5-氟-2-甲氧基苯胺0.3~2份，提高了固化物的交联密度，从而增强了环氧绝缘体的整体力学性能，有效保证了制得DFN封装器件结构稳定性。
4. 本发明高导热DFN封装器件的制备方法，其环氧绝缘体配方采用环氧树脂80~100份和线型酚醛树脂50~70份，并添加聚乙二醇单辛基苯基醚0.1~1.5份和醋酸丁酸纤维素2~6份，降低了树脂体系与无机填料间的相互作用力，显著改善了组合物的流动性，能够有效降低封装后内部气孔的发生率，避免了气孔导致的导热性能降低进而引起电性方面的失效的问题，提高了封装成品率。
附图说明
附图1为本发明高导热DFN封装器件结构示意图。
以上附图中：1、散热焊盘；11、沉槽；12、围堰部；121、阶梯部；13、换热盲孔；2、银浆层；21、银浆填充部；3、芯片；4、导电焊盘；5、引线；6、环氧绝缘体。
具体实施方式
下面结合实施例对本发明作进一步描述：
实施例1~4：一种高导热DFN封装器件的制备方法，所述高导热DFN封装器件包括位于环氧绝缘体6中的散热焊盘1、芯片3和导电焊盘4，所述芯片3位于散热焊盘1上，位于散热焊盘1周边设有若干个导电焊盘4，所述导电焊盘4和芯片3通过一引线5连接；
所述散热焊盘1的中央区开有一供芯片3嵌入的沉槽11，从而在散热焊盘1的边缘区形成一围堰部12，所述沉槽11的底部和围堰部12与芯片3的下表面和侧壁之间均设置有银浆层2，所述沉槽11的底部开有若干个延伸至散热焊盘1内的换热盲孔13，所述换热盲孔13中具有银浆填充部21；
上述沉槽11深度不大于芯片3厚度设置；
上述换热盲孔13为锥形盲孔，上述换热盲孔13靠近芯片3一端端口的孔径大于换热盲孔13远离芯片3一端端口的孔径；
上述换热盲孔13延伸至散热焊盘1中下部；
上述围堰部12内侧上开有阶梯部121；
上述环氧绝缘体6的原料的制备方法包括以下步骤：
S1. 先将硅微粉65~90份和阻燃剂10~25份与3-氨基丙基三乙氧基硅烷2~5份混合均匀，进行表面处理；
S2. 再加入环氧树脂80~100份、线型酚醛树脂50~70份、液体丁腈橡胶12~18份、焦碳酸二乙酯3~8份、聚乙二醇单辛基苯基醚0.1~1.5份、醋酸丁酸纤维素2~6份、5-氟-2-甲氧基苯胺0.3~2份、2,4,6-三(二甲氨基甲基)苯酚0.5~5份和脱模剂1~5份，混合均匀；
S3. 将混合物于90~110℃混炼3~5分钟，产物冷却后粉碎过筛，以上份数均为重量份。
各实施例环氧绝缘体6的原料具体组分如表1所示：
表1
Figure DEST_PATH_IMAGE002A
实施例1中的脱模剂为硬脂酸，阻燃剂为硼酸盐；实施例2中的脱模剂为硬脂酸盐，阻燃剂为硼酸盐；实施例3中的脱模剂为氧化聚乙烯蜡，阻燃剂为钼酸盐；实施例4中的脱模剂为硬脂酸和氧化聚乙烯蜡的混合物，阻燃剂为钼酸盐。
对比例1~3：一种环氧绝缘体，原料包括以下重量份组分：
表2
组分 对比例1 对比例2 对比例3
环氧树脂 80 90 100
线型酚醛树脂 50 30 70
液体丁腈橡胶 5 18 12
焦碳酸二乙酯 8 - 5
硅微粉 65 90 75
聚乙二醇单辛基苯基醚 0.1 1.5 -
3-氨基丙基三乙氧基硅烷 2 5 4
醋酸丁酸纤维素 - 3 6
5-氟-2-甲氧基苯胺 2 0.3 -
2,4,6-三(二甲氨基甲基)苯酚 0.5 2 5
脱模剂 2 1 5
阻燃剂 10 25 15
对比例1中的脱模剂为硬脂酸，阻燃剂为硼酸盐；对比例2中的脱模剂为硬脂酸盐，阻燃剂为硼酸盐；对比例3中的脱模剂为氧化聚乙烯蜡，阻燃剂为钼酸盐。
制备工艺方法同实施例。
上述实施例1~4和对比例1~3制得的环氧绝缘体的性能如表3所示：
表3
Figure DEST_PATH_IMAGE004
各实施例和对比例中，环氧绝缘体的成型条件均为：模具温度180℃，注射压力700kg/cm2，固化时间2min。
如表3的评价结果所示，各实施例中的环氧绝缘体无论是整体力学性能还是流动性均优于各对比例，用于DFN封装器件中能够保证封装结构稳定性，降低封装后内部气孔的发生率，提高封装成品率。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (8)

1.一种高导热DFN封装器件的制备方法，其特征在于：所述高导热DFN封装器件包括位于环氧绝缘体（6）中的散热焊盘（1）、芯片（3）和导电焊盘（4），所述芯片（3）位于散热焊盘（1）上，位于散热焊盘（1）周边设有若干个导电焊盘（4），所述导电焊盘（4）和芯片（3）通过一引线（5）连接；
所述散热焊盘（1）的中央区开有一供芯片（3）嵌入的沉槽（11），从而在散热焊盘（1）的边缘区形成一围堰部（12），所述沉槽（11）的底部和围堰部（12）与芯片（3）的下表面和侧壁之间均设置有银浆层（2），所述沉槽（11）的底部开有若干个延伸至散热焊盘（1）内的换热盲孔（13），所述换热盲孔（13）中具有银浆填充部（21）；
所述环氧绝缘体（6）的原料的制备方法包括以下步骤：
S1. 先将硅微粉65~90份和阻燃剂10~25份与3-氨基丙基三乙氧基硅烷2~5份混合均匀，进行表面处理；
S2. 再加入环氧树脂80~100份、线型酚醛树脂50~70份、液体丁腈橡胶12~18份、焦碳酸二乙酯3~8份、聚乙二醇单辛基苯基醚0.1~1.5份、醋酸丁酸纤维素2~6份、5-氟-2-甲氧基苯胺0.3~2份、2,4,6-三(二甲氨基甲基)苯酚0.5~5份和脱模剂1~5份，混合均匀；
S3. 将混合物于90~110℃混炼3~5分钟，产物冷却后粉碎过筛，以上份数均为重量份。
2.根据权利要求1所述的高导热DFN封装器件的制备方法，其特征在于：所述沉槽（11）深度不大于芯片（3）厚度设置。
3.根据权利要求1所述的高导热DFN封装器件的制备方法，其特征在于：所述换热盲孔（13）为锥形盲孔，所述换热盲孔（13）靠近芯片（3）一端端口的孔径大于换热盲孔（13）远离芯片（3）一端端口的孔径。
4.根据权利要求3所述的高导热DFN封装器件的制备方法，其特征在于：所述换热盲孔（13）延伸至散热焊盘（1）中下部。
5.根据权利要求1所述的高导热DFN封装器件的制备方法，其特征在于：所述围堰部（12）内侧上开有阶梯部（121）。
6.根据权利要求1所述的高导热DFN封装器件的制备方法，其特征在于：所述脱模剂选自硬脂酸、硬脂酸盐或者氧化聚乙烯蜡中的至少一种。
7.根据权利要求1所述的高导热DFN封装器件的制备方法，其特征在于：所述阻燃剂为硼酸盐和/或钼酸盐。
8.根据权利要求1所述的高导热DFN封装器件的制备方法，其特征在于：步骤S3中，混炼温度为100℃。
CN201910131685.6A 2019-02-22 2019-02-22 高导热dfn封装器件的制备方法 Active CN109950158B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202011403562.2A CN112420532B (zh) 2019-02-22 2019-02-22 无引脚dfn封装器件的封装工艺
CN202011426172.7A CN112701054B (zh) 2019-02-22 2019-02-22 电子产品用dfn半导体器件的制造方法
CN201910131685.6A CN109950158B (zh) 2019-02-22 2019-02-22 高导热dfn封装器件的制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910131685.6A CN109950158B (zh) 2019-02-22 2019-02-22 高导热dfn封装器件的制备方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
CN202011403562.2A Division CN112420532B (zh) 2019-02-22 2019-02-22 无引脚dfn封装器件的封装工艺
CN202011426172.7A Division CN112701054B (zh) 2019-02-22 2019-02-22 电子产品用dfn半导体器件的制造方法

Publications (2)

Publication Number Publication Date
CN109950158A CN109950158A (zh) 2019-06-28
CN109950158B true CN109950158B (zh) 2020-11-17

Family

ID=67008018

Family Applications (3)

Application Number Title Priority Date Filing Date
CN202011403562.2A Active CN112420532B (zh) 2019-02-22 2019-02-22 无引脚dfn封装器件的封装工艺
CN202011426172.7A Active CN112701054B (zh) 2019-02-22 2019-02-22 电子产品用dfn半导体器件的制造方法
CN201910131685.6A Active CN109950158B (zh) 2019-02-22 2019-02-22 高导热dfn封装器件的制备方法

Family Applications Before (2)

Application Number Title Priority Date Filing Date
CN202011403562.2A Active CN112420532B (zh) 2019-02-22 2019-02-22 无引脚dfn封装器件的封装工艺
CN202011426172.7A Active CN112701054B (zh) 2019-02-22 2019-02-22 电子产品用dfn半导体器件的制造方法

Country Status (1)

Country Link
CN (3) CN112420532B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725154B (zh) * 2020-06-29 2022-06-10 上海先方半导体有限公司 一种埋入器件的封装结构以及制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102191002A (zh) * 2011-04-02 2011-09-21 烟台德邦科技有限公司 一种耐高湿高热单组分环氧胶粘剂及其制备方法
CN102612744A (zh) * 2009-09-08 2012-07-25 克里公司 具有导热通路的电子器件基座和包括该基座的发光器件

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07242733A (ja) * 1994-03-05 1995-09-19 Toshiba Chem Corp エポキシ樹脂組成物および半導体封止装置
JPH10116940A (ja) * 1996-10-09 1998-05-06 Toshiba Corp 樹脂封止型半導体装置及びその製造方法
JP2001081286A (ja) * 1999-09-13 2001-03-27 Sumitomo Bakelite Co Ltd 半導体用樹脂ペースト及びそれを用いた半導体装置
JP3420153B2 (ja) * 2000-01-24 2003-06-23 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2007016063A (ja) * 2005-07-05 2007-01-25 San Apro Kk 光半導体封止用エポキシ樹脂組成物
KR100782225B1 (ko) * 2005-09-02 2007-12-05 엘에스전선 주식회사 함몰부가 형성된 다이패드를 구비한 리드프레임 및반도체 패키지
JP2011014885A (ja) * 2009-06-01 2011-01-20 Shin-Etsu Chemical Co Ltd 多層半導体装置用アンダーフィル材のダム材組成物、及び該ダム材組成物を用いた多層半導体装置の製造方法
WO2014167993A1 (ja) * 2013-04-11 2014-10-16 東洋紡株式会社 熱伝導性樹脂組成物およびそれを使用した熱伝導性封止体
JP6427974B2 (ja) * 2013-06-21 2018-11-28 住友ベークライト株式会社 半導体封止用樹脂組成物および半導体装置
CN104673111B (zh) * 2014-06-30 2017-01-11 广东丹邦科技有限公司 环氧树脂基各向异性导电胶膜的配方及制备方法
CN104497490B (zh) * 2014-12-22 2017-08-25 科化新材料泰州有限公司 用于全包封器件的高导热环氧树脂组合物及其制备方法
CN105440588B (zh) * 2015-12-24 2017-11-03 江苏中鹏新材料股份有限公司 一种高导热模塑型环氧底填料及其制备方法与用途
JP6332488B2 (ja) * 2017-01-30 2018-05-30 日立化成株式会社 液状エポキシ樹脂組成物の選択方法及び製造方法、並びに電子部品装置及びその製造方法
CN206864460U (zh) * 2017-04-27 2018-01-09 江苏长电科技股份有限公司 一种防止芯片溢胶的封装结构
US10079198B1 (en) * 2017-05-31 2018-09-18 Stmicroelectronics, Inc. QFN pre-molded leadframe having a solder wettable sidewall on each lead

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102612744A (zh) * 2009-09-08 2012-07-25 克里公司 具有导热通路的电子器件基座和包括该基座的发光器件
CN102191002A (zh) * 2011-04-02 2011-09-21 烟台德邦科技有限公司 一种耐高湿高热单组分环氧胶粘剂及其制备方法

Also Published As

Publication number Publication date
CN112701054A (zh) 2021-04-23
CN112420532B (zh) 2022-07-19
CN112701054B (zh) 2022-07-19
CN112420532A (zh) 2021-02-26
CN109950158A (zh) 2019-06-28

Similar Documents

Publication Publication Date Title
US8278743B2 (en) Semiconductor device with heat spreader
US8766430B2 (en) Semiconductor modules and methods of formation thereof
DE102013112592B4 (de) Chipanordnungen und Verfahren zum Herstellen einer Chipanordnung
EP3042932A1 (en) Epoxy resin composition for use in sealing of semiconductors, and semiconductor-packaged structure and method for producing same
KR101833651B1 (ko) 반도체 장치 및 그 제조 방법
CN109950158B (zh) 高导热dfn封装器件的制备方法
CN109904131B (zh) 高稳定性dfn封装器件
CN215377395U (zh) 一种用于半导体芯片的封装结构
US20230386959A1 (en) Chip heat dissipating structure, process and semiconductor device
US6955949B2 (en) System and method for reducing or eliminating semiconductor device wire sweep
CN109904125B (zh) 耐高温qfn封装结构的制备方法
TW200409315A (en) Semiconductor package with stilts for supporting dice
CN113451235B (zh) Qfn封装半导体器件
US9230874B1 (en) Integrated circuit package with a heat conductor
CN110098161A (zh) 浪涌保护器件
CN218867083U (zh) 一种封装体结构及芯片器件
KR19990036775A (ko) 봉입 재료 및 그를 사용한 리드-온-칩 구조 반도체 장치
JP3356398B2 (ja) ディスクリート素子封止用のエポキシ樹脂組成物および樹脂封止型半導体装置
JP5421157B2 (ja) 半導体モジュールの製造方法
KR20130107670A (ko) 열방출을 위한 반도체 패캐지 방열판 구조 및 그 패캐지 제조 방법.
KR20090103510A (ko) 반도체 패키지

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
PE01 Entry into force of the registration of the contract for pledge of patent right
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: Fabrication Methods of DFN Packaging Devices with High Thermal Conductivity

Effective date of registration: 20221214

Granted publication date: 20201117

Pledgee: Xi'an Youyi District Sub branch of China Construction Bank Corp.

Pledgor: XI'AN HANGSI SEMICONDUCTOR Co.,Ltd.

Registration number: Y2022610000807