CN109950013B - Ceramic chip and piezoresistor - Google Patents

Abstract

The invention relates to the technical field of piezoresistors, in particular to a ceramic chip and a piezoresistor. Different piezoresistors are formed at the projection overlapping part between different electrode surfaces, and the discharge element is connected on the first electrode surface in a conductive manner, so that the whole structure forms an equivalent circuit: a discharge tube is connected in series with a voltage dependent resistor with lower voltage dependent voltage and then connected in parallel with a voltage dependent resistor with higher voltage dependent voltage, so that the formed voltage dependent resistor has the advantages of quick response time, high conduction threshold value, low limiting voltage, large flow, low inherent capacitance and low cost.

Description

Ceramic chip and piezoresistor

Technical Field

The invention relates to the technical field of piezoresistors, in particular to a ceramic chip and a piezoresistor.

Background

The piezoresistor is used as safety element, and is suitable for protecting circuit and electric appliance, especially for low-frequency power supply circuit. During the use of the piezoresistor, the lower the limiting voltage of the piezoresistor is required to be, the better the limiting voltage is, namely the higher the protection level of the piezoresistor is required to be, so that the proportion of the protected device which has faults is reduced through the protection of the piezoresistor, and the situation that the protected device is required to improve the withstand voltage level is avoided. However, the voltage-sensitive voltage represents the conduction threshold of the voltage-sensitive resistor, the safety of the voltage-sensitive resistor is greatly influenced by the excessively low voltage-sensitive voltage, and the failure damage rate is greatly increased. Therefore, obtaining a lower voltage limiting varistor without lowering the turn-on threshold is an important goal commonly pursued in this field.

In the prior art, in order to achieve the purpose, a discharge tube and a voltage dependent resistor with a low voltage dependent voltage value are generally connected in series to achieve the purpose, when the normal surge-free state is realized, the discharge tube is in a non-conducting state, and the voltage dependent resistor is not connected into a circuit loop, so that the damage caused by abnormity such as power grid fluctuation is avoided. When surge comes, the discharge tube is conducted to enable the voltage dependent resistor access circuit to present low limiting voltage so as to achieve the protection purpose. When the surge disappears, the piezoresistor returns to a high-resistance state to interrupt the following current of the power grid, so that the discharge tube returns to a disconnected state, the piezoresistor is separated from a circuit loop, and the aim of safe operation is fulfilled. However, this circuit has an important drawback that, because the response time of the discharge tube is slow, typically 1 μ s, and the waveform of the surge of thunder and lightning is steep and narrow, typically 20 μ s, the discharge tube is not yet conducted, and the surge wave head enters the post-stage circuit, which seriously affects the protection effect. The solution is to connect a voltage dependent resistor in parallel at both ends of the series branch, and to absorb the steep wave head of the surge by using the fast response time (<20ns) of the voltage dependent resistor.

In the combined circuit, different parameters can be selected according to different functions of the three elements, and the discharge tube and the piezoresistor series branch are main channels for absorbing surge energy. The electrode area of the piezoresistor needs to be large, so that larger flux can be provided. The voltage-dependent resistor is connected in parallel with the voltage-dependent resistor, and the voltage-dependent resistor is only connected firstly when a surge wave head occurs, so that the surge amplitude is not high and the energy is not large. Therefore, the voltage-dependent voltage can be selected higher to avoid damage caused by grid anomalies, and the size can be much smaller than that of the voltage-dependent resistor in the series branch. Because once the discharge tube and the piezoresistor series branch are conducted, most surge current can pass through the series piezoresistor branch, and no large current can pass through the parallel piezoresistor.

After the parameters are selected, the combined circuit also has the advantage of low inherent capacitance, the inherent capacitance of the series branch is very low due to the fact that the discharge tube is an air medium and the dielectric constant is very low, and the inherent capacitance of the parallel small-size piezoresistor is also very low due to the fact that the electrode area is reduced, so that the inherent capacitance of the whole circuit combination is much lower than that of a single piezoresistor with the same flux, and the combined circuit can be applied to working occasions with higher frequency than that of the piezoresistor used alone.

The combined circuit constructed by the prior art has the following disadvantages although the advantages are provided: firstly, the cost is high, and three separate elements have many identical manufacturing steps to be repeated respectively, such as electrode manufacturing, lead wire connection, insulation packaging and the like, so that the cost is high, and the popularization and application are influenced; secondly, the installation volume is large, and three elements occupy more installation space, which is not favorable for the miniaturization direction of the whole machine; and thirdly, the increase of elements causes the circuit to be complex and affects the reliability of the whole machine, and the three elements have six lead-out welding spots and corresponding wiring, so that the workload and unreliable factors of the manufacture of a circuit board of the whole machine can be increased, more parasitic inductance and capacitance can be brought, and the response time of the circuit is affected.

The invention aims to: aiming at the problems that when a combined circuit with good performance parameters such as quick response time, large flow, high conduction threshold, low limiting voltage, low inherent capacitance and the like is formed by connecting a discharge tube and a piezoresistor with a low voltage-sensitive voltage value in series and then connecting the piezoresistor with a high voltage-sensitive voltage value in parallel in the prior art, the manufacturing steps and the circuit layout are complicated, the cost is high, the installation volume is large, more parasitic inductance and capacitance exist, and the response time of the circuit is influenced, a ceramic chip and a piezoresistor are provided, the piezoresistor manufactured by the ceramic chip not only has the good performance parameters such as quick response time, large flow, high conduction threshold, low limiting voltage and low inherent capacitance, but also shares the structures such as an electrode, a lead wire, an insulating packaging layer and the like after the integrated combination, thereby achieving the purposes of reducing the cost and reducing the volume, in addition, the connected lead and welding spot are greatly reduced, the reliability is improved, the parasitic inductance and capacitance brought by more lead connections are reduced, and the response time is further prolonged

In order to achieve the above purpose, the invention provides the following technical scheme:

a ceramic chip comprises a third electrode surface, a first electrode surface and a second electrode surface, wherein the first electrode surface and the second electrode surface are arranged on the opposite sides of the third electrode surface, and the second electrode surface and the first electrode surface are independent.

The second electrode surface and the first electrode surface are mutually independent, and the first electrode surface and the second electrode surface are mutually independent in the physical connection mode and are mutually independent in the electric connection mode.

The physical connection mode independently comprises the situation that the second electrode surface and the first electrode surface are positioned on two different planes, and also comprises the situation that the second electrode surface and the first electrode surface are positioned on the same plane but are relatively independent and separated; the mutual independence in the electrical connection sense also includes the situation that the first electrode surface and the second electrode surface are connected in the physical sense, but an insulator is arranged between the first electrode surface and the second electrode surface.

A ceramic chip with three surfaces is manufactured by adopting a piezoresistor forming process, and conductive electrodes are coated on each surface according to a piezoelectrode manufacturing process to form three electrode surfaces. Since the second electrode surface and the first electrode surface are arranged on the opposite side of the third electrode surface, the second electrode surface and the first electrode surface form different piezoresistors (for example, the first electrode surface and the third electrode surface form a first piezoresistor, and the second electrode surface and the third electrode surface form a second piezoresistor), so that when the ceramic chip is used after being used for manufacturing the piezoresistor, under normal conditions and when a large surge occurs in the line, the current characteristics are represented by different piezoresistors, different piezoresistors can be made to function at different stages according to requirements, so that the piezoresistor formed by combining the ceramic chips not only has the capability of absorbing large surge, but also has lower limiting voltage, on the basis of ensuring a higher conduction threshold value to ensure the safety and reliability of the piezoresistor, the residual voltage at two ends of the piezoresistor can be further reduced, and the protection level of the piezoresistor is greatly improved. Meanwhile, when the ceramic chip with the structure is used for combining and forming the piezoresistor for use, the repeated same processing steps are reduced, so that the production cost is saved, and the reliability level of circuit protection is improved.

Preferably, the first electrode surface, the second electrode surface and the third electrode surface are three planes arranged in parallel.

The three electrode surfaces are set to be parallel planes, so that the voltage-sensitive voltage of each formed piezoresistor is convenient to calculate and control, and the area and the relative distance of each electrode surface of the ceramic chip are adjusted according to the requirements of different piezoresistor models, thereby forming the piezoresistor with different voltage-sensitive voltages and flow rates and meeting different use occasions.

Preferably, projections of the first electrode surface and the second electrode surface on the third electrode surface are overlapped with the third electrode surface, and the first electrode surface and the second electrode surface are used for connecting the gas discharge element.

Preferably, the ceramic chip is provided with a groove, the groove is positioned on the opposite surface of the third electrode surface, the second electrode surface is arranged on the groove bottom of the groove, and the first electrode surface is arranged along the end surface of the ceramic chip, which is provided with the groove.

The grooves are positioned on the opposite surface of the third electrode surface, the bottom surface of the concave groove of the surface is provided with a second electrode surface, and the outer edge of the surface is not provided with a concave end surface part which is provided with the first electrode surface.

The ceramic chip is provided with a groove, a conductive electrode plate is arranged on a first electrode surface of the end surface of the groove, the first electrode surface connected with the conductive electrode plate and a third electrode surface form a first piezoresistor, the electrode surface of the conductive electrode plate and a second electrode surface form a discharge gap, the second electrode surface and the third electrode surface form a second piezoresistor, under the normal condition, the small current characteristic is reflected by the first piezoresistor, when the circuit has large surge, the discharge gap between the conductive electrode plate and the second electrode surface is conducted, the second piezoresistor is conducted, the second electrode surface is arranged to be larger, most of energy is absorbed by the second piezoresistor, the groove structure is adopted, the piezoresistor voltage of the second piezoresistor can be made to be very low by adjusting the depth of the groove, so that the limiting voltage at two ends of the piezoresistor is very low, and the second piezoresistor and the discharge gap are connected in series, and then the voltage-sensitive resistor is in parallel connection with the first voltage-sensitive resistor, and the residual voltage at two ends of the voltage-sensitive resistor formed by combination is mainly determined by the second voltage-sensitive resistor. The capacitance is mainly determined by the first piezoresistor, the surge wave head is absorbed by the first piezoresistor, the surge wave energy is mainly absorbed by the first piezoresistor and the second piezoresistor in parallel, but the second piezoresistor absorbs the main energy, and the effect of quick response and large surge impact of the piezoresistor is realized.

The distance between the bottom of the groove of the ceramic chip and the conductive electrode plate is adjusted to obtain the width of a discharge gap, the narrower the discharge gap is, the lower the breakdown voltage is, the air gap between the conductive electrode plate and the second electrode surface can also be regarded as an air dielectric flat capacitor, because the dielectric constant (about 1) of air is far lower than the series branch of the dielectric constant (about 7-9) of the voltage-sensitive ceramic plate and the second voltage-sensitive resistor, the inherent capacitance can be approximately represented by the inherent capacitance of the air gap, and the wider the gap is, the smaller the inherent capacitance is.

Preferably, the width of the discharge gap is 0.05-0.5 mm.

Preferably, the ceramic chip is a cylinder, and the groove is a cylindrical hole formed in one end of the cylinder.

Further, the cylindrical hole is coaxial with the cylinder.

The ceramic chip is arranged to be a cylinder, one end of the ceramic chip is a third electrode surface, the other end of the ceramic chip is provided with a cylindrical hole, the bottom surface of the cylindrical hole is a second electrode surface, and the end surface of the cylindrical hole is a circular first electrode surface.

The conductive electrode plate is connected to the circular ring surface, and a gap is formed between the conductive electrode plate and the second electrode surface at the bottom of the cylindrical hole.

Set up ceramic chip into the cylinder, the recess is established to the cylinder hole of arranging at the cylinder terminal surface, is convenient for adjust the area of torus and the size in cylinder hole to adjust the limiting voltage and the inherent electric capacity of the piezoresistor who is formed by this ceramic chip combination, concrete work reason is the aforesaid, no longer gives details.

The ceramic chip is made into a cylinder and is provided with a cylindrical hole-shaped groove, the static capacitance of the piezoresistor formed by combining the ceramic chips is mainly determined by the annular first electrode surface and the annular third electrode surface, and the annular first electrode surface can be made to be very small, so that the capacitance of the first piezoresistor can be made to be very small. The piezoresistor formed by the ceramic chip combination has the voltage-sensitive voltage determined by the first piezoresistor, and the voltage-sensitive voltage is characterized by the first piezoresistor on the aspect of low current characteristic, although the capacitance between the second electrode surface and the third electrode surface is larger, a certain discharge gap exists between the first electrode surface and the second electrode surface, the dielectric difference is realized, the capacitance between the discharge gap and the second electrode surface is far lower than that of the first piezoresistor, and the capacitance formed by the discharge gap and the second piezoresistor in series connection is determined by the discharge gap, so the capacitance of the whole piezoresistor can be made very small.

Besides the cylindrical shape, the ceramic chip can be made into a square shape, and the groove can also be made into a square shape, a round shape or other shapes.

Preferably, the ceramic chip is a pressure sensitive tile.

Further, the ceramic chip is a square pressure-sensitive ceramic chip, and the groove is a square hole formed in one end of the square pressure-sensitive ceramic chip.

Preferably, the first electrode surface, the second electrode surface and the third electrode surface are conductive coatings coated on the ceramic chip.

Preferably, the pressure-sensitive material used for manufacturing the pressure-sensitive ceramic tile is metal oxide.

Furthermore, the metal oxide is zinc oxide as a main component.

Correspondingly, the invention also provides a piezoresistor, wherein a gas discharge element is arranged between the first electrode surface and the second electrode surface of the ceramic chip, the third electrode surface is electrically connected with a first extraction electrode, and the first electrode surface or the second electrode surface is electrically connected with a second extraction electrode.

The piezoresistor of the scheme is characterized in that a gas discharge element is arranged on the ceramic chip, the gas discharge element is arranged between a first electrode surface and a second electrode surface, a third electrode surface of the piezoresistor is connected with a first leading-out electrode, meanwhile, the first electrode surface or the second electrode surface is connected with a second leading-out electrode, the first electrode surface and the third electrode surface form a first piezoresistor, the second electrode surface and the third electrode surface form a second piezoresistor, meanwhile, the gas discharge element is arranged between the first electrode surface and the second electrode surface, and equivalently, the gas discharge element is connected in series on a branch circuit of the first piezoresistor or the second piezoresistor. Under normal conditions, the characteristic of small current is embodied by a first voltage dependent resistor, when a line has large surge, a gas discharge element is conducted, a second voltage dependent resistor is conducted, lower limiting voltage can be obtained through a larger electrode surface, most energy is absorbed by the second voltage dependent resistor, through adjusting the thickness of the second voltage dependent resistor, the voltage dependent voltage of the second voltage dependent resistor can be made very low, so that the limiting voltage at the two ends of the voltage dependent resistor is very low, the second voltage dependent resistor and the gas discharge element are connected in series to form a branch circuit, the branch circuit and the first voltage dependent resistor are in a parallel state, and the residual voltage at the two ends is mainly determined by the second voltage dependent resistor. The capacitance is mainly determined by the first piezoresistor, the surge wave head is absorbed by the first piezoresistor, most of surge wave energy is absorbed by the first piezoresistor and the second piezoresistor together, but the second piezoresistor absorbs main energy, and the piezoresistor can quickly respond to large surge impact.

Preferably, the gas discharge element is a discharge gap formed between the conductive electrode sheet and the second electrode surface.

The first electrode surface is connected with a conductive electrode plate, a discharge gap is formed between the conductive electrode plate and the second electrode surface, the discharge gap is used as a gas discharge element, and the function of the piezoresistor is realized by adjusting the distance of each electrode surface of the ceramic chip, the size of the electrode surface and the size of the overlapped part of the electrode surfaces. The piezoresistor with the structure is simple in structure and manufacturing process, and can reduce manufacturing cost and improve reliability of circuit protection.

A conductive electrode plate is connected to the first electrode surface, and a discharge gap is formed between the conductive electrode plate and the second electrode surface to serve as a gas discharge element.

Preferably, a groove is formed in the ceramic chip, and a protrusion protruding into the groove is correspondingly formed on the conductive electrode sheet.

The grooves are formed in the ceramic chip, the protrusions are correspondingly arranged on the conductive electrode plates, so that the grooves can be made deeper, the discharge gap distance between the conductive electrode plates and the bottoms of the grooves is adjusted through the protrusions, different types of piezoresistors are manufactured, and different use requirements are met.

The width of a discharge gap can be adjusted by adjusting the downward projection depth of the conductive electrode plate, the narrower the gap is, the lower the breakdown voltage is, the air gap between the conductive electrode plate and the second electrode surface can also be regarded as an air dielectric flat capacitor, because the dielectric constant (about 1) of air is far lower than the series branch of the dielectric constant (about 7-9) of the voltage-sensitive ceramic chip and the second piezoresistor, the inherent capacitance can be approximately represented by the inherent capacitance of the air gap, the wider the gap is, the smaller the inherent capacitance is, and the preferable width of the discharge gap can be selected to be 0.05-0.5 mm.

Preferably, the protrusion is formed by protruding the conductive electrode sheet, and the protrusion height of the protrusion corresponds to the depth of the groove of the ceramic chip and forms a discharge gap.

The depth of the downward projection of the conductive electrode plate is approximately consistent with the depth of the groove of the ceramic chip, and a certain gap is formed, wherein the gap is a discharge gap between the conductive metal sheet and the ceramic chip, and the discharge gap is in discharge conduction when a circuit has large surge.

Preferably, the lower convex surface of the protrusion corresponds to the shape of the second electrode surface, and the lower convex surface and the second electrode surface are arranged at equal intervals.

The lower convex surface of the protruding part of the conductive electrode plate is arranged corresponding to the second electrode surface at equal intervals, so that the distance between each point on the lower convex surface of the protruding part and the projection point of the point on the second electrode surface is equal, the width of a discharge gap between the protruding part and the second electrode surface is ensured to be uniform, and the piezoresistor is ensured to form effective and reliable protection on a circuit.

Preferably, a conducting strip for adjusting the width of the discharge gap is arranged on the second electrode surface of the ceramic chip.

The second electrode surface on the ceramic chip groove is provided with a conducting strip, a discharge gap is formed between the conducting strip and the conducting electrode plate, and the discharge gap distance between the conducting strip and the conducting electrode plate can be adjusted by adjusting the thickness of the conducting strip.

Further, the conducting sheet is a conducting metal sheet.

Further, when a conductive electrode sheet is employed, a discharge gap is formed between the conductive sheet and the conductive electrode sheet.

Preferably, the conductive electrode plate is hermetically connected with the first electrode surface, so that the cavity of the discharge gap is a sealed cavity.

After the conductive electrode plate is connected with the first electrode surface in a sealing mode, a discharge gap formed by the conductive electrode plate and the second electrode surface is a sealed cavity, so that the conductive electrode plate is isolated from air, the conductive electrode plate and the second electrode surface can be prevented from being oxidized due to contact with air, the conductive electrode plate and the second electrode surface can be prevented from being seriously oxidized in a discharge process, if necessary, inert gases such as argon, neon or nitrogen can be filled into the sealed cavity to further protect the electrodes, a normal discharge function is guaranteed, and the piezoresistor can reliably protect a circuit.

Further, after the conductive electrode plate is connected to the first electrode surface in a sealing mode, a discharge gap is formed between the conductive electrode plate and the second electrode surface, and a cavity of the discharge gap is a sealed cavity.

Preferably, the width of the discharge gap is 0.05-0.5 mm. The corresponding discharge voltage is 0.5-3.5 KV.

Instead of the protruding portion protruding downward, a metal sheet may be connected to the second electrode surface of the ceramic chip by welding or the like to form an protruding portion protruding upward, and the height of the metal protrusion may be adjusted to adjust the width of the discharge gap.

Preferably, the piezoresistor is coated with an insulating layer on the other surfaces except for the leading ends of the first and second leading electrodes.

Compared with the prior art, the invention has the beneficial effects that:

1. the ceramic chip comprises three electrode surfaces, the electrode surfaces are arranged side by side and are not intersected with each other, different piezoresistors are formed at the projection overlapping part between different electrode surfaces, so that when the ceramic chip is used for manufacturing the piezoresistor, under the normal condition and when a large surge is generated on a circuit, the current characteristics are embodied by the different piezoresistors, different piezoresistors can play a role in different stages according to requirements, the piezoresistor formed by combining the ceramic chips has the capability of absorbing the large surge, the limiting voltage is lower, the conduction threshold value can be higher, the safety and the reliability of the element are ensured, meanwhile, the quick response time of the piezoresistor is kept, and the inherent capacitance is reduced.

2. The shape of the ceramic chip, the size of the electrodes, the distance between the electrodes, the size of the conductive electrode plate, the depth of the downward bulge and other key shape dimensions can be conveniently designed by utilizing the forming die so as to realize expected technical parameters. The manufacturing processes including electrode coating, lead connection, insulation packaging and the like are mature and stable, have good consistency and can continuously and stably produce expected finished products.

3. The combination of three series-parallel circuits of the separated elements is integrally manufactured on a ceramic chip, the important sizes of the first piezoresistor, the second piezoresistor, the electrode area, the thickness, the gap width and the like of the discharge gap can be conveniently preset, the expected effect is achieved, the structures of the electrode, the lead, the insulating wrapping layer and the like can be shared, and the purposes of reducing the cost and reducing the volume are achieved.

4. The number of leads is reduced, so that the number of mounting welding spots is reduced, corresponding wiring is reduced, the complexity of the whole machine is reduced, the safety and reliability are improved, parasitic inductance and capacitance caused by wiring are reduced, and the response time to surge is prolonged.

Description of the drawings:

fig. 1 is a schematic structural view of a ceramic chip in example 1.

Fig. 2 is a sectional view taken along a-a in fig. 1.

Fig. 3 is a schematic structural view of a ceramic chip in example 2.

Fig. 4 is a cross-sectional view taken along line D-D in fig. 3.

Fig. 5 is a schematic structural view of a ceramic chip in example 3.

Fig. 6 is a sectional view taken along B-B in fig. 5.

Fig. 7 is a schematic diagram of the varistor in embodiment 4.

Fig. 8 is a schematic view of the structure of a varistor in embodiment 5.

Fig. 9 is a schematic structural diagram of the varistor of fig. 8 after the mounting of the leads.

Fig. 10 is a schematic structural view of a varistor in embodiment 6.

Fig. 11 is a schematic structural view of the varistor of fig. 10 after mounting the leads.

Fig. 12 is a schematic structural view of the conductive electrode sheet in fig. 10.

Fig. 13 is an equivalent circuit diagram.

The labels in the figure are: 1-ceramic chip, 11-first electrode surface, 12-second electrode surface, 13-third electrode surface, 1A-groove, 2-conductive electrode sheet, 23-protrusion, D1-conductive electrode sheet thickness, D2-ceramic chip thickness difference, D3-discharge gap width, 4-pin, 41-first pin, 42-second pin, 5-discharge gap, 6-conductive sheet, U1-first piezoresistor, U2-second piezoresistor, 7-gas discharge element, 8-first leading-out electrode, 9-second leading-out electrode.

Detailed Description

The present invention will be described in further detail with reference to test examples and specific embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.

Example 1

The ceramic chips of the present embodiment are used in combination to form low limiting voltage, low intrinsic capacitance piezoresistors.

As shown in fig. 1 and 2, the ceramic chip 1 has a cylindrical structure, and one end of the cylinder is provided with a groove 1A, where the groove 1A is a cylindrical hole.

The ceramic chip 1 of the present embodiment includes a plurality of planes on which an upper electrode layer is coated to form electrode surfaces, including a second electrode surface 12 disposed at the bottom of the cylindrical hole, and a first electrode surface 11 and a third electrode surface 13 disposed at both end surfaces of the ceramic chip of the cylindrical structure, the three electrode surfaces being disposed side by side, and the three electrode surfaces being in a parallel state.

As one embodiment, the ceramic chip of the present embodiment has a cylindrical structure, and may have other structures.

When the ceramic chip of this embodiment is combined into a varistor, the conductive electrode sheet is connected to the first electrode surface 11 having a circular ring shape, and forms a discharge gap with the second electrode surface 12 at the bottom of the cylindrical hole, and the discharge gap becomes a gas discharge element connected between the first electrode surface 11 and the second electrode surface 12.

As an embodiment, the first electrode surface 11, the second electrode surface 12, and the third electrode surface 13 of the present embodiment are three electrode planes arranged in parallel. The embodiment of non-parallelism among multiple electrode surfaces can also be adopted.

As an implementation manner, the projection surfaces of the first electrode surface 11 and the second electrode surface 12 on the third electrode surface 13 all fall on the third electrode surface 13, and the first electrode surface 11 is used for connecting a conductive electrode sheet.

In one embodiment, the ceramic chip of the present embodiment is a pressure-sensitive ceramic chip, and other materials having pressure-sensitive characteristics may be used to manufacture the ceramic chip, and the electrode surfaces may be provided on the manufactured ceramic chip.

As one of the embodiments, the cylindrical hole is arranged coaxially with the cylinder in this embodiment. It is contemplated that the cylindrical bores may be otherwise arranged.

The material for manufacturing the pressure-sensitive ceramic chip in this embodiment is a metal oxide, and the pressure-sensitive ceramic chip is manufactured by a ceramic process, specifically, the metal oxide may be ZnO or other materials.

A ceramic chip with three domain surfaces is manufactured by adopting a pressure-sensitive forming process, and conductive electrodes are coated on each surface according to a pressure-sensitive electrode manufacturing process to form three electrode surfaces. Because set up side by side and two liang of non-intersections between the electrode face, form different piezo-resistor between the different electrode face, specifically as: the first electrode surface and the third electrode surface form a first piezoresistor, and the second electrode surface and the third electrode surface form a second piezoresistor, so that when the ceramic chip is used for manufacturing a piezoresistor and then used, under normal conditions and when a large surge occurs on a circuit, the current characteristics are embodied by different piezoresistors, different piezoresistors can play a role in different stages according to requirements, and the piezoresistor formed by combining the ceramic chips has the capability of absorbing the large surge, and the limiting voltage is lower. Meanwhile, when the ceramic chip with the structure is used for combining and forming the piezoresistor for use, the number of electrodes, leads and insulating wrapping layers is reduced, so that the production cost is saved, and the reliability level of circuit protection is improved.

Example 2

The ceramic chips of the present embodiment are used in combination to form low limiting voltage, low intrinsic capacitance piezoresistors.

As shown in fig. 3 and 4, the ceramic chip 1 has a rectangular structure, and a groove 1A is formed in an upper bottom surface of the rectangular structure, and the groove 1A is a rectangular hole.

The ceramic chip 1 of the present embodiment includes a plurality of planes, and an upper electrode layer is coated on the plurality of planes to form electrode surfaces, including a second electrode surface 12 disposed at the bottom of a rectangular hole, and a first electrode surface 11 and a third electrode surface 13 disposed on the upper and lower bottom surfaces of the ceramic chip having a rectangular parallelepiped structure, and the three electrode surfaces are disposed side by side and in parallel. The first electrode surface 11 is arranged annularly outside the second electrode surface 12.

As one embodiment, the ceramic chip of the present embodiment has a rectangular parallelepiped structure, and may also have a square ceramic body or other structural forms.

When the ceramic chip of this embodiment is combined into a varistor, the conductive electrode sheet is connected to the first electrode surface 11 of the rectangular ring, and forms a discharge gap with the second electrode surface 12 at the bottom of the rectangular hole, and the discharge gap serves as a gas discharge element connected between the first electrode surface and the second electrode surface.

As an embodiment, the first electrode surface 11, the second electrode surface 12, and the third electrode surface 13 of the present embodiment are three electrode planes arranged in parallel.

As an implementation manner, the projection surfaces of the first electrode surface 11 and the second electrode surface 12 on the third electrode surface 13 all fall on the third electrode surface 13, and the first electrode surface 11 is used for connecting a conductive electrode sheet.

The ceramic chip is a pressure-sensitive ceramic piece, the pressure-sensitive ceramic piece is made into the shape implemented in the embodiment, and each electrode surface is arranged on the pressure-sensitive ceramic piece.

Example 3

The ceramic chips of the present embodiment are used in combination to form low limiting voltage, low intrinsic capacitance piezoresistors.

As shown in fig. 5 and 6, the ceramic chip 1 has a rectangular structure, a third electrode surface 13 is disposed on a lower bottom surface of the ceramic chip 1, a first electrode surface 11 and a second electrode surface 12 are disposed on an upper bottom surface of the ceramic chip 1, and the first electrode surface 11 and the second electrode surface 12 are located on different planes to form two relatively independent step surfaces.

The ceramic chip 1 of the present embodiment includes a plurality of flat surfaces, and electrode layers are coated on the lower and upper bottom surfaces to form electrode surfaces, and the first electrode surface 11 and the second electrode surface 12 are not connected independently of each other because they are on different planes.

When the ceramic chip of the present embodiment is combined into a varistor, the conductive electrode sheet is connected to the first electrode surface 11, and forms a discharge gap with the second electrode surface 12, and the discharge gap serves as a gas discharge element connected between the first electrode surface 11 and the second electrode surface 12.

Example 4

The varistor manufacturing method of the present embodiment is used in the process of manufacturing a varistor.

The piezoresistor, as shown in fig. 7, comprises a ceramic chip 1, the ceramic chip 1 comprises three electrode surfaces, including a third electrode surface 13, and a first electrode surface 11 and a second electrode surface 12 arranged on the opposite side of the third electrode surface 13, the second electrode surface 12 and the first electrode surface 11 are independent from each other, a gas discharge element 7 is arranged between the first electrode surface 11 and the second electrode surface 12, a first extraction electrode 8 is electrically connected to the third electrode surface 13, and a second extraction electrode 9 is electrically connected to the first electrode surface 11 or the second electrode surface 12.

In the present embodiment, the second electrode surface 12 and the first electrode surface 11 are physically independent from each other, and an insulator may be disposed between the second electrode surface 12 and the first electrode surface 11, so as to be physically connected by the insulator, but the electrode layers covered on the two electrode surfaces are independently electrically connected or independently conductive.

As shown in fig. 13, the first electrode surface 11 and the third electrode surface 13 form a first varistor U1, the second electrode surface 12 and the third electrode surface 13 form a second varistor U2, and the gas discharge element 7 is provided between the first electrode surface 11 and the second electrode surface 12, which corresponds to the discharge gap 5 (the gas discharge element 7 in fig. 11) connected in series to a branch of the second varistor U2. Under normal conditions, the low current characteristic is embodied by the first piezoresistor U1, when a line has a large surge, the gas discharge element 7 is switched on, the second piezoresistor U2 is switched on, a lower limiting voltage can be obtained through a larger electrode surface, most of energy is absorbed by the second piezoresistor U2, the piezoresistor U2 can be made to be very low in voltage by adjusting the thickness of the second piezoresistor U2, so that the limiting voltage at two ends of the piezoresistor is very low, the second piezoresistor U2 and the gas discharge element 7 (which is equivalent to a discharge gap 5 in an equivalent circuit diagram) are connected in series to form a branch, the branch is in a parallel state with the first piezoresistor U1, and the residual voltage at two ends is mainly determined by the second piezoresistor U2. The capacitance is mainly determined by the first piezoresistor U1, the surge wave head is absorbed by the first piezoresistor U1, most of surge wave energy is absorbed by the first piezoresistor U1 and the second piezoresistor U2 together, but the second piezoresistor U2 absorbs main energy, and the quick response and large surge impact of the piezoresistor is realized.

Example 5

The piezoresistor of the present embodiment is used for connection in a protection circuit.

The varistor, as shown in fig. 8 and 9, comprises the ceramic chip 1 according to embodiment 1 or embodiment 2, wherein the conductive electrode sheet 2 is disposed on the first electrode surface 11 of the ceramic chip 1, the projection surface of the conductive electrode sheet 2 on the second electrode surface 12 overlaps with the second electrode surface 12, the conductive sheet 6 for adjusting the width of the discharge gap is welded on the second electrode surface 12 to form a convex protrusion, so that a discharge gap is formed between the conductive electrode sheet 2 and the conductive sheet 6, the discharge gap is a gas discharge element connected between the first electrode surface 11 and the second electrode surface 12, and if the design requires that the difference between the varistor voltages of the first varistor and the second varistor is not large, that is, the difference D2 between the varistor thicknesses of the ceramic chips is not large, the varistor 6 can be omitted.

The above-described embodiments are only embodiments of the present embodiment, and include various embodiments.

As one of the embodiments, the varistor of the present embodiment is formed by combining the ceramic chips 1 described in embodiment 1 or embodiment 2.

In this embodiment, a discharge gap formed by the conductive electrode sheet 2 provided on the first electrode surface 11 of the ceramic chip 1 and the second electrode surface is used as a gas discharge element.

As one embodiment, the conductive electrode sheet of the present embodiment is a metal conductive electrode sheet, and a conductive electrode sheet made of other conductive materials such as a graphite conductive electrode sheet may also be used.

As one embodiment, the conductive electrode sheet of the present embodiment has a flat plate structure, and other types of conductive electrode sheets, such as the conductive electrode sheet structure described in embodiment 6, may also be adopted.

As an embodiment, the conductive electrode sheet in this embodiment is hermetically connected to the first electrode surface 11, so that a sealed cavity is formed between the second electrode surface 12 and the conductive electrode sheet 2. The conductive electrode sheet 2 may be sealed or unsealed as long as a discharge gap is formed between the conductive electrode sheet and the convex protrusion on the second electrode surface 12.

In one embodiment, the discharge gap distance between the lower convex surface of the protrusion of the conductive electrode sheet 2 and the second electrode surface is 0.05-0.5 mm. The corresponding discharge voltage is 0.5-3.5 KV.

Instead of the protruding portion protruding downward, a metal sheet may be connected to the second electrode surface of the ceramic chip by welding or the like to form an protruding portion protruding upward, and the height of the metal protrusion may be adjusted to adjust the width of the discharge gap.

As an implementation manner, except for the leading ends of the first leading electrode and the second leading electrode, the other surfaces of the piezoresistor are wrapped by the insulating layer, and the first leading electrode and the second leading electrode of this embodiment adopt the pin 4.

The piezoresistor of the scheme is provided with the conductive electrode plate 2 on the ceramic chip, the conductive electrode plate 2 is positioned on the first electrode surface 11 of the ceramic chip 1, the projection surface of the conductive electrode plate 2 on the second electrode surface 12 is overlapped with the second electrode surface 12, so that a discharge gap is formed between the conductive electrode plate and the convex protrusion on the second electrode surface 12, meanwhile, a second piezoresistor is formed between the second electrode surface 12 and the third electrode surface 13, and a first piezoresistor is formed between the first electrode surface 11 and the third electrode surface 13.

Specifically, the first lead electrode and the second lead electrode in this embodiment are pins, the first pin 41 is connected to the third electrode surface 13 of the varistor in this embodiment, and the second pin 42 is connected to the conductive electrode sheet, so that the connection between the conductive electrode sheet and the first electrode surface is equivalent to the connection between the second lead electrode on the first electrode surface, and after the first pin 41 and the second pin 42 are connected to a circuit, an equivalent circuit diagram is shown in fig. 13, where the conductive electrode sheet (equivalent to the first electrode surface 11) and the third electrode surface 13 form a first varistor U1, the conductive electrode sheet (equivalent to the first electrode surface 11) and the second electrode surface 12 protrude to form a discharge gap 5, and the connection between the conductive electrode sheet (equivalent to the first electrode surface 11) and the second electrode surface 12 is equivalent to the connection between a gas discharge element (such as a discharge tube), and the second varistor U2 is formed by the second electrode surface 12 and the third electrode surface 13. Under normal conditions, the characteristic of small current is embodied by the first piezoresistor U1, when the line has large surge, the discharge gap 5 between the conductive electrode sheet and the convex protrusion on the second electrode surface 12 is conducted (equivalent to gas discharge element discharge), the second piezoresistor U2 is conducted, because the electrode surface is larger and has low voltage limiting, most of the energy is absorbed by the second piezoresistor U2, the voltage limiting voltage of the second piezoresistor U2 can be made very low by adjusting the thickness difference D2 of the ceramic chip between the first electrode surface 11 and the second electrode surface 12, so that the voltage limiting voltage of two ends of the piezoresistor U6332 is very low, the series branch of the first piezoresistor U1 and the discharge gap 5 and the second piezoresistor U2 is in parallel connection, the residual voltage of two ends is determined by the second piezoresistor U2, while the first piezoresistor U1 mainly determines, the wave head is absorbed by the first piezoresistor U1, most of the energy of the surge is absorbed by the first piezoresistor U1 and the second piezoresistor U2 in parallel connection, but the second piezoresistor U2 absorbs main energy, so that the pressure-sensitive quick response and large surge impact are realized.

Example 6

The piezoresistor of the present embodiment is used for connection in a protection circuit.

A varistor, as shown in fig. 10, 11 and 12, comprises a ceramic chip 1 of low limiting voltage and low intrinsic capacitance as described in embodiment 1 or embodiment 2, wherein a conductive electrode sheet 2 is provided on a first electrode surface 11 of the ceramic chip 1, and a projection surface of the conductive electrode sheet 2 on a second electrode surface 12 is overlapped with the second electrode surface 12, so that a discharge gap is formed between the conductive electrode sheet 2 and the second electrode surface 12, and the varistor is used as a gas discharge element.

The varistor of this embodiment is substantially the same as embodiment 5, except for the structural form of the conductive electrode sheet 2 and the manner of adjusting the discharge gap width D3.

In one embodiment, the ceramic chip 1 is provided with a groove 1A, and the conductive electrode sheet 2 of the present embodiment is correspondingly provided with a protrusion 23 protruding downward toward the groove 1A.

In one embodiment, the protrusion 23 is formed by protruding the conductive electrode pad 2 downward, and the thickness of the protrusion 23 is substantially the same as the thickness of the conductive electrode pad. It is easily conceivable that the thickness of the coating layer is adjusted to adjust the discharge gap width D3 by forming a discharge gap between the conductive electrode sheet 2 and the second electrode surface 12 by coating the conductive electrode sheet 2 to be thicker.

The discharge gap width D3 of the present embodiment is obtained by adjusting the thickness D1 of the conductive electrode sheet and the thickness difference D2 of the ceramic chip, resulting in the desired discharge gap width D3.

In one embodiment, the lower convex surface of the protrusion 23 corresponds to the shape of the second electrode surface 12, the lower convex surface is equidistant from the second electrode surface 12, the lower convex surface of the protrusion 23 does not correspond to the shape of the second electrode surface 12, and a gap is formed between the lower convex surface of the protrusion 23 and the second electrode surface 12.

The equivalent circuit diagram formed by the piezoresistor of the present embodiment is shown in fig. 13.

The working principle of the piezoresistor is as follows: in the varistor of the present embodiment, the first pin 41 is connected to the third electrode surface 13, which is equivalent to connecting the first lead electrode to the third electrode surface, and since the conductive electrode tab is connected to the first electrode surface 11, when the second pin 42 is connected to the conductive electrode tab, which is equivalent to connecting the second lead electrode to the first electrode surface 11, the conductive electrode tab and the third electrode surface 13 form the first varistor U1, the conductive electrode tab and the second electrode surface 12 form the discharge gap 5, and the second electrode surface 12 and the third electrode surface 13 form the second varistor U2. Under normal conditions, the characteristic of small current is embodied by a first piezoresistor U1, when a line has large surge, the discharge gap 5 of the gas discharge element is conducted, the second piezoresistor U2 is conducted, the voltage limiting is low due to the larger electrode surface, most of energy is absorbed by a second piezoresistor U2, the discharge gap width D3 is obtained by adjusting the thickness D1 of a conductive electrode sheet and the thickness difference D2 of a ceramic chip, the voltage-sensitive voltage of the second piezoresistor U2 can be made very low, so that the limiting voltage at two ends of the piezoresistor is very low, the first piezoresistor U1 and the series branch of the discharge gap 5 and the second piezoresistor U2 are in parallel connection, the residual voltage at two ends is determined by the second piezoresistor U2, the capacitance of the piezoresistor U1 is mainly determined by the first surge, the first piezoresistor U1 absorbs most of surge energy, and the surge energy is absorbed by the first piezoresistor U1 and the second piezoresistor U2 which are connected in parallel, but the second piezoresistor U2 absorbs main energy, so that the pressure-sensitive quick response and large surge impact are realized.

Example 7

The varistor manufacturing method of the present embodiment is used in the process of manufacturing a varistor.

The varistor manufacturing method, when manufacturing the varistor as in examples 4-6, uses the conventional manufacturing method, including arranging the electrode pins, and then uses the conventional varistor manufacturing process to perform the production, manufacturing, including the steps of cleaning, encapsulating, curing, marking, and measuring, thereby forming the single-port varistor composed of the pins.

Claims (15)

1. A ceramic chip comprising a third electrode surface, and a first electrode surface and a second electrode surface disposed on opposite sides of the third electrode surface, the second electrode surface and the first electrode surface being independent of each other;

the ceramic chip is provided with a groove, the groove is positioned on the opposite surface of the third electrode surface, the second electrode surface is arranged on the groove bottom of the groove, and the first electrode surface is arranged along the end surface of the ceramic chip, which is provided with the groove.

2. The ceramic chip of claim 1, wherein the first electrode face, the second electrode face, and the third electrode face are three parallel planes.

3. The ceramic chip of claim 1, wherein the projections of the first electrode surface and the second electrode surface on the third electrode surface are overlapped with the third electrode surface, and the first electrode surface and the second electrode surface are used for connecting a gas discharge element.

4. The ceramic chip of claim 1, wherein the ceramic chip is a cylinder, and the recess is a cylindrical hole formed at one end of the cylinder.

5. The ceramic chip of claim 1, wherein the ceramic chip is a pressure sensitive tile.

6. The ceramic chip of any one of claims 1 to 5, wherein the first electrode surface, the second electrode surface and the third electrode surface are conductive coatings coated on the ceramic chip.

7. A varistor comprising a ceramic chip according to any one of claims 1 to 6, the ceramic chip having a gas discharge element disposed between a first electrode surface and a second electrode surface, a first extraction electrode electrically connected to a third electrode surface, and a second extraction electrode electrically connected to either the first electrode surface or the second electrode surface.

8. The varistor of claim 7, wherein a conductive electrode pad is mounted on said first electrode surface, said conductive electrode pad having a gap with said second electrode surface, and said gas discharge element is a discharge gap formed between said conductive electrode pad and said second electrode surface.

9. The varistor of claim 8, wherein said conductive electrode pads are correspondingly provided with protrusions protruding into said recesses.

10. The varistor according to claim 9, wherein said protrusions are formed by protruding conductive electrode pieces with a protrusion height corresponding to a groove depth of said ceramic chip and forming discharge gaps.

11. A varistor according to claim 10, wherein the protrusions have a lower convex surface corresponding to the shape of the second electrode surface, said lower convex surface being equidistant from the second electrode surface.

12. The varistor of claim 8, wherein said second electrode surface of said ceramic chip is provided with a conductive sheet for adjusting the width of said discharge gap.

13. A varistor according to any of claims 8 to 12, wherein said conductive electrode sheet is sealingly connected to said first electrode surface such that the cavity of said discharge gap is a sealed cavity.

14. The varistor according to any of claims 7-12, wherein the varistor is coated with an insulating layer on the other surfaces except for the terminals of the first and second extraction electrodes.

15. A varistor according to any of claims 8 to 12, wherein said discharge gap has a width of between 0.05 and 0.5 mm.

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