CN109935523B - Semiconductor device package and method of manufacturing the same - Google Patents

Semiconductor device package and method of manufacturing the same Download PDF

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Publication number
CN109935523B
CN109935523B CN201810322315.6A CN201810322315A CN109935523B CN 109935523 B CN109935523 B CN 109935523B CN 201810322315 A CN201810322315 A CN 201810322315A CN 109935523 B CN109935523 B CN 109935523B
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substrate
conductive layer
semiconductor device
disposed
package
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CN201810322315.6A
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CN109935523A (en
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陈毅
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

A semiconductor device package includes a substrate, a first electronic component, a first package body, an electrical contact, and a first conductive layer. The substrate has a first surface, a second surface, and a lateral surface extending between the first surface and the second surface. The first electronic component is disposed on the first surface of the substrate. The first package encapsulates the first electronic component. The electrical contact is disposed on the second surface of the substrate. The first conductive layer includes a first portion and a second portion. The first portion is disposed on the lateral surfaces of the first package and the substrate. The second portion is in contact with the electrical contact.

Description

Semiconductor device package and method of manufacturing the same
Technical Field
The present disclosure relates generally to a semiconductor device package, and to a semiconductor device package in which a shield layer is directly connected to a ground terminal.
Background
In semiconductor device packaging, molding techniques may be used to encapsulate the semiconductor device to form a package for protection.
A shielding layer may be formed on the package body to reduce or mitigate electromagnetic interference (EMI). The shield layer may be electrically connected to a ground layer in the substrate for packaging or assembling the semiconductor device. Accordingly, the placement of the ground layer may increase the cost and size of the semiconductor device package.
Disclosure of Invention
In some embodiments, a semiconductor device package includes a substrate, a first electronic component, a first package body, an electrical contact, and a first conductive layer. The substrate has a first surface, a second surface, and a lateral surface extending between the first surface and the second surface. A first electronic component is disposed on the first surface of the substrate. The first package encapsulates the first electronic component. The electrical contact is disposed on the second surface of the substrate. The first conductive layer includes a first portion and a second portion. The first portion is disposed on lateral surfaces of the first package body and the substrate. The second portion is in contact with the electrical contact.
In some embodiments, a method of manufacturing a semiconductor device package includes the operations of: providing a substrate; disposing a package on a substrate; disposing an electrical contact on a substrate; and forming a conductive layer on the substrate and the package body to contact the electrical contacts.
Drawings
Fig. 1A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 1B illustrates a cross-sectional view of a portion of the semiconductor device package shown in fig. 1A, in accordance with some embodiments of the present disclosure.
Fig. 1C illustrates a bottom view of a portion of the semiconductor device package shown in fig. 1B.
Fig. 1D illustrates a cross-sectional view of a portion of the semiconductor device package shown in fig. 1A, in accordance with some embodiments of the present disclosure.
Fig. 1E illustrates a bottom view of the portion of the semiconductor device package shown in fig. 1D.
Fig. 2 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 3 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 4 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 5 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 6A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 6B illustrates a cross-sectional view of the portion of the semiconductor device package shown in fig. 6A, according to some embodiments of the present disclosure.
Fig. 6C illustrates a bottom view of the portion of the semiconductor device package shown in fig. 6B.
Fig. 7 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 8 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 9 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.
Fig. 10A, 10B, 10C, 10D, 10E, 10F, and 10G illustrate methods of manufacturing semiconductor device packages according to some embodiments of the present disclosure.
Fig. 11A, 11B, 11C, 11D, 11E, and 11F illustrate methods of manufacturing a semiconductor device package according to some embodiments of the present disclosure.
Fig. 12A, 12B, 12C, 12D, and 12E illustrate methods of manufacturing a semiconductor device package according to some embodiments of the present disclosure.
Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like elements. The present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.
Detailed Description
As used herein, relative terms such as "inner," "outer," "top," "bottom," "front," "rear," "upper," "upward," "lower," "downward," "vertical," "vertically," "lateral," "laterally," "above," and "below" refer to the orientation of a collection of components relative to one another; this orientation is in accordance with the drawings and is not the required orientation during manufacture or use.
In one or more embodiments, the conductive material forms a shield layer and may extend from the lateral surface of the substrate to external connection elements (e.g., solder balls/bumps) of the semiconductor device package by electroplating techniques (e.g., controlling the overflow of the conductive material) or sputtering techniques (e.g., dual-side/dual-side sputtering techniques).
Fig. 1A illustrates a cross-sectional view of a semiconductor device package 10, according to some embodiments of the present disclosure. The semiconductor device package 10 includes a substrate 11, an electronic component 121, a first package body 12, electrical contacts 13, and a first conductive layer 14. The substrate 11 has a first surface 111, a second surface 112, and a lateral surface 113 extending between the first surface 111 and the second surface 112. Electronic components 121 are disposed on the first surface 111 of the substrate 11. Electronic component 121 may include, for example, a die, a chip, an application specific integrated circuit, or a passive electronic device (e.g., a capacitor). The package body 12 encapsulates the electronic component 121. The electrical contacts 13 are disposed on the second surface 112 of the substrate 11. The first conductive layer 14 includes a first portion 141 and a second portion 142. The first portion 141 is disposed on the lateral surface 113 of the substrate 11 and the first package body 12. The second portion 142 is in contact with the electrical contact 13. In some embodiments, another electronic component 122 is disposed on the first surface 111 of the substrate 11. In some embodiments, the second portion 142 of the first conductive layer 14 is in contact with the second surface 112 of the substrate 11. In some embodiments, electronic components 123 are also disposed on the first surface 111 of the substrate 11. In some embodiments, one or more electrically conductive patterned layers are disposed within the substrate. In some embodiments, the semiconductor device package 10 further comprises a solder mask layer 115.
The solder mask layer 115 may be used to protect the second surface 112 of the substrate 11. In some embodiments, the solder mask layer 115 is (or includes) a photosensitive dry film or other patternable material, such as polyimide. In some embodiments, the solder mask layer 115 is (or includes) a solder resist. An opening is defined by the solder mask layer 115 to expose a portion of the second surface 112 of the substrate 11 for external electrical connection, and one or more of the electrical contacts 13 may be disposed in the opening. In some embodiments, second portion 142 of first conductive layer 14 is disposed in such an opening. Such openings may be any suitable shape, including (but not limited to): columnar (e.g., cylindrical, elliptical, square, rectangular, or other columnar shape) or non-columnar (e.g., conical, funnel, or other non-columnar shape). The sidewalls of the opening defined by the solder mask layer 115 may be arcuate in shape. The sidewalls of the opening defined by the solder mask layer 115 may be textured. In some embodiments, the solder mask layer 115 may constitute at least a portion of the second surface 112 of the substrate 11.
In some embodiments, the thickness of the first portion 141 is greater than the thickness of the second portion 142. In some embodiments, the thickness of first portion 141 is at least about three times greater than the thickness of second portion 142 (e.g., the thickness of first portion 141 is greater than the thickness of second portion 142 by a factor of about 4 or more, by a factor of about 5 or more, or by a factor of about 6 or more).
In some embodiments, the electrical contact 13 may be a solder bump, a metal pillar (e.g., a copper pillar or a pillar comprising another conductive metal or alloy), a conductive bump comprising a copper core surrounded by a solder shell (e.g., a shell comprising tin (Sn)), or a conductive bump comprising a higher melting temperature (melting point) solder core (e.g., comprising a higher melting temperature tin alloy) surrounded by a lower melting temperature solder shell (e.g., comprising a lower melting temperature tin alloy).
In some embodiments, the first conductive layer 14 acts as a shielding layer on the package body 12 to reduce or mitigate EMI, and may be electrically connected to a ground layer in the substrate 11. By directly connecting the second portion 142 of the first conductive layer 14 to the electrical contact 13, the cost of manufacturing the substrate 11 and the size of a semiconductor device package containing the substrate 11 may be reduced.
Fig. 1B illustrates a cross-sectional view of the portion of the semiconductor device package 10 shown in fig. 1A, according to some embodiments of the present disclosure. As shown in fig. 1B, the first portion 141 is disposed on the lateral surface 113 of the substrate 11. The electrical contact 13 is in electrical contact with the second portion 142 and may partially cover the second portion 142. In some embodiments, the electrical contact 13 covers a portion of the second portion 142. As shown in fig. 1B, second portion 142 does not directly contact ground pad 114 (which may be electrically connected to (or may constitute) a ground layer) within substrate 11. The ground pad 114 is electrically connected to the second portion 142 by the electrical contacts 13. In some embodiments, the second portion 142 directly contacts the ground pad 114 within the substrate 11.
Fig. 1C illustrates a bottom view of a portion of the semiconductor device package shown in fig. 1B. As shown in fig. 1C, the second portion 142 does not directly contact the ground pad 114 within the substrate 11.
Fig. 1D illustrates a cross-sectional view of a portion of the semiconductor device package shown in fig. 1A, in accordance with some embodiments of the present disclosure. As shown in fig. 1D, the first portion 141 is disposed on the lateral surface 113 of the substrate 11. The second portion 142 is in electrical contact with the electrical contact 13 by extending to and partially surrounding (or abutting) the electrical contact 13. In some embodiments, the second portion 142 includes a protrusion that covers a portion of the electrical contact 13 (shown in fig. 1E). As shown in fig. 1D, the second portion 142 does not directly contact the ground pad 114 within the substrate 11. The ground pad 114 is electrically connected to the second portion 142 by electrical contacts 13.
Fig. 1E illustrates a bottom view of the portion of the semiconductor device package shown in fig. 1D. As shown in fig. 1E, the second portion 142 partially surrounds the electrical contact 13 (e.g., includes one or more protrusions extending around at least a portion of the electrical contact 13, and covers 10% or more of the outer perimeter of the electrical contact 13, covers 20% or more of the outer perimeter, covers 30% or more of the outer perimeter, covers 40% or more of the outer perimeter, or more) and does not directly contact the ground pad 114 within the substrate 11. By applying the structure shown in fig. 1D and 1E, the contact area between the second portion 142 and the electrical contact 13 is increased so that the safety is also increased and the possibility of peeling between the second portion 142 and the electrical contact 13 is reduced.
Fig. 2 illustrates a cross-sectional view of a semiconductor device package 10, according to some embodiments of the present disclosure. The semiconductor device package shown in fig. 2 is similar to the semiconductor device package shown in fig. 1A, wherein the differences include that the first conductive element 15 is disposed in the first package body 12 and separates the electronic component 121 (and/or the electronic component 122) from the electronic component 123, or is disposed between the electronic component 121 (and/or the electronic component 122) and the electronic component 123. The electrically-conductive material of the first electrically-conductive element 15 forms an EMI compartment shield. The EMI compartment shield may help separate electronic components 121/122 and electronic component 123 and allow electronic components 121/122 and 123 to withstand lower EMI and have higher electromagnetic compatibility (EMC). In addition, this configuration provides different functions integrated into the package for electronic components 121/122 and 123 to reduce the number of elements in the package (e.g., by implementing the appropriate specific function) in order to reduce the size of the package.
The EMI compartment shield may be formed by injecting a conductive glue into a trench/groove extending from the top surface of the package to the bottom surface of the package. EMI compartment shields are provided in packages to protect devices or components from EMI as caused by other devices (e.g., radio frequency integrated circuits or other components operating at relatively higher frequencies).
Fig. 3 illustrates a cross-sectional view of a semiconductor device package 10, according to some embodiments of the present disclosure. The semiconductor device package 10 shown in fig. 3 is similar to the semiconductor device package shown in fig. 2, with the differences including the electronic component 161 and/or the electronic component 162 being disposed on the second surface 112 of the substrate 11. The second package body 17 encapsulates the second electronic component 161. A second conductive layer 18 is disposed on the second molding compound 17. The second conductive layer 18 is electrically connected to the electrical contact 13. In some embodiments, the second conductive layer 14 acts as a shielding layer on the package body 17 to reduce or mitigate EMI.
Fig. 4 illustrates a cross-sectional view of a semiconductor device package 10, according to some embodiments of the present disclosure. The semiconductor device package 10 shown in fig. 4 is similar to the semiconductor device package shown in fig. 3, wherein the differences include that the second conductive element 19 is disposed in the second package body 17 and separates the electronic component 161 and the electronic component 162 or is disposed between the electronic component 161 and the electronic component 162.
Fig. 5 illustrates a cross-sectional view of the semiconductor device package 10, in accordance with some embodiments of the present disclosure. The semiconductor device package 10 shown in fig. 5 is similar to the semiconductor device package shown in fig. 4, with the difference including the second portion 142 extending from the first portion 141 (e.g., the second portion 142 is integral with the first portion 141, or constitutes an integral structure including the first portion 141).
Fig. 6A illustrates a cross-sectional view of a semiconductor device package 10, according to some embodiments of the present disclosure. The semiconductor device package 10 shown in fig. 6A is similar to the semiconductor device package shown in fig. 1A, with the differences including the electronic components 261 and 262 being disposed on the second surface 112 of the substrate 11, and the second package body 27 encapsulating the electronic components 261 and 262 and the electrical contacts 23. The second package body 27 has a lateral surface 271 and a first surface 272. The electrical contacts 23 are exposed from (e.g., protrude from) the first surface 272 of the second molding compound 27.
In some embodiments, the first portion 241 of the first conductive layer 24 is disposed on the lateral surface 271 of the second molding compound 27. The second portion 242 of the first conductive layer 24 is disposed on the first surface 272 of the second molding compound 27. In some embodiments, the third electronic component 123 is disposed on the first surface 111 of the substrate 11.
Fig. 6B illustrates a cross-sectional view of the portion of the semiconductor device package shown in fig. 6A, according to some embodiments of the present disclosure. As shown in fig. 6B, the first portion 241 is disposed on the lateral surface 113 of the substrate 11. The second portion 242 is in electrical contact with the electrical contact 23 by extending to and partially surrounding the electrical contact 23. In some embodiments, the second portion 242 includes a protrusion that covers a portion of the electrical contact 23 (shown in fig. 6C). The ground pad 114 is electrically connected to the second portion 242 by electrical contacts 23.
Fig. 6C illustrates a bottom view of the portion of the semiconductor device package shown in fig. 6B. As shown in fig. 6C, the second portion 242 partially surrounds the electrical contact 23. In some embodiments, the second portion 242 includes a raised portion that covers at least a portion of the electrical contact 23 (e.g., includes one or more projections that extend around at least a portion of the electrical contact 23 and cover 10% or more of the outer perimeter of the electrical contact 23, cover 20% or more of the outer perimeter, cover 30% or more of the outer perimeter, cover 40% or more of the outer perimeter, or more).
Fig. 7 illustrates a cross-sectional view of the semiconductor device package 10, according to some embodiments of the present disclosure. The semiconductor device package 10 shown in fig. 7 is similar to the semiconductor device package shown in fig. 6A, wherein the differences include that the first conductive element 15 is disposed in the first package body 12, and separates the electronic components 121 and 122 and the electronic component 123, or is disposed between the electronic components 121 and 122 and the electronic component 123.
Fig. 8 illustrates a cross-sectional view of a semiconductor device package 10, according to some embodiments of the present disclosure. The semiconductor device package 10 shown in fig. 8 is similar to the semiconductor device package shown in fig. 7, with the difference including conductive elements 291 and 293 disposed in the second package body 27 and surrounding the electronic component 261. In some embodiments, conductive elements 291 and 293 enclose electronic component 261 and electronic component 262. In some embodiments, second conductive layer 28 is disposed on second package 27 and connected to conductive elements 291 and 293. In some embodiments, the conductive elements 291 and 293 are electrically connected to the electrical contacts 23.
Fig. 9 illustrates a cross-sectional view of a semiconductor device package 10, according to some embodiments of the present disclosure. The semiconductor device package 10 shown in fig. 9 is similar to the semiconductor device package shown in fig. 8, with the difference including the third conductive element 292 disposed in the second package body 27 and separating the electronic component 261 from the electronic component 262.
Fig. 10A, 10B, 10C, 10D, 10E, 10F, and 10G illustrate methods of manufacturing the semiconductor device package 10 according to some embodiments of the present disclosure.
Fig. 10A illustrates the provision of a substrate 11. The substrate 11 has a first surface 111, a second surface 112, and a lateral surface 113 extending between the first surface 111 and the second surface 112. Electronic components 121 are disposed on the first surface 111 of the substrate 11. In some embodiments, another electronic component 122 is disposed on the first surface 111 of the substrate 11. In some embodiments, electronic components 123 are also disposed on the first surface 111 of the substrate 11. In some embodiments, a solder mask layer 115 is disposed on the second surface 112 of the substrate.
Fig. 10B illustrates disposing a molding compound to form the package body 12 on the substrate 11. The package body 12 encapsulates the electronic components 121, 122, and 123.
Fig. 10C illustrates the formation of a conductive layer 14 on the lateral surface 113 of the substrate 11 and the package 12 shown in fig. 10B. The conductive layer 14 includes a first portion 141 and a second portion 142. The first portion 141 is disposed on the lateral surface 113 of the package body 12 and the substrate 11. The second portion 142 is disposed on the second surface 112 of the substrate 11.
Fig. 10D illustrates the placement of the electrical contacts 13 on the second surface 112 of the substrate 11 and the solder mask layer 115. In some embodiments, the electrical contacts 13 are disposed on the substrate 11 after the conductive layer 14 is formed on the substrate 11 and the package body 12. The second portion 142 of the conductive layer 14 is in contact with the electrical contact 13. In some embodiments, the structure shown in fig. 1B and 1C is subsequently formed. Although fig. 10A shows the opening in the solder mask layer 115 at an early stage of fabrication, the opening may be formed at any time prior to formation of the electrical contact 13.
Fig. 10E illustrates having a first portion 141 of conductive layer 14 formed on lateral surface 113 of substrate 11 and package 12 shown in fig. 10B. Fig. 10C differs from fig. 10E at least in that: second portion 142 of conductive layer 14 is formed at a different time than first portion 141 of conductive layer 14 (e.g., second portion 142 of conductive layer 14 is formed after first portion 141 of conductive layer 14 is formed).
Fig. 10F illustrates the placement of the electrical contact 13 on the second surface 112 of the substrate 11 and the solder mask layer 115 shown in fig. 10E.
Fig. 10G illustrates having a second portion 142 of the conductive layer 14 formed on the second surface 112 of the substrate 11 to contact the electrical contact 13. In some embodiments, the structures of fig. 1D and 1E are subsequently formed. In some embodiments, the method further comprises reflowing the electrical contact 13. The semiconductor device package 10 of fig. 10G corresponds to the semiconductor device package shown in fig. 1A.
Fig. 11A, 11B, 11C, 11D, 11E, and 11F illustrate methods of manufacturing a semiconductor device package according to some embodiments of the present disclosure.
Fig. 11A illustrates providing a substrate 11. The substrate 11 has a first surface 111, a second surface 112, and a lateral surface 113 extending between the first surface 111 and the second surface 112. Electronic components 121 are disposed on the first surface 111 of the substrate 11. In some embodiments, another electronic component 122 is disposed on the first surface 111 of the substrate 11. In some embodiments, electronic components 123 are also disposed on the first surface 111 of the substrate 11. Electronic components 161 and/or electronic components 162 are disposed on second surface 112 of substrate 11. A solder mask layer 115 is disposed on the second surface 112 of the substrate.
Fig. 11B illustrates disposing a first portion of the molding compound to form the first package 12 on the first surface 111 of the substrate 11 and disposing a second portion of the molding compound to form the second package 17 on the second surface 112 of the substrate 11. In some embodiments, the first package body 12 encapsulates the electronic components 121, 122, and 123. The second package body 17 encapsulates the electronic components 161 and 162. In some embodiments, the first conductive element 15 is disposed in the first package body 12 and separates the electronic components 121 and 122 from the electronic component 123. The second conductive element 19 is disposed in the second package body 17 and separates the electronic component 161 from the electronic component 162.
Fig. 11C illustrates the formation of a conductive layer 14 on the lateral surface 113 of the substrate 11 and the first package body 12 shown in fig. 11B. The conductive layer 14 includes a first portion 141 and a second portion 142. The first portion 141 is disposed on the lateral surface 113 of the substrate 11 and the first package body 12. The second portion 142 is disposed on the second surface 112 of the substrate 11.
Fig. 11D illustrates the conductive layer 18 being formed on the second package body 17. The electrical contacts 13 may be disposed on the second surface 112 of the substrate 11 before or after forming the conductive layer 18. The second portion 142 of the conductive layer 14 is in contact with the electrical contact 13. In some embodiments, the structures shown in fig. 1B and 1C are subsequently formed. Finally, the semiconductor device package shown in fig. 5 is formed.
Fig. 11E illustrates having a first portion 141 of the conductive layer 14 formed on the lateral surface 113 of the substrate 11 and the first package body 12 shown in fig. 11B. Fig. 11C and 11E differ in that: second portion 142 of conductive layer 14 is formed at a different time than first portion 141 of conductive layer 14 (e.g., second portion 142 of conductive layer 14 is formed after first portion 141 of conductive layer 14 is formed).
Fig. 11F illustrates forming the conductive layer 18 on the second package 17 and forming the second portion 142 of the conductive layer 14 on the second surface 112 of the substrate 11. The electrical contacts 13 may be disposed on the second surface 112 of the substrate 11 before or after forming the conductive layer 18. The second portion 142 of the conductive layer 14 is in contact with the electrical contact 13. In some embodiments, the structures shown in fig. 1D and 1E are subsequently formed. Finally, the semiconductor device package shown in fig. 4 is formed. Although fig. 11A shows the opening in the solder mask layer 115 at an earlier stage of fabrication, the opening may be formed at any time prior to the formation of the electrical contact 13.
Fig. 12A, 12B, 12C, 12D, and 12E illustrate methods of manufacturing a semiconductor device package according to some embodiments of the present disclosure.
Fig. 12A illustrates providing a substrate 11. The substrate 11 has a first surface 111, a second surface 112, and a lateral surface 113 extending between the first surface 111 and the second surface 112. Electronic components 121 are disposed on the first surface 111 of the substrate 11. In some embodiments, another electronic component 122 is disposed on the first surface 111 of the substrate 11. In some embodiments, electronic components 123 are also disposed on the first surface 111 of the substrate 11. Electronic component 261 and/or electronic component 262 are disposed on second surface 112 of substrate 11. A solder mask layer 115 is disposed on the second surface 112 of the substrate 11. The electrical contacts 23 are disposed on the second surface 112 of the substrate 11 and the solder mask layer 115.
Fig. 12B illustrates disposing a first portion of the molding compound such that the first package body 12 is formed on the first surface 111 of the substrate 11. Fig. 12B also illustrates disposing a second portion of the molding compound such that a second package body 27 is formed on the second surface 112 of the substrate 11. In some embodiments, the first package body 12 encapsulates the electronic components 121, 122, and 123. The second package 27 encapsulates the electronic components 261 and 262 and the electrical contacts 23 and exposes portions of the electrical contacts 23.
Fig. 12C illustrates the formation of a conductive layer 24 on the lateral surface 113 of the substrate 11, the first package body 12, and the lateral surface 271 of the second package body 27 shown in fig. 12B. The conductive layer 24 includes a first portion 241 and a second portion 242. The first portion 241 is disposed on the first package body 12, the lateral surface 113 of the substrate 11, and the lateral surface 271 of the second package body 27. The second portion 242 is disposed on the second package body 27 to contact the electrical contact 23.
Fig. 12D illustrates the formation of a first portion 241 of the conductive layer 24 on the lateral surface 113 of the substrate 11, the first package 12, and the lateral surface 271 of the second package 27 shown in fig. 12B. Fig. 12C and 12D differ in that: the second portion 242 of the conductive layer 24 is formed at a different time than the first portion 241 of the conductive layer 24 (e.g., the second portion 242 of the conductive layer 24 is formed after the first portion 241 of the conductive layer 24 is formed).
Fig. 12E illustrates having a second portion 242 of conductive layer 24 formed over second package 27. The second portion 242 of the conductive layer 24 is in contact with the electrical contact 23. In some embodiments, the structure shown in fig. 6B and 6C is subsequently formed. Finally, the semiconductor device package shown in fig. 6A is formed.
The semiconductor device packages illustrated in fig. 7, 8, and 9 may be formed by a method similar to the method of manufacturing the semiconductor device packages illustrated in fig. 12A, 12B, 12C, 12D, and 12E.
As used herein, the singular terms "a" and "the" can include plural referents unless the context clearly dictates otherwise.
As used herein, the term "connected" refers to an operative coupling or link. The connection components may be directly or indirectly coupled to each other, such as through another collection of components.
As used herein, the terms "conductive", "electrically conductive", and "conductivity" refer to the ability to pass an electrical current. Conductive materials generally indicate those materials that exhibit little or zero resistance to current flow. One measure of conductivity is siemens per meter (S/m). Typically, the conductive material is a material having a conductivity greater than about 10 4 S/m (e.g., at least 10) 5 S/m or at least 10 6 S/m) of electrical conductivity. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of the material was measured at room temperature.
As used herein, the terms "about," "substantially," "generally," and "about" refer to a substantial degree. When used in conjunction with an event or circumstance, the terms can refer to the exact occurrence of the event or circumstance, as well as the occurrence of the event or circumstance in close proximity, such as when interpreting typical tolerance levels for the manufacturing methods described herein. For example, when used in conjunction with numerical values, the terms can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are "substantially" identical or equal if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include both the values explicitly recited as the limits of the range, and to include all the individual values or sub-ranges encompassed within that range as if each value and sub-range is explicitly recited.
In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the preceding component is directly on (e.g., in physical contact with) the succeeding component, as well as the case where one or more intervening components are located between the preceding and succeeding components.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims.
The construction and arrangement of the structures and methods as shown in the various example embodiments are illustrative only. Accordingly, all such modifications are intended to be included within the scope of this disclosure. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the example embodiments without departing from the scope of the present disclosure.

Claims (23)

1. A semiconductor device package, comprising:
a substrate having a first surface, a second surface, and a lateral surface extending between the first surface and the second surface;
a first electronic component disposed on the first surface of the substrate;
a first package encapsulating the first electronic component;
an electrical contact disposed on the second surface of the substrate; and
a first conductive layer comprising:
a first portion disposed on the lateral surfaces of the first package and the substrate, and
a second portion in contact with the electrical contact, wherein the second portion comprises a protrusion that partially surrounds an outer perimeter of the electrical contact.
2. The semiconductor device package of claim 1, wherein the second portion of the first conductive layer is in contact with the second surface of the substrate.
3. The semiconductor device package of claim 2, further comprising:
a second electronic component disposed on the first surface of the substrate;
a first conductive element disposed in the first package body and separating the first electronic component from the second electronic component.
4. The semiconductor device package of claim 1, further comprising:
a ground pad disposed within the substrate;
a second electronic component disposed on the second surface of the substrate;
a second package encapsulating the second electronic component; and
a second conductive layer disposed on the second package body, and the second conductive layer electrically connected to the second portion of the first conductive layer through the ground pad.
5. The semiconductor device package of claim 4, further comprising:
a third electronic component disposed on the second surface of the substrate; and
a second conductive element disposed in the second package body and separating the second electronic component from the third electronic component.
6. The semiconductor device package of claim 1, wherein a lower surface of the first portion of the first conductive layer is exposed through the second portion.
7. The semiconductor device package of claim 1, further comprising: a ground pad disposed within the substrate, wherein a portion of the ground pad is uncovered by the electrical contacts in a bottom view of the semiconductor device package.
8. The semiconductor device package of claim 1, wherein the second portion of the first conductive layer is integral with the first portion of the first conductive layer.
9. The semiconductor device package of claim 8, wherein a thickness of the first portion of the first conductive layer is greater than a thickness of the second portion of the first conductive layer.
10. The semiconductor device package of claim 7, wherein the first conductive layer is spaced apart from the ground pad, and the first conductive layer electrically connects the first conductive layer through the electrical contacts.
11. The semiconductor device package of claim 1, further comprising:
a second electronic component disposed on the second surface of the substrate; and
a second package encapsulating the second electronic component and the electrical contacts, the second package having a lateral surface and a first surface, wherein the electrical contacts are exposed from the first surface of the second package;
wherein the first portion of the first conductive layer is disposed on the lateral surface of the second package body;
wherein the second portion of the first conductive layer is disposed on the first surface of the second package body.
12. The semiconductor device package of claim 11, further comprising:
a third electronic component disposed on the first surface of the substrate;
a first conductive element disposed in the first package body and separating the first electronic component from the third electronic component.
13. The semiconductor device package of claim 12, further comprising:
a second conductive element disposed in the second package body and surrounding the second electronic component; and
a second conductive layer disposed on the second package body and connected to the second conductive element,
wherein the second electrically conductive element is electrically connected to the electrical contact.
14. The semiconductor device package of claim 13, further comprising:
a fourth electronic component disposed on the second surface of the substrate; and
a third conductive element disposed in the second package body and separating the second electronic component from the fourth electronic component.
15. The semiconductor device package of claim 1, further comprising:
a solder shield layer having a lateral surface, the electrical contact contacting the lateral surface of the solder shield layer.
16. The semiconductor device package of claim 1, wherein the second portion of the first conductive layer has a first width at contacting the first portion and a second width at contacting the electrical connection, the first width being different than the second width.
17. The semiconductor device package of claim 16, the first width being less than the second width.
18. The semiconductor device package of claim 1, further comprising:
a ground pad disposed within the substrate,
wherein the second portion of the first conductive layer is disposed on the first surface of the substrate and defines a gap with the ground pad in a bottom view of the semiconductor device package, a projection of the gap on the substrate being surrounded by a projection of the electrical contact on the substrate.
19. The semiconductor device package of claim 4, wherein the second conductive layer further electrically connects the second portion of the first conductive layer through the electrical contacts.
20. A method of fabricating a semiconductor device package, comprising:
providing a substrate;
disposing a first package on an upper surface of the substrate;
forming a first conductive layer on the substrate and the first package body, wherein the first conductive layer includes a first portion formed on a lateral surface of the substrate and a second portion formed on a lower surface of the substrate; and
after forming the first conductive layer, forming electrical contacts on the lower surface of the substrate such that the electrical contacts cover the second portion of the first conductive layer.
21. The method of claim 20, further comprising:
forming an electronic component on the lower surface of the substrate before forming the first conductive layer; and
and forming a second packaging body to cover the electronic component.
22. The method of claim 20, further comprising:
forming a second conductive layer on the second package body, wherein the second conductive layer is electrically connected to the first conductive layer through a ground pad of the substrate.
23. The method of claim 22, wherein the electrical contact is brought into contact with the ground pad of the substrate and the second conductive layer is electrically connected to the electrical contact through the ground pad while the electrical contact is caused to cover the second portion of the first conductive layer.
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