CN109933529A - Verification method and verification platform based on computing unit - Google Patents
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Abstract
The present invention relates to electronic technology fields, and in particular to a kind of verification method and verification platform based on computing unit, wherein method includes: to obtain instruction to be verified；According to the instruction to be verified, sequence of opcodes, operation Number Sequence and the register series in virtual sequence library are called, with building verifying excitation；The verifying is captured using monitor to motivate, and the verifying is motivated and is sent into reference model；It is compared and checked using export structure of the scoring board to computing unit processing result and the reference model that the monitor is collected, to be verified result.By being called to sequence of opcodes, operation Number Sequence and the register series in virtual sequence library, complicated sequence is carried out division combination, improves the verification efficiency of the method to be verified.
Description
Technical field
The present invention relates to electronic technology fields, and in particular to a kind of verification method and verification platform based on computing unit.
Background technique
UVM is a verification platform Development Framework based on SystemVerilog class libraries, verifies engineer and utilizes it
Reusable Module can construct the functional verification environment with standardization hierarchical structure and interface.UVM verification methodology is effectively tied
Closed test and excitation generate at random, test platform and randomization constraint the methods of, it uses best frame to realize coverage rate
The verifying of driving reduces verifying engineer by risk by using high level of authentication technology.
In processor design, numerous corresponding computing units can be designed according to its instruction set, such as simple fixed/floating-point
Computing unit, data displacement unit, fixed/floating-point converting unit, division/squareroot unit, is estimated complicated fixed/floating point calculating unit
The various computing units such as value cell, encryption/decryption element；The operand types of all kinds of computations, initial state register configuration,
The scenes such as immediate, register type to be feedback, abnormal conditions and result checking method are different；Existing conventional authentication
Method is to build respective verification environment by all kinds of computing units, and verification method is different, is unfavorable for being managed collectively, simultaneously
Influence verification efficiency.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of verification method and verification platform based on computing unit, to improve
The verification efficiency of verification method, the versatility for promoting verification platform.
According in a first aspect, the embodiment of the present invention provides a kind of verification method based on computing unit, comprising:
Obtain instruction to be verified；
According to the instruction to be verified, to sequence of opcodes, operation Number Sequence and the register sequence in virtual sequence library
Column are called, with building verifying excitation；
The verifying is captured using monitor to motivate, and the verifying is motivated and is sent into reference model；
Utilize the output knot of computing unit processing result and the reference model that scoring board collects the monitor
Structure is compared and checked, to be verified result.
Verification method provided by the invention based on computing unit, by the sequence of opcodes in virtual sequence library, behaviour
Make Number Sequence and register series are called, complicated sequence is carried out division combination, improves the method to be verified
Verification efficiency.
With reference to first aspect, described according to the instruction to be verified in the embodiment of first aspect, to operation code sequence
Column, operation Number Sequence and register series are combined calling, with building verifying excitation, comprising:
Function scene composition is carried out to virtual sequence library based on the instruction to be verified；Wherein, the virtual sequence library packet
Include the sequence of the computing unit corresponding at least two types；
Determined in the virtual sequence library using test case library the sequence of opcodes, the operation Number Sequence and
The calling of the register series, to obtain the verifying excitation corresponding to the instruction to be verified.
Verification method provided by the invention based on computing unit, when handling the sequence of computing unit of polymorphic type, benefit
Pass through test case library after carrying out scene composition with instruction to be verified and sequence of opcodes, operation Number Sequence and register series
Verifying excitation is extracted to the virtual sequence executed needed for wherein, by being verified to different types of computing unit, is made described
Verification method there is the versatility for handling a variety of different type computing units.
First embodiment with reference to first aspect, in the second embodiment of first aspect, one kind being based on computing unit
Verification method, further includes:
Function scenario building parameter is obtained, the function scenario building parameter includes order number, operand type and a
Number；
It is wherein, described that function scene composition is carried out to virtual sequence library based on the instruction to be verified, comprising:
Using described instruction number, orientation chooses specific instruction sequence from instruction operation code sequence library；
Random operation number is chosen using the operand and number；
It is determined from register series library using the macrodefinition to be verified for instructing corresponding computing unit specific defeated
Enter register；
The function is constructed using the specific instruction sequence, the random operation number and the specific input register
It can scene.
Verification method provided by the invention based on computing unit divides instruction to be verified by constructing function scene
It picks, improves the execution efficiency of the verification method；Different type computing unit is divided, specified execute needed for sequential extraction procedures is found
The mode for verifying excitation, solves the problems, such as the versatility of the verification method.
Second embodiment with reference to first aspect, in the 3rd embodiment of first aspect, the method, further includes:
Obtain specified operand, immediate and register value；Utilize described instruction operand, the immediate and the register value
Construct the function scene.
Verification method provided by the invention based on computing unit, by specifying operand, immediate and register value, into
Row operation, improves the verification efficiency of the verification method.
With reference to first aspect, in the fourth embodiment of first aspect, the method, according to the instruction to be verified,
Sequence of opcodes, operation Number Sequence and register series are called, before the step of building verifying excitation, are also wrapped
It includes: the parameter in the instruction to be verified being constrained, the parameter includes operand.
Verification method provided by the invention based on computing unit, by constraining the parameter in verifying instruction, with
Improve the verification efficiency of the verification method.
With reference to first aspect, in the 5th embodiment of first aspect, the reference model is realized using C language.
According to second aspect, the present invention provides a kind of verifying device based on computing unit, comprising:
Module is obtained, for obtaining instruction to be verified；
Module is constructed, is used for according to the instruction to be verified, to the sequence of opcodes in virtual sequence library, operation Number Sequence
And register series are called, with building verifying excitation；
Trapping module captures the verifying using monitor and motivates, and the verifying is motivated and is sent into reference model；
Comparison module, the computing unit processing result that the monitor is collected using scoring board and the reference model
Export structure be compared and checked, to be verified result.
Verifying device provided by the invention based on computing unit, the testing based on computing unit built using the module
Card device can improve the verification efficiency of verification method, realize the versatility of a variety of computing units of processing of verification method.
According to the third aspect, the present invention provides a kind of verification platform, comprising: memory and processor, the memory and
Connection is communicated with each other between the processor, computer instruction is stored in the memory, the processor is by executing institute
Computer instruction is stated, thereby executing the verification method of any of claims 1-7 based on computing unit.
According to fourth aspect, the present invention provides a kind of verifying device based on computing unit, comprising: described computer-readable
Storage medium is stored with computer instruction, and the computer instruction is for making the computer execute any institute in embodiment
The verification method based on computing unit stated.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow chart of the verification method provided in an embodiment of the present invention based on computing unit；
Fig. 2 is that the acquisition of random number verification provided in an embodiment of the present invention motivates flow chart；
Fig. 3 is that virtual sequence library provided in an embodiment of the present invention constructs scene flow chart；
Fig. 4 is the structure chart of the verification platform provided in an embodiment of the present invention based on computing unit；
Fig. 5 is a kind of verification platform schematic diagram provided in an embodiment of the present invention.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In addition, the verification method and verification platform provided in an embodiment of the present invention based on computing unit, to be tested by obtaining
Card instruction, is sent into virtual sequence library, is called by the combination to setting parameter, computing unit scene is constructed, from computing unit
Verifying excitation needed for extracting is sent into monitoring model and reference model by two models of comparison, is verified result；Verification method,
It is called using the combination to setting parameter and carries out scenario building, from verifying excitation needed for extraction in scene is executed, make verifying calculating
The execution efficiency of unit is promoted, by handled on a verification platform different computing units realize verifying method it is general
Property.Technical characteristic involved in invention described below different embodiments as long as they do not conflict with each other can
To be combined with each other.
Implementation column of the present invention provides a kind of verification method based on computing unit, as shown in Figure 1, this method comprises:
S1 obtains instruction 21 to be verified；
S2 Number Sequence 23 and posts the sequence of opcodes 22 in virtual sequence library 26, operation according to instruction 21 to be verified
Storage sequence 24 is called, with building verifying excitation 28；
S3 captures verifying excitation 28 using monitor, and reference model is sent into verifying excitation 28；
S4 is carried out using export structure of the scoring board to computing unit processing result and reference model that monitor is collected
Compare verification, to be verified result.
Specifically, a kind of verification method based on computing unit；It is carried out in conjunction with UVM verification platform and Fig. 1 as described below；
S1 obtains instruction 21 to be verified；Verifying instruction processor design in, according to its instruction set can design it is numerous therewith
Corresponding computing unit, such as: simply fixed/floating point calculating unit, data displacement unit, is determined complicated fixed/floating point calculating unit/are floating
The various computing units such as point converting unit, division/squareroot unit, evaluation block, encryption/decryption element.
S2 Number Sequence 23 and posts the sequence of opcodes 22 in virtual sequence library 26, operation according to instruction 21 to be verified
Storage sequence 24 is called, with building verifying excitation 28；Virtual sequence library 28 integrates a variety of sequences, can be divided into operation code, behaviour
It counts and register three classes；Operation code can be the Unified coding of all instructions in instruction set, and operand can be instruction
Logical operation or data required for controlling, register can be system initial state when instruction works, utilize 3 classes
The signal that sequence is called output can be verifying excitation 28.
S3 captures verifying excitation 28 using monitor, and reference model is sent into verifying excitation 28；The verifying of output motivates
28 are sent into monitor, are captured and be sent to reference model by verifying excitation 28 of the monitor to input, reference model can
To be C language or other write language.
The export structure of S4, the processing result of the computing unit that monitor is collected using scoring board and reference model into
Row is relatively checked, to be verified result；Scoring board can be comparator, the processing knot for the computing unit collected from monitor
The result information obtained in fruit and reference model is sent into scoring board and is checked, and comparison result is exported.
By the verification method using computing unit, different computing units is handled, to the parameter of construction scene
It is combined, therefrom extracts the verifying excitation 18 of needs in the unit sequence for extracting needs from scene, pass through monitor and ginseng
Model is examined, output result is compared, it is ensured that it is single to can be improved calculating using the verification method for the versatility of computing unit
The verification efficiency of member, can count coverage rate using scoring board.
Implementation column of the present invention provides a kind of verification method based on computing unit, as shown in Fig. 2, according to instruction to be verified
21, calling is combined to sequence of opcodes 22, operation Number Sequence 23 and register series 24, motivates 28 with building verifying,
Include:
Function scene composition is carried out to virtual sequence library 26 based on instruction to be verified；Wherein, virtual sequence library 26 includes pair
It should be in the sequence of the computing unit of at least two types；
Sequence of opcodes 22, operation Number Sequence 23 and deposit are determined in virtual sequence library 26 using test case library 25
The calling of device sequence 24, to obtain the verifying excitation corresponding to instruction to be verified.
In the implementation method, virtual sequence library 26 provides specific eligible according to operand type, instruction type
Random operation number, immediate, carry equal excitation；
Sequence of opcodes 22, according to order number, operand type, operand number, computing unit interface other control
Signal issues activation sequence；The instruction operation code sequence of each computing unit is different, can use the overloading mechanics of generic validation method
To correspond to；
Number Sequence 23 is operated, the register configuration that certain computing functions need is provided；The register configuration of each computing unit
Difference can be corresponded to the overloading mechanics of generic validation method；
Register series 24 provide specific qualified random operation number according to operand type, instruction type, stand
That is number, carry equal excitation；
Building verifying excitation 28, needs to realize by virtual sequence library 26, will according to the respective function scene of computing unit
Sequence of opcodes 22, register series 24, certain sequences are combined into a set of virtual sequence library 26 in operation Number Sequence 23, and refer to
It is fixed to be issued by specific virtual sequence 27, complete traffic control, output verifying excitation 28.
It is combined by instruction 28 to be verified, finds the sequence of corresponding computing unit in virtual sequence library 26, need
By test case library 25 as guiding, corresponding virtual sequence 27 is found in virtual sequence library 26, is passing through virtual sequence
Verifying excitation 28 needed for 27 buildings.Required verifying can be quickly found out using scenario building of the corresponded manner to authentication unit to motivate
28, improve the execution efficiency of verification method.
With XS_unit, fixed point calculation unit, for:
1, order line or script are passed to computing unit (macrodefinition), test case name, the order number, operand type
And number and instruction issue number；
2, verification platform is according to the computing unit macrodefinition conditional compilation computing unit part；
3, verification platform runs nominative testing use-case according to test case name from test case library；Test case library, can be with
Including such as simple fixed/floating point calculating unit, complicated fixed/floating point calculating unit, data displacement unit, fixed/floating-point converting unit,
The respective test case library of division/squareroot unit, evaluation block, encryption/decryption element.
4, verification platform orients from instruction operation code sequence library according to order number and chooses concrete operations sequence；
5, verification platform chooses specific excitation according to computing unit macrodefinition；
6, verification platform chooses random behaviour's excitation according to operand type and number；
7, verification platform issues a whole set of incentive combination of corresponding number according to instruction issue number；
8, it is then driven by respective env onto the interface of dut, while corresponding monitor captures driven interface signal,
Pass to reference model interface；
9, the output result of verified dut and reference model is sent to scoring board, completes corresponding computing unit macrodefinition branch
Under result compare and coverage rate statistics.
Above-mentioned citing belongs to random data verification method, and data verification method provided by the present embodiment removes random data
The method that can also be directional data verifying outside verification method, process for using and the difference of random data verification method are order
Specified operand, immediate and register value, the method and steps handled in addition to this is passed in capable or script to test with random data
Card method is identical.
Specific embodiment, further includes: obtain function scenario building parameter, function scenario building parameter includes that instruction is compiled
Number, operand type and number；Function scenario building parameter, needs to be arranged order number, operand type, number.Instruction is compiled
It number can be the scene environment for being packaged completion, be also possible to a multiple instructions set；Operand type can be address, number
Word, character etc..
For computing unit in certain processor architecture, there are many input, can be classified as 3 major class, operation code, operand is posted
Storage is motivated by reasonable combination 3, can complete the construction to the function scene of computing unit.
Such as: certain fixed point vector addition instructs 1:iop+operandA (the vector integer data of 4Word)+operandB
(the vector integer data of 4Word)+reg (such as VSCR)
Certain floating point multiplication addition instruction 2:iop+operandA (single precision floating datum)+operandB (single precision floating datum)+
OperandC (single precision floating datum)+reg (such as FPSCR)
As shown in figure 3, instruction to be verified carries out function scene composition to virtual sequence library 26, need to pass through: S31 to utilize
Order number is oriented from instruction operation code sequence library chooses specific instruction sequence；S32 is chosen random using operand and number
Operand；S33 is determined from register series library specific defeated using the macrodefinition of 11 corresponding computing units of instruction to be verified
Enter register；S34 is carried out using specific instruction sequence, random operation number and specific input register constructing function scene
Combined sequence obtains, and a combination thereof mode can be random or orientation, is determined by selected execution data.In addition it is also possible to
By obtaining specified operand, immediate and register value；Utilize instruction operands, immediate and register value constructing function
Scene.
A kind of verification method based on computing unit is additionally provided in the present embodiment, it can also be in instruction 11 to be verified
Parameter constrained, parameter includes operand, and restriction on the parameters is that mainly to the composition of 128bit vector data, (data type multiplies
With data amount check), floating-point single precision/double precision (sp32, sp64, dp64), symbol integer (int8, int16, int32,
Int64), unsigned int (uint8, uint16, uint32, uint64, uint128 (vector class or crack class calculate)) etc.
The constraint of Various types of data type defined in instruction set；Floating-point values are such as: positive/negative infinite, positive/negative normalized number according to, it is positive/negative non-
Normalized number evidence, zero these probability distribution constraints；Parameter is carried out to constrain the versatility having using verification method, Yi Jican
Compatibility between several and parameter guarantees that the uniqueness of institute's setting parameter is logical, can prevent from believing in extracting parameter by restriction on the parameters
It repeats to extract when breath, improves the execution efficiency of verification method.
A kind of verification method based on computing unit is additionally provided in the present embodiment, needs to refer to model and finger to be verified
It enables 11 corresponding computing units correspond, is guaranteed in executing verification process with this, the correctness of verify data, joined by allowing
The uniformity of the verification method in executing verification process can be guaranteed with 11 corresponding computing units of instruction to be verified by examining model.
A kind of verification method based on computing unit is additionally provided in the present embodiment, and reference model can be used: C language
It realizes；C language may include the data verification type of the overwhelming majority, and compatibility is strong, to meet the versatility of verifying computing unit.
Specifically, the verification method based on computing unit further include: monitor, it is main to complete to export result to computing unit
Capture, also to be sent into computing unit verifying excitation capture, be sent into reference model；
Reference model, by DPI Interface integration, input operation code from capture and interface control signal, capture it is defeated
Enter register, the operand of capture and immediate；After reference model completes instruction calculating, calculated result and destination register are exported
Value；The model of each computing unit is different, can be corresponded to by the overloading mechanics of generic validation method.
Scoring board, complete the output result of reference model, the output result of register and computing unit, register ratio
Right and coverage rate statistics；There is following covering point:
(1) instruction operation code value covers, and counts whether each item instruction all covers, and has specific value；
(2) register value covers, and has specific value；
(3) immediate value covers, and has specific value；
(4) operand value covers, and has symbol integer, unsigned int, single precision floating datum, double-precision floating points, because
It is very wide for operand value range, statistical method is covered using section here, if any operand in the section covers,
Then indicate that the section number field covers；By the accurate division in section, can assurance function verifying when numerical value value range arrive,
Also it can accelerate the convergence of whole coverage rate；Such as the covering in the covering section, double-precision floating point operand of single-precision floating point operand
Section, 64 bit sign integer operands cover section.
Wherein, sequence of opcodes 12, operation Number Sequence 13 and register series 14 are completed respective operations and are motivated.
A kind of verifying device based on computing unit is additionally provided in the present embodiment, and the device is for realizing above-mentioned implementation
Example and preferred embodiment, the descriptions that have already been made will not be repeated.As used below, term " module " may be implemented pre-
Determine the combination of the software and/or hardware of function.Although device described in following embodiment is preferably realized with software,
The realization of the combination of hardware or software and hardware is also that may and be contemplated.
The present embodiment provides a kind of verifying device based on computing unit, as shown in Figure 4, comprising: obtain module 40, building
Module 41, trapping module 42, comparison module 43；Verifying instruction 21 is obtained using module 40 is obtained, by the void for constructing module 41
Sequence of opcodes 22, operation Number Sequence 23 and register series 24 are called in quasi- sequence library 26, with building verifying excitation
28；Trapping module 42 carries out capture to the verifying excitation 28 completed and is sent into reference model, and comparison module 43 utilizes reference model
And monitor carries out data comparison, exporting verification result by the verifying device based on computing unit ensure that the system of signal
One property simplifies complicated verification process using the connection type between module and module, is conducive to promote verification efficiency.
In the present embodiment based on the verifying device of computing unit presented in the form of functional unit, unit here
Refer to ASIC circuit, execute one or more softwares or fixed routine processor and memory and/or other can provide
State the device of function.
The further function description of above-mentioned modules is identical as above-mentioned corresponding embodiment, and details are not described herein.
A kind of verification platform is additionally provided in the present embodiment, verification platform is by constraining operand, instruction behaviour
Make to carry out function scene composition to the virtual library sequence in this 3 class of code, source operand, input register excitation library sequence
(different computing units correspond to different function scene compositions here, are controlled by macrodefinition), then utilizes virtual sequence machine
System carries out the scheduling to sequencer in instruction operation code, source operand, this 3 class of input register ENV, from 3 env (rings
Border) in driving excitation is carried out to computing unit；The corresponding excitation of respective monitor capture of 3 env simultaneously, is sent into C and refers to mould
Type.Then by des_env) in monitor complete the capture that export to computing unit, capture the defeated of result and C reference model
Result is completed to compare verification in scoreboard out.
In addition, a kind of verification platform for proposing of the present embodiment can by being instructed, the intersection of register, operand covers
Lid is counted, different according to the result comparison method of each computing unit, coverage rate information, can use the heavy duty of uvm
Override mechanism corresponds to；
There is component sim_top, testcase_lib in the top layer of verification platform.Sim_top completes uvm component and calculating
Integrating for unit, can specify which class computing unit and component according to macrodefinition or command line parameter；Testcase_lib is complete
At test case classification, the corresponding env component of computing unit type is instantiated, specifies computing unit type corresponding virtual
Sequence combination；
A kind of verification platform as shown in Figure 5.
Referring to Fig. 5, Fig. 5 is a kind of verification platform schematic diagram that alternative embodiment of the present invention provides, as shown in figure 5, one
Kind verification platform may include: at least one processor 51, such as CPU (Central Processing Unit, central processing
Device), at least one communication interface 53, memory 54, at least one communication bus 52.Wherein, communication bus 52 is for realizing this
Connection communication between a little components.Wherein, communication interface 53 may include display screen (Display), keyboard (Keyboard), can
Selecting communication interface 53 can also include standard wireline interface and wireless interface.Memory 54 can be high speed RAM memory
(Random Access Memory, effumability random access memory), is also possible to non-labile memory (non-
Volatile memory), a for example, at least magnetic disk storage.It is remote that memory 54 optionally can also be that at least one is located at
Storage device from aforementioned processor 51.Wherein processor 51 can be stored in memory 54 and be answered with device described in conjunction with Figure 4
With program, and processor 51 calls the program code stored in memory 54, for executing any of the above-described method and step.
Wherein, communication bus 52 can be Peripheral Component Interconnect standard (peripheral component
Interconnect, abbreviation PCI) bus or expanding the industrial standard structure (extended industry standard
Architecture, abbreviation EISA) bus etc..Communication bus 52 can be divided into address bus, data/address bus, control bus etc..
Only to be indicated with a thick line in Fig. 5, it is not intended that an only bus or a type of bus convenient for indicating.
Wherein, memory 54 may include volatile memory (English: volatile memory), such as arbitrary access
Memory (English: random-access memory, abbreviation: RAM)；Memory also may include nonvolatile memory (English
Text: non-volatile memory), for example, flash memory (English: flash memory), hard disk (English: hard disk
Drive, abbreviation: HDD) or solid state hard disk (English: solid-state drive, abbreviation: SSD)；Memory 604 can also wrap
Include the combination of the memory of mentioned kind.
Wherein, processor 51 can be central processing unit (English: central processing unit, abbreviation: CPU),
The combination of network processing unit (English: network processor, abbreviation: NP) or CPU and NP.
Wherein, processor 51 can further include hardware chip.Above-mentioned hardware chip can be specific integrated circuit
(English: application-specific integrated circuit, abbreviation: ASIC), programmable logic device (English:
Programmable logic device, abbreviation: PLD) or combinations thereof.Above-mentioned PLD can be Complex Programmable Logic Devices
(English: complex programmable logic device, abbreviation: CPLD), field programmable gate array (English:
Field-programmable gate array, abbreviation: FPGA), Universal Array Logic (English: generic array
Logic, abbreviation: GAL) or any combination thereof.
Optionally, memory 54 is also used to store program instruction.Processor 51 can be instructed with caller, realize such as this Shen
It please the verification method based on computing unit shown in Fig. 1-3 embodiment.
The embodiment of the invention also provides a kind of non-transient computer storage medium, computer storage medium is stored with calculating
The verifying based on computing unit in above-mentioned any means embodiment can be performed in machine executable instruction, the computer executable instructions
Method.Wherein, storage medium can be magnetic disk, CD, read-only memory (Read-Only Memory, ROM), random storage
Memory body (Random Access Memory, RAM), flash memory (Flash Memory), hard disk (Hard Disk
Drive, abbreviation: HDD) or solid state hard disk (Solid-State Drive, SSD) etc.；Storage medium can also include mentioned kind
Memory combination.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And thus amplify out it is obvious variation or
It changes still within the protection scope of the invention.
Claims (10)
1. a kind of verification method based on computing unit characterized by comprising
Obtain instruction to be verified；
According to the instruction to be verified, to sequence of opcodes, operation Number Sequence and the register series in virtual sequence library into
Row calls, with building verifying excitation；
The verifying is captured using monitor to motivate, and the verifying is motivated and is sent into reference model；
The export structure of the monitor is collected using scoring board computing unit processing result and the reference model into
Row is relatively checked, to be verified result.
2. the method according to claim 1, wherein described according to the instruction to be verified, to sequence of opcodes,
Operation Number Sequence and register series are combined calling, with building verifying excitation, comprising:
Function scene composition is carried out to virtual sequence library based on the instruction to be verified；Wherein, the virtual sequence library includes pair
It should be in the sequence of the computing unit of at least two types；
The sequence of opcodes, the operation Number Sequence and described are determined in the virtual sequence library using test case library
The calling of register series, to obtain the verifying excitation corresponding to the instruction to be verified.
3. according to the method described in claim 2, it is characterized by further comprising:
Function scenario building parameter is obtained, the function scenario building parameter includes order number, operand type and number；
It is wherein, described that function scene composition is carried out to virtual sequence library based on the instruction to be verified, comprising:
Using described instruction number, orientation chooses specific instruction sequence from instruction operation code sequence library；
Random operation number is chosen using the operand and number；
Determine that specific input is posted from register series library using the macrodefinition to be verified for instructing corresponding computing unit
Storage；
The function field is constructed using the specific instruction sequence, the random operation number and the specific input register
Scape.
4. according to the method described in claim 2, it is characterized by further comprising:
Obtain specified operand, immediate and register value；
The function scene is constructed using described instruction operand, the immediate and the register value.
5. method according to any of claims 1-4, which is characterized in that it is described according to the instruction to be verified, it is right
Sequence of opcodes, operation Number Sequence and register series are called, before the step of building verifying excitation, further includes:
Parameter in the instruction to be verified is constrained, the parameter includes operand.
6. the method according to claim 1, wherein reference model meter corresponding with the instruction to be verified
Unit is calculated to correspond.
7. according to the method described in claim 6, it is characterized in that, the reference model is realized using C language.
8. a kind of verifying device based on computing unit characterized by comprising
Module is obtained, for obtaining instruction to be verified；
Construct module, for according to the instruction to be verified, in virtual sequence library sequence of opcodes, operation Number Sequence and
Register series are called, with building verifying excitation；
Trapping module captures the verifying using monitor and motivates, and the verifying is motivated and is sent into reference model；
Comparison module is compared and checked using export structure of the scoring board to the monitor and the reference model, with
It is verified result.
9. a kind of verification platform characterized by comprising
Memory and processor communicate with each other connection, are stored in the memory between the memory and the processor
Computer instruction, the processor is by executing the computer instruction, thereby executing of any of claims 1-7
Verification method based on computing unit.
10. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage has computer to refer to
It enables, the computer instruction is used to making the computer perform claim to require described in any one of 1-7 based on computing unit
Verification method.
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| CN201910185856.3A CN109933529B (en) | 2019-03-12 | 2019-03-12 | Verification method and verification platform based on computing unit |
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| CN109933529B CN109933529B (en) | 2022-03-29 |
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| CN111190786A (en) * | 2019-12-31 | 2020-05-22 | Oppo广东移动通信有限公司 | UVM-based test framework, test platform and test method |
| CN111460746A (en) * | 2020-03-31 | 2020-07-28 | 上海安路信息科技有限公司 | Method and device for realizing circuit design by FPGA IP soft core and FPGA chip |
| CN111523283A (en) * | 2020-04-16 | 2020-08-11 | 北京百度网讯科技有限公司 | Method and device for verifying processor, electronic equipment and storage medium |
| CN112232000A (en) * | 2020-10-23 | 2021-01-15 | 海光信息技术股份有限公司 | Authentication system, authentication method and authentication device spanning multiple authentication domains |
| CN112365917A (en) * | 2020-12-04 | 2021-02-12 | 深圳市芯天下技术有限公司 | Nonvolatile memory instruction combination verification method and device, storage medium and terminal |
| CN112560393A (en) * | 2020-12-17 | 2021-03-26 | 中科芯云微电子科技有限公司 | Comparison verification method and device of EDA software tool |
| CN114330625A (en) * | 2021-11-18 | 2022-04-12 | 北京智芯微电子科技有限公司 | Passive radio frequency tag verification system and control method thereof |
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| CN111190786A (en) * | 2019-12-31 | 2020-05-22 | Oppo广东移动通信有限公司 | UVM-based test framework, test platform and test method |
| CN111460746A (en) * | 2020-03-31 | 2020-07-28 | 上海安路信息科技有限公司 | Method and device for realizing circuit design by FPGA IP soft core and FPGA chip |
| CN111523283A (en) * | 2020-04-16 | 2020-08-11 | 北京百度网讯科技有限公司 | Method and device for verifying processor, electronic equipment and storage medium |
| CN111523283B (en) * | 2020-04-16 | 2023-05-26 | 北京百度网讯科技有限公司 | Method and device for verifying processor, electronic equipment and storage medium |
| CN112232000A (en) * | 2020-10-23 | 2021-01-15 | 海光信息技术股份有限公司 | Authentication system, authentication method and authentication device spanning multiple authentication domains |
| CN112365917B (en) * | 2020-12-04 | 2021-11-05 | 芯天下技术股份有限公司 | Nonvolatile memory instruction combination verification method and device, storage medium and terminal |
| CN112365917A (en) * | 2020-12-04 | 2021-02-12 | 深圳市芯天下技术有限公司 | Nonvolatile memory instruction combination verification method and device, storage medium and terminal |
| CN112560393A (en) * | 2020-12-17 | 2021-03-26 | 中科芯云微电子科技有限公司 | Comparison verification method and device of EDA software tool |
| CN112560393B (en) * | 2020-12-17 | 2023-01-24 | 中科芯云微电子科技有限公司 | Comparison verification method and device of EDA software tool |
| CN114330625A (en) * | 2021-11-18 | 2022-04-12 | 北京智芯微电子科技有限公司 | Passive radio frequency tag verification system and control method thereof |
| CN114330625B (en) * | 2021-11-18 | 2024-01-23 | 北京智芯微电子科技有限公司 | Passive radio frequency tag verification system and control method thereof |
| CN114896114A (en) * | 2022-03-01 | 2022-08-12 | 北京百度网讯科技有限公司 | Score board implementation method and device, score board, electronic equipment and storage medium |
| WO2023165059A1 (en) * | 2022-03-01 | 2023-09-07 | 北京百度网讯科技有限公司 | Scoreboard implementation method and apparatus, scoreboard, electronic device, and storage medium |
| CN116070474A (en) * | 2023-04-07 | 2023-05-05 | 之江实验室 | Verification excitation generation method for AI floating point fusion operation unit |
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Address after: No.9, Xuesen Road, science and Technology City, Suzhou high tech Zone, Suzhou City, Jiangsu Province Patentee after: Hexin Technology (Suzhou) Co.,Ltd. Address before: 215163 building 3, No.9 Xuesen Road, science and Technology City, high tech Zone, Suzhou City, Jiangsu Province Patentee before: SUZHOU POWERCORE TECHNOLOGY Co.,Ltd. |
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