CN109921802B - Decoding method, module and device of QC-LDPC code - Google Patents
Decoding method, module and device of QC-LDPC code Download PDFInfo
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Abstract
The invention provides a method, a module and a device for decoding QC-LDPC codes. The method comprises the following steps: calculating external information transmitted to the check node by the Z-layer variable node according to the check matrix of the QC-LDPC code and the first shift information; updating the Z-layer check nodes simultaneously according to the external information transmitted to the check nodes by the Z-layer variable nodes; z is a natural number; updating the Z-layer variable nodes simultaneously according to the updated Z-layer check nodes, and shifting the updated Z-layer variable nodes according to second shifting information; and judging according to the shifted variable nodes, and determining whether to stop iterative updating according to a judgment result so as to output a decoding result. The decoding method of the QC-LDPC code provided by the embodiment of the invention improves the decoding efficiency, saves the decoding time, and has wide applicability and high flexibility.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, a module, and an apparatus for decoding a QC-LDPC code.
Background
Digital signals are subject to errors during transmission due to noise and interference, and error correction coding techniques are commonly employed in communication systems to ensure reliable transmission. Currently, low Density Parity Check Code (LDPC) is considered as one of the most promising error correction coding methods.
However, the encoding complexity of the LDPC code is high, and therefore, in recent years, a Quasi-cyclic Low-Density Parity-Check code (hereinafter referred to as QC-LDPC) has been proposed. The check matrix of the QC-LDPC code is composed of a plurality of sub-matrixes, and each sub-matrix is a unit cyclic matrix or an all-zero matrix, so that cyclic digits can be used for replacing the sub-matrixes for storage, and the storage space is greatly saved.
The decoding process of the QC-LDPC code is to update the transfer information between variable nodes and check nodes in the check matrix, complete decoding through multiple iterations, and decode each iteration according to the flow of parallel sub-codes and layered sub-codes. Because the number of check nodes in the check matrix of the QC-LDPC code is huge, the decoding time of the current QC-LDPC code is long, and the decoding throughput is low.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides a method, a module and a device for decoding QC-LDPC codes.
According to a first aspect of the present invention, there is provided a method for decoding a QC-LDPC code, comprising:
calculating external information transmitted to the check node by the Z-layer variable node according to the check matrix of the QC-LDPC code and the first shift information;
updating the Z-layer check nodes simultaneously according to the external information transmitted to the check nodes by the Z-layer variable nodes; z is a natural number;
updating the Z-layer variable nodes simultaneously according to the updated Z-layer check nodes, and shifting the updated Z-layer variable nodes according to the second shift information;
and judging according to the shifted variable nodes, and determining whether to stop iterative updating according to a judgment result so as to output a decoding result.
In an embodiment of the present invention, the updating the Z-layer check nodes simultaneously according to the external information transmitted to the check nodes by the variable nodes includes:
determining minimum value, secondary minimum value and minimum value index from the information transmitted from the Z-layer variable node to the check node;
and updating each layer of check nodes simultaneously according to the minimum value, the second minimum value and the minimum value index based on the external information transmitted to the check nodes by the variable nodes.
In one embodiment of the invention, let σ' j For the tth updated check node information, then
Where α is the scaling factor and sign (k) is the kth θ v→c Sum _ sign is θ per layer v→c Sub _ min is a second smallest value, min is a smallest value, min _ index is a smallest value index, and theta is the result of the symbolic operation of (1) v→c And transmitting variable nodes to check node information, wherein j is a column index of a value 1 in the ith row in the check matrix, and k is a natural number.
In an embodiment of the present invention, after updating each layer of variable nodes simultaneously according to the updated check nodes, the method further includes:
and updating and storing non-zero-value nodes in the check matrix of the QC-LDPC code to obtain an updated check matrix.
In one embodiment of the present invention, further comprising: and storing non-zero value indexes in the check base matrix of the QC-LDPC code.
According to a second aspect of the present invention, there is provided a decoding module for a QC-LDPC code, comprising:
the data storage unit is used for storing Z-layer variable node information of the QC-LDPC code;
a first shift unit configured to shift the Z-layer variable node stored in the data storage unit 21 in one clock cycle according to first shift information;
the calculation unit is used for calculating external information transmitted to the check node by the variable node according to the variable node information after the first shifting unit shifts;
the check node updating unit is used for updating the Z-layer check nodes according to the external information transmitted to the check nodes by the variable nodes;
the variable node updating unit is used for updating the Z-layer variable nodes simultaneously according to the updated Z-layer check nodes;
the second shifting unit is used for shifting the updated Z-layer variable node in one clock cycle according to second shifting information;
and the judgment unit is used for carrying out hard judgment according to the shifted variable node and determining whether to stop iterative updating according to a judgment result so as to output a decoding result.
In one embodiment of the present invention, further comprising: the device comprises a lookup table storage unit, a matrix storage subunit and an index storage subunit, wherein the lookup table storage unit comprises the matrix storage subunit and the index storage subunit;
and the matrix storage subunit is used for storing the updated check matrix of the QC-LDPC code.
And the index storage unit is used for storing the non-zero value index in the check base matrix.
According to a third aspect of the present invention, there is provided a decoding apparatus of a QC-LDPC code, including: the program storage module, the control module and the decoding module;
the program storage module is used for storing QC-LDPC codes to be decoded;
the decoding module is used for decoding the QC-LDPC codes stored by the program storage module;
and the control module is used for controlling the working states and time sequences of the program storage module and the decoding module.
According to a fourth aspect of the present invention, there is provided an electronic apparatus comprising:
a processor;
a memory for storing the processor-executable instructions;
the executable instructions, when executed by the processor, cause the processor to perform the above-described method of decoding a QC-LDPC code.
According to a fifth aspect of the present invention, there is provided a computer-readable storage medium having stored thereon computer program instructions which, when executed by a processor, cause the processor to perform the method of decoding QC-LDPC codes.
Compared with the prior art, the invention has the advantages that:
1) The embodiment of the invention calculates the external information transmitted to the check node by the Z-layer variable node according to the check matrix of the QC-LDPC code and the first shift information, updates the Z-layer check node simultaneously according to the external information, updates the Z-layer variable node simultaneously according to the updated check node, shifts the updated variable node according to the second shift information, finally carries out hard decision according to the shifted variable node, and determines whether to stop iterative update or not according to the decision result so as to output the decoding result. Because the plurality of layers of check nodes can be updated simultaneously and all the check nodes of each layer are updated simultaneously, the decoding efficiency is greatly improved and the decoding time is saved; meanwhile, the variable nodes are shifted through the first shift information and the second shift information, so that the decoding method is suitable for different check matrixes, and the applicability and the flexibility of the decoding method are improved;
2) Furthermore, the nonzero-value index in the check base matrix is stored, and the designated variable node can be quickly updated through the stored nonzero-value index when the variable node is updated, so that the decoding efficiency is further improved;
3) Furthermore, minimum value, sub-minimum value and minimum value index are determined from the information transmitted to the check nodes from each layer of variable nodes, then the multi-layer check nodes are updated simultaneously according to the minimum value, the sub-minimum value and the minimum value index, and various QC-LDPC codes can be decoded, so that the decoding method not only has wide application, but also can meet the requirements of various communication systems;
4) Furthermore, the non-zero value nodes in the check matrix are updated and stored, and when the check nodes and the variable nodes are updated subsequently, the nodes can be updated according to the sequence of the stored non-zero value nodes, so that the addressing operation before updating is saved, and the network overhead is greatly reduced;
5) Furthermore, in the embodiment of the present invention, the program storage module stores the QC-LDPC code to be decoded, one instruction is extracted in each clock cycle, the bit width of the data storage unit is Z × Col _ Num × BW, a bit width scalable high parallel storage module is formed, the lookup table storage unit stores the check base matrix and the non-zero value index, and these three storage modes form a high parallelism storage system, so that the decoding device can access multiple pieces of data in one clock cycle, thereby implementing single-instruction multiple-data stream processing and greatly improving the decoding efficiency.
Drawings
The invention is illustrated in the following drawings, which are only schematic and explanatory and are not restrictive of the invention, and wherein:
FIG. 1 is a flow chart illustrating a method for decoding a QC-LDPC code according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a structure of a decoding module of a QC-LDPC code according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an update procedure of a check node update unit according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the structure of a QC-LDPC code decoding apparatus according to an embodiment of the present invention;
fig. 5 shows a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions, design methods, and advantages of the present invention more apparent, the present invention will be further described in detail by specific embodiments with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Before describing the embodiments of the present invention, the basic description of the LDPC code and the QC-LDPC code is first made to facilitate understanding of the present invention.
LDPC codes are a special type of linearityBlock codes. In communication, every time a code word c with the packet length of N bits is transmitted, M check bits are needed to ensure that the code word c has certain error correction capability, and each code word is required to meet the requirement of c.H T =0, where H is a parity check matrix of M × N dimensions over a binary domain.
The QC-LDPC code is a subclass of LDPC code, and its check matrix H is formed by several sub-matrixes belonging to cyclic permutation matrix, in which the sub-matrix is obtained by making cyclic right shift of column and row of unit matrix. And setting a check matrix H of the QC-LDPC code to be formed by J x L sub-matrixes belonging to the cyclic permutation matrix, wherein the size of each sub-matrix is Z x Z, and the QC-LDPC code has J x Z check nodes and L x Z variable nodes. Therefore, the decoding parallelism of the invention is Z, and Z layer data can be processed every clock cycle.
The technical solution of the present invention will be described in detail with reference to specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 1, an embodiment of the present invention provides a decoding method for a QC-LDPC code, including:
s101, calculating external information transmitted to check nodes by Z-layer variable nodes according to a check matrix of the QC-LDPC code and first shift information;
specifically, the external information transmitted to the check node by the variable node is set as sigma j' Then, then
σ j' ＝γ j -λ i,j Wherein γ is j Is a variable node, λ i,j J is a column index where a value 1 in the ith row in the check matrix is located, j '=0,1, 2., N-1, j' represents a check node index value to be updated in each layer, and N is a row weight of the ith row in the check matrix.
In the embodiment of the invention, only the non-zero value nodes are stored in the check matrix. After the check matrix is shifted through the acquired first shift information, the variable nodes of each layer are nonzero-value nodes, so that external information transmitted to the check nodes by the variable nodes of the Z layer can be calculated at the same time. Wherein, the first shift information is the times of cyclic shift of the QC-LDPC code.
S102, updating the Z-layer check nodes simultaneously according to external information transmitted to the check nodes by the Z-layer variable nodes; z is a natural number;
the decoding process of the QC-LDPC code is completed through multiple iterations, in the prior art, each iteration is performed according to the flow of parallelism among subcodes and layering in the subcodes, and the specific decoding process is to update the transmission information between variable nodes and check nodes. The embodiment of the invention updates the check nodes of the Z layer simultaneously, thereby greatly improving the decoding efficiency.
Specifically, the step S102 of updating the Z-layer check nodes simultaneously according to the external information transmitted by the variable nodes to the check nodes includes:
s1021, determining a minimum value, a secondary minimum value and a minimum value index from the information transmitted from the variable node to the check node;
and S1022, based on the external information transmitted to the check nodes by the variable nodes, updating the check nodes of each layer simultaneously according to the minimum value, the secondary minimum value and the minimum value index.
For example, provided σ' j For the kth updated check node information, then
Where α is the scaling factor and sign (k) is the kth θ v→c Sum _ sign is θ per layer v→c Sub _ min is a second smallest value, min is a smallest value, min _ index is a smallest value index, and theta is the result of the symbolic operation of (1) v→c And transmitting the variable node information to the check node information.
It should be noted that, in the embodiment of the present invention, the check node update formula may be adaptively modified according to specific requirements, that is, corresponding algorithms, such as a min-sum algorithm, a normalized min-sum algorithm, a lookup table algorithm, a Q-function algorithm, and the like, are implemented through the value of α. The embodiment of the present invention is described by taking a minimum sum algorithm as an example, but the embodiment of the present invention is not limited to a specific check node update formula. For example, when the scaling factor α is 1, the check node update algorithm is a minimum sum algorithm; when alpha is other fixed value, such as 0.95, the check node updating algorithm is a normalized minimum sum algorithm; when alpha is a programmable parameter, the check node updating algorithm is a lookup table algorithm.
S103, updating the Z-layer variable nodes simultaneously according to the updated Z-layer check nodes, and shifting the updated Z-layer variable nodes according to second shift information;
each layer of the check matrix is provided with variable nodes, and the number of the variable nodes is equal to the row weight of the layer. Setting the updated variable node of each layer as gamma j ', then gamma j ′＝γ j -λ i,j +σ' j Wherein γ is j Is the variable node, σ 'before update' j Is the updated check node information. Let gamma j "is the variable node shifted according to the second shift information.
Specifically, second shift information of the variable node in the Z layer may be obtained through the lookup table, and the updated variable node is shifted according to the second shift information. As is well known, the definitions of the check matrices in different communication standards are different, and in the embodiment of the present invention, the variable nodes are shifted through the first shift information and the second shift information, so that the decoding method can adapt to different check matrices, thereby improving the applicability and flexibility of the decoding method.
Further, after step S103 updates the variable nodes of each layer at the same time according to the updated check node, the embodiment of the present invention further includes:
and updating and storing non-zero-value nodes in the check matrix of the QC-LDPC code to obtain an updated check matrix.
In particular, λ i,j ＝σ' j The non-zero value nodes in the check matrix are updated and stored, and when the check nodes and the variable nodes are updated subsequently, the nodes can be updated according to the sequence of the stored non-zero value nodes, so that the addressing operation before updating is saved, and the network overhead is greatly reduced.
Further, the embodiment of the present invention further includes:
and storing non-zero value indexes in the check base matrix of the QC-LDPC code.
After the non-zero value index in the check base matrix of the QC-LDPC code is stored, the designated variable node can be quickly updated through the stored non-zero value index when the variable node is updated, and the decoding efficiency is further improved. This step may be executed before or after any step from S101 to S104, and the specific execution time of S105 is not limited in the embodiment of the present invention.
And S104, judging according to the shifted variable nodes, and determining whether to stop iterative updating according to a judgment result so as to output a decoding result.
In the embodiment of the invention, the decision bit is set as v j If vH T If =0, stopping decoding; otherwise, repeating the steps 101 to 104, and performing the next iteration operation until the maximum iteration number I is reached max And stopping decoding. Since it is common knowledge of those skilled in the art to make hard decisions according to updated variable nodes, the embodiments of the present invention are not described herein again.
The embodiment of the invention calculates the external information transmitted to the check node by the Z-layer variable node according to the check matrix of the QC-LDPC code and the first shift information, updates the Z-layer check node simultaneously according to the external information, updates the Z-layer variable node simultaneously according to the updated check node, shifts the updated variable node according to the second shift information, finally carries out hard decision according to the shifted variable node, and determines whether to stop iterative update or not according to the decision result so as to output the decoding result. Because the multiple layers of check nodes can be updated simultaneously and all the check nodes of each layer are updated simultaneously, the decoding efficiency is greatly improved and the decoding time is saved; meanwhile, the variable nodes are shifted through the first shift information and the second shift information, so that the decoding method is suitable for different check matrixes, and the applicability and the flexibility of the decoding method are improved; furthermore, the nonzero-value index in the check base matrix is stored, and the designated variable node can be quickly updated through the stored nonzero-value index when the variable node is updated, so that the decoding efficiency is further improved; furthermore, minimum value, sub-minimum value and minimum value index are determined from the information transmitted to the check node from each layer of variable node, then the multi-layer check nodes are updated simultaneously according to the minimum value, sub-minimum value and minimum value index, and a plurality of QC-LDPC codes can be decoded, so that the decoding method not only has wide application, but also can meet the requirements of a plurality of communication systems; furthermore, the non-zero value nodes in the check matrix are updated and stored, and when the check nodes and the variable nodes are updated subsequently, the nodes can be updated according to the sequence of the stored non-zero value nodes, so that the addressing operation before updating is saved, and the network overhead is greatly reduced.
Fig. 2 is a schematic structural diagram of a decoding module of a QC-LDPC code according to an embodiment of the present invention, and as shown in fig. 2, the decoding module 20 includes: a data storage unit 21, a first shifting unit 22, a calculation unit 23, a check node updating unit 24, a variable node updating unit 25, a second shifting unit 26 and a decision unit 27;
the data storage unit 21 is used for storing Z-layer variable node information of the QC-LDPC codes; the number of the data storage units is the maximum row weight of the check matrix of the QC-LDPC code.
In the embodiment of the invention, the maximum row weight is the number of non-zero nodes of each layer of variable nodes of the check matrix H, and the maximum row weight of the check matrix H is set to be Col _ Num. The check matrix H is expanded from the base matrix, the expanded sub-matrix is a matrix of Z × Z, and BW represents the quantization bit width of the node information value, so the bit width of the data storage unit in the embodiment of the present invention is Z × Col _ Num × BW bits.
Wherein the variable node information comprises variable node information of the received QC-LDPC code and updated variable node information.
A first shift unit 22, configured to shift, in one clock cycle, the Z-layer variable node stored in the data storage unit 21 according to first shift information;
in the embodiment of the present invention, the shift unit may be a direct shifter, a benes shifter, or a barrel shifter, and since configuration information required by the barrel shifter is simple and there is no requirement for the number of data at the input end, the first shift unit in the embodiment of the present invention is described as an example using the first barrel shifter, but the embodiment of the present invention does not limit the specific form of the shift unit, as long as the shift purpose in the embodiment of the present invention can be achieved.
Correspondingly, the number of the first barrel shifters is Col _ Num, which can shift Z variable node information with bit width BW in one clock.
The calculating unit 23 is configured to calculate external information transmitted to the check node by the variable node according to the variable node information shifted by the first shifting unit 22;
a check node updating unit 24, configured to update the Z-layer check nodes according to the external information transmitted to the check nodes by the variable nodes calculated by the calculating unit 23;
the updating process of the check node is described below by taking 802.11n as an example, and the check base matrix of the protocol is taken as Hb,
Hb＝{0,-1,-1,-1,0,0,-1,-1,0,-1,-1,0,1,0,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,22,0,-1,-1,17,-1,0,0,12,-1,-1,-1,-1,0,0,-1,-1,-1,-1,-1,-1,-1,-1,-1,6,-1,0,-1,10,-1,-1,-1,24,-1,0,-1,-1,-1,0,0,-1,-1,-1,-1,-1,-1,-1,-1,2,-1,-1,0,20,-1,-1,-1,25,0,-1,-1,-1,-1,-1,0,0,-1,-1,-1,-1,-1,-1,-1,23,-1,-1,-1,3,-1,-1,-1,0,-1,9,11,-1,-1,-1,-1,0,0,-1,-1,-1,-1,-1,-1,24,-1,23,1,17,-1,3,-1,10,-1,-1,-1,-1,-1,-1,-1,-1,0,0,-1,-1,-1,-1,-1,25,-1,-1,-1,8,-1,-1,-1,7,18,-1,-1,0,-1,-1,-1,-1,-1,0,0,-1,-1,-1,-1,13,24,-1,-1,0,-1,8,-1,6,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,0,-1,-1,-1,7,20,-1,16,22,10,-1,-1,23,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,0,-1,-1,11,-1,-1,-1,19,-1,-1,-1,13,-1,3,17,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,0,-1,25,-1,8,-1,23,18,-1,14,9,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,0,3,-1,-1,-1,16,-1,-1,2,25,5,-1,-1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0}；
in the embodiment of the present invention, the check node updating unit updates 24 check nodes of all layers at the same time. Fig. 3 is a schematic diagram of an update process structure of a check node update unit, and as shown in fig. 3, a min4to2 module is a four-input three-output module, that is, a minimum value and a second minimum value are selected from information transmitted from four variable nodes to a check node, and a minimum value index is output; the min3to2 module is a six-input three-output module, namely a minimum value and a secondary minimum value are selected from information transmitted to the check node from three variable nodes, and a minimum value index is output from three index values; the min3to1 module is a three-input one-output module, namely, the minimum value is selected from information transmitted to the check node by three variable nodes; the min2to2 module is a four-input three-output module, namely a minimum value and a secondary minimum value are selected from information transmitted to the check node from two variable nodes, and a minimum value index is output from two index values; the min2to1 module is a two-input one-output module, i.e., the minimum value is selected from the information transmitted from the two variable nodes to the check node. The data0_ pro module updates the 0 th check node, the data1_ pro module updates the 1 st check node, and so on, and the data23_ pro module updates the 24 th check node.
The Data0_ pro module to the Data23_ pro module specifically update the check node according to the check node update formula in the method, and the embodiment of the present invention is not described herein again.
In the embodiment of the invention, the check node updating unit compares data through multiple groups of multiple levels to determine the minimum value and the secondary minimum value, so that the operation efficiency is high.
The variable node updating unit 25 is configured to update the Z-layer variable nodes simultaneously according to the updated Z-layer check nodes;
specifically, the variable node update unit is composed of a plurality of adders.
A second shifting unit 26, configured to shift the updated Z-layer variable node according to second shifting information in one clock cycle;
specifically, the second shifting unit 26 may obtain the second shifting information through the lookup table, and shift the updated variable node according to the second shifting information.
Further, the second shifting unit stores the shifted variable node into the data storage unit to update the variable node information stored in the data storage unit.
As described above, the second shift unit is the second barrel shifter, and the number of the second barrel shifter is also Col _ Num.
The maximum value of Z in the current 5GNR protocol is 384, and the adopted barrel shifter can support that Z takes any value (Z < = 384).
Because the definitions of the check matrixes in different communication standards are different, the decoding module can adapt to different check matrixes by arranging the first shifting unit and the second shifting unit to shift the variable nodes in the embodiment of the invention, thereby improving the applicability, flexibility and life cycle of the decoding module.
A decision unit 27, configured to perform decision according to the variable node shifted by the second shift unit 26, and determine whether to stop iterative update according to a decision result, so as to output a decoding result.
Furthermore, the embodiment of the invention also comprises a lookup table storage unit, wherein the lookup table storage unit comprises a matrix storage subunit and an index storage subunit;
and the matrix storage subunit is used for storing a check base matrix of the updated QC-LDPC code, and the check base matrix is a non-zero-value node in the check matrix.
Specifically, the nonzero-value nodes in the check matrix are updated and stored, and when the check nodes and the variable nodes are updated subsequently, the stored nonzero-value nodes can be updated according to the sequence of the stored nonzero-value nodes, so that the addressing operation before updating is saved, and the network overhead is greatly reduced.
And the index storage unit is used for storing the non-zero value index in the check base matrix.
Correspondingly, the variable node updating unit is used for updating the variable nodes of each layer at the same time according to the nonzero-value index stored in the index storage unit and the updated check node.
Continuing with the example of fig. 3, the storage bit width requirement of the matrix memory subunit is 9 × 24=216bit, the storage bit width requirement of the index memory subunit is 7 × 24=168bit, and considering that the storage bit width is generally the power of 2, the bit width of the lookup table memory unit is set to 256bit in the embodiment of the present invention.
In the 802.11n protocol, when the code rate of the QC-LDPC code is 1/2, the iteration times are 10, 12 cycles are needed for one-time iterative decoding, and the main frequency is 200MHz, the throughput of decoding through the decoding module is 540Mbps. In the 802.16 protocol, when the code rate of the QC-LDPC code is 1/2, the parallelism Z of decoding is 96, and the maximum data stream decoded in each clock cycle is 2304, the decoding throughput of the decoding module is 1.92Gbps, so that the decoding module greatly improves the decoding throughput of the QC-LDPC code in the embodiment of the invention.
The embodiment of the invention calculates the external information transmitted to the check node by the Z-layer variable node according to the check matrix of the QC-LDPC code and the first shift information, updates the Z-layer check node simultaneously according to the external information, updates the Z-layer variable node simultaneously according to the updated check node, shifts the updated variable node according to the second shift information, finally carries out hard decision according to the shifted variable node, and determines whether to stop iterative update or not according to the decision result so as to output the decoding result. Because the multiple layers of check nodes can be updated simultaneously and all the check nodes of each layer are updated simultaneously, the decoding efficiency is greatly improved and the decoding time is saved; meanwhile, the variable nodes are shifted by arranging the first shifting unit and the second shifting unit, so that the decoding module can adapt to different check matrixes, and the applicability, flexibility and life cycle of the decoding module are improved; furthermore, a check node updating unit of the decoding module determines a minimum value, a secondary minimum value and a minimum value index from the information transmitted to the check node by each layer of variable node; then updating the Z-layer check nodes according to the minimum value, the second minimum value and the minimum value index, and updating the check nodes according to a plurality of decoding algorithms, so that decoding of a plurality of QC-LDPC codes is supported, the use efficiency of a hardware unit is improved, and meanwhile, the decoding module can realize the change of application requirements through software programming, and the life cycle of a chip using the decoding module is improved; furthermore, the index storage subunit stores the nonzero-value index in the check base matrix, and when the variable node is updated, the designated variable node can be quickly updated through the stored nonzero-value index, so that the decoding efficiency is further improved; furthermore, the matrix storage subunit stores the non-zero value nodes in the updated check matrix, and when the check nodes and the variable nodes are updated subsequently, the non-zero value nodes can be updated according to the sequence of the stored non-zero value nodes, so that the addressing operation before updating is saved, and the network overhead is greatly reduced.
Fig. 4 is a schematic structural diagram of a decoding device for QC-LDPC codes according to an embodiment of the present invention, and as shown in fig. 4, the decoding device includes: a program storage module 31, a control module 32 and the decoding module 20 shown in fig. 2;
wherein, the program storage module 31 is used for storing the QC-LDPC codes to be decoded;
a decoding module 20, configured to decode the QC-LDPC code stored in the program storage module 31;
and a control module 32 for controlling the working state and timing sequence of the program storage module 31 and the decoding module 20.
The embodiment of the invention calculates the external information transmitted to the check nodes by the Z-layer variable nodes according to the check matrix of the QC-LDPC codes and the first shift information, updates the Z-layer check nodes simultaneously according to the external information, updates the Z-layer variable nodes simultaneously according to the updated check nodes, shifts the updated variable nodes according to the second shift information, finally carries out hard decision according to the shifted variable nodes, and determines whether to stop iterative update according to the decision result so as to output the decoding result. Because the plurality of layers of check nodes can be updated simultaneously and all the check nodes of each layer are updated simultaneously, the decoding efficiency is greatly improved and the decoding time is saved; meanwhile, the variable nodes are shifted by arranging the first shifting unit and the second shifting unit, so that the decoding module can adapt to different check matrixes, and the applicability, flexibility and life cycle of the decoding module are improved; furthermore, a check node updating unit of the decoding module determines a minimum value, a secondary minimum value and a minimum value index from the information transmitted to the check node by each layer of variable node; then updating the Z-layer check nodes according to the minimum value, the second minimum value and the minimum value index, and updating the check nodes according to a plurality of decoding algorithms, so that decoding of a plurality of QC-LDPC codes is supported, the use efficiency of a hardware unit is improved, and meanwhile, the decoding module can realize the change of application requirements through software programming, and the life cycle of a chip using the decoding module is improved; furthermore, the index storage subunit stores the nonzero-value index in the check base matrix, and when the variable node is updated, the designated variable node can be quickly updated through the stored nonzero-value index, so that the decoding efficiency is further improved; furthermore, the matrix storage subunit stores the non-zero value nodes in the updated check matrix, and when the check nodes and the variable nodes are updated subsequently, the non-zero value nodes can be updated according to the sequence of the stored non-zero value nodes, so that the addressing operation before updating is saved, and the network overhead is greatly reduced; furthermore, in the embodiment of the invention, the program storage module stores the QC-LDPC codes to be decoded, one instruction is extracted in each clock cycle, the bit width of the data storage unit is Z × Col _ Num × BW, a high parallel storage module with scalable bit width is formed, the lookup table storage unit stores the check base matrix and the nonzero-value index, and the three storage modes form a high-parallelism storage system, so that a decoding device can access a plurality of data in one clock cycle, single-instruction multiple-data-stream processing is realized, and the decoding efficiency is greatly improved.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and an electronic device according to an embodiment of the present application is described below with reference to fig. 5.
As shown in fig. 5, the electronic device 100 includes one or more processors 101 and memory 102.
The processor 101 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 100 to perform desired functions.
In one example, the electronic device 100 may further include: an input device 103 and an output device 104, which are interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, the input device 103 may include a camera device for capturing an input image. The input device 103 may also include, for example, a keyboard, a mouse, and the like.
The output device 104 may output various information to the outside, including the determined foreground mask profile. The output devices 104 may include, for example, a display, speakers, a printer, and a communication network and its connected remote output devices, among others.
Of course, for simplicity, only some of the components of the electronic device 100 relevant to the present application are shown in fig. 5, and components such as buses, input/output interfaces, and the like are omitted. In addition, electronic device 100 may include any other suitable components depending on the particular application.
In addition to the above-described methods and apparatuses, embodiments of the present application may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the steps in the method for decoding QC-LDPC codes according to the present application described in the "exemplary methods" section of this specification above.
The computer program product may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages, for carrying out operations according to embodiments of the present application. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, embodiments of the present application may also be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the steps in the method for decoding QC-LDPC codes according to the present application described in the "exemplary methods" section above in the present specification.
The computer-readable storage medium may take any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.
The block diagrams of devices, apparatuses, devices, systems referred to in this application are only used as illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably herein. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application. For example, the look-up table storage unit may be provided in the decoding apparatus as long as the corresponding function can be realized.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (9)
1. A decoding method of QC-LDPC codes comprises the following steps:
calculating external information transmitted to the check node by the Z-layer variable node according to the check matrix of the QC-LDPC code and the first shift information in the following mode: sigma j' ＝γ j -λ i,j Wherein σ j' Representing variable node gamma j External information, lambda, passed to check nodes i,j J is the row index of the value 1 in the ith row in the check matrix, j '=0,1, 2.. Multidot.N-1, and j' represents the check node index value to be updated in each layer, and N is the row weight of the ith row in the check matrix; the first shift information is the times of cyclic shift of the QC-LDPC codes; updating the Z-layer check nodes simultaneously according to the external information transmitted to the check nodes by the Z-layer variable nodes; z is a natural number; wherein, when updating Z layer check node simultaneously, include: determining minimum value, secondary minimum value and minimum value index from the information transmitted from the variable node to the check node; based on external information transmitted to the check nodes by the variable nodes, updating the check nodes of each layer simultaneously according to the minimum value, the second minimum value and the minimum value index according to a preset updating algorithm; updating the Z-layer variable nodes according to the updated Z-layer check nodes in the following mode, and shifting the updated Z-layer variable nodes according to the second shifting information: gamma ray j ′＝γ j -λ i,j +σ' j Wherein γ is j Is the variable node before update, σ' j The updated check node information; and judging according to the shifted variable nodes, and determining whether to stop iterative updating according to a judgment result so as to output a decoding result.
2. The method of claim 1, wherein σ' j For the tth updated check node information, then
Where α is the scaling factor and sign (k) is the kth θ v→c With sum _ sign of θ per layer v→c Sub _ min is a second smallest value, min is a smallest value, min _ index is a smallest value index, and theta is the result of the symbolic operation of (1) v→c And transmitting information to the check node for the variable node, wherein k is a natural number.
3. The method of claim 1, wherein after updating the Z-level variable nodes according to the updated Z-level check nodes simultaneously, further comprising:
and updating and storing non-zero-value nodes in the check matrix of the QC-LDPC code to obtain an updated check matrix.
4. The method of claim 1, further comprising: and storing non-zero value indexes in the check base matrix of the QC-LDPC code.
5. A decoding module for QC-LDPC codes, comprising:
the data storage unit is used for storing Z-layer variable node information of the QC-LDPC codes;
the first shifting unit is used for shifting the Z-layer variable node stored in the data storage unit in one clock cycle according to the first shifting information;
the calculation unit is used for calculating external information transmitted to the check node by the variable node according to the variable node information shifted by the first shifting unit in the following mode: sigma j' ＝γ j -λ i,j Wherein σ is j' Represents a variable node γ j External information, lambda, passed to check nodes i,j J is the row index of the value 1 in the ith row in the check matrix, j '=0,1, 2.. Multidot.N-1, and j' represents the check node index value to be updated in each layer, and N is the row weight of the ith row in the check matrix; the first shift information is the times of cyclic shift of the QC-LDPC codes;
the check node updating unit is used for updating the Z-layer check nodes according to the external information transmitted to the check nodes by the variable nodes in the following way: determining minimum value, secondary minimum value and minimum value index from the information transmitted from the variable node to the check node; based on external information transmitted to the check nodes by the variable nodes, updating the check nodes of each layer simultaneously according to the minimum value, the second minimum value and the minimum value index according to a preset updating algorithm;
and the variable node updating unit is used for updating the Z-layer variable nodes according to the updated Z-layer check nodes at the same time in the following way:γ j ′＝γ j -λ i,j +σ' j wherein γ is j Is the variable node before update, σ' j The updated check node information; the second shifting unit is used for shifting the updated Z-layer variable node in one clock cycle according to second shifting information;
and the judging unit is used for carrying out hard judgment according to the shifted variable nodes and determining whether to stop iterative updating according to a judgment result so as to output a decoding result.
6. The coding module of claim 5, further comprising:
the device comprises a lookup table storage unit, a data processing unit and a data processing unit, wherein the lookup table storage unit comprises a matrix storage subunit and an index storage subunit;
the matrix storage subunit is used for storing the check matrix of the updated QC-LDPC code;
and the index storage unit is used for storing the non-zero value index in the check base matrix.
7. An apparatus for decoding a QC-LDPC code, comprising: a program storage module, a control module and a decoding module as claimed in any one of claims 5 to 6;
the program storage module is used for storing the QC-LDPC codes to be decoded;
the decoding module is used for decoding the QC-LDPC codes stored by the program storage module;
and the control module is used for controlling the working states and time sequences of the program storage module and the decoding module.
8. An electronic device, comprising:
a processor;
a memory for storing the processor-executable instructions;
the executable instructions, when executed by the processor, cause the processor to perform a method for decoding a QC-LDPC code according to any one of claims 1 to 4.
9. A computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, cause the processor to perform a method of decoding QC-LDPC codes according to any one of claims 1 through 4.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101499804A (en) * | 2009-03-12 | 2009-08-05 | 上海交通大学 | Multi-code rate decoder for quasi-cyclic low density parity check code |
| CN101803205A (en) * | 2008-08-15 | 2010-08-11 | Lsi公司 | RAM list-decoding of near codewords |
| CN103220003A (en) * | 2013-03-29 | 2013-07-24 | 西安空间无线电技术研究所 | Realization method for QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoder for improving node processing parallelism |
| WO2013117076A1 (en) * | 2012-02-07 | 2013-08-15 | 中兴通讯股份有限公司 | Method and system for iterative decoding |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9509342B2 (en) * | 2014-06-02 | 2016-11-29 | Sandisk Technologies Llc | Error correcting code decoder |
-
2019
- 2019-02-26 CN CN201910139816.5A patent/CN109921802B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101803205A (en) * | 2008-08-15 | 2010-08-11 | Lsi公司 | RAM list-decoding of near codewords |
| CN101499804A (en) * | 2009-03-12 | 2009-08-05 | 上海交通大学 | Multi-code rate decoder for quasi-cyclic low density parity check code |
| WO2013117076A1 (en) * | 2012-02-07 | 2013-08-15 | 中兴通讯股份有限公司 | Method and system for iterative decoding |
| CN103220003A (en) * | 2013-03-29 | 2013-07-24 | 西安空间无线电技术研究所 | Realization method for QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoder for improving node processing parallelism |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的准循环LDPC码低时延译码器设计;雷瑾亮等;《北京理工大学学报》;20130715(第07期);全文 * |
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