CN109917192A - The test device of power MOSFET device conducting resistance and output capacitance based on attenuation oscillasion impulse - Google Patents
The test device of power MOSFET device conducting resistance and output capacitance based on attenuation oscillasion impulse Download PDFInfo
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Abstract
The test device of the invention discloses a kind of power MOSFET device conducting resistance and output capacitance based on attenuation oscillasion impulse, the sampled-data control system of measured power MOSFET element and its peripheral test circuit and rear end including front end；Testing circuit includes adjustable DC power supply, fuse, controllable impedance, voltage sample resistance, divider resistance and current sampling resistor, and sampled-data control system includes amplifier module, A/D module, CPU module, drive module and host computer.Measurement method of the present invention is easy, and installation cost is lower, and the avalanche capability, conducting resistance and output capacitance that measure power MOSFET device simultaneously may be implemented, easy to operate efficient.
Description
Technical field
The invention belongs to semiconductor test technical fields, and in particular to a kind of power MOSFET device based on attenuation oscillasion impulse
The test device of part conducting resistance and output capacitance.
Background technique
Power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transitor, metal oxidation
The long effect transistor of object semiconductor) device with its high frequency, low driving power, anti-interference energy is strong, cost performance is high the advantages that, in height
Play key player in frequency power conversion, therefore power MOSFET device is integrated in modern electronics.
Such as automotive field, their driving inductive loads such as motor and alternating current generator, these power MOSFET devices
Need to bear the energy spikes of non-clamper perception switch (Unclamped Inductive Switching, UIS).Non- clamper sense
Property the lower switching process of load be typically considered the most extreme stress that power MOSFET device can be subjected in system is applied
Situation, because the energy being stored in inductance when circuit is connected must all be discharged by power device in shutdown moment, simultaneously
The high voltage and high current for being applied to power device easily cause component failure, and this failure bring damage is usually that can not repair
Multiple, therefore avalanche capability is usually to measure the important indicator of power device reliable rows.
When consider power MOSFET device work in switching mode, target be the time as short as possible device most
Switch between small resistance state and maximum resistance state；Due to the presence of power MOSFET device parasitic capacitance, practical on-off time ratio reason
By switch time long at least 2~3 orders of magnitude, therefore in high-speed switch application, most important parameter is the parasitism electricity of device
Hold.
In conclusion measuring the avalanche capability of power MOSFET device, conducting resistance and output capacitance is that have very much must
Want, presently, there are most of measuring devices be only capable of individually testing avalanche capability or conducting resistance or output capacitance, there is survey
The problem of amount efficiency is low, higher cost, cannot achieve multiple characterisitic parameters while measuring.Wherein power MOSFET device is defeated
Capacitor mainly passes through LCR tester binding test circuit and measures out, by change test circuit in DC voltage source it is defeated
Voltage swing measures corresponding output capacitance out, and the output capacitance that can draw power MOSFET device under certain condition is leaked with device
The change curve of voltage between source electrodes；Although LCR tester and test circuit connection are simple, due to contact resistance, connection electricity
Stray capacitance between the series impedance of cable, connecting cable and terminal can cause biggish error.
Summary of the invention
In view of above-mentioned, the present invention provides a kind of power MOSFET device conducting resistance and output based on attenuation oscillasion impulse
The test device of capacitor, installation cost is lower, and measurement method is simple, and the snowslide that can measure power MOSFET device simultaneously is resistance to
Amount, conducting resistance and output capacitance.
A kind of test device of power MOSFET device conducting resistance and output capacitance based on attenuation oscillasion impulse, comprising:
The measured power MOSFET element and its peripheral test circuit of front end and the sampled-data control system of rear end；The test circuit packet
Include adjustable DC power supply, fuse, controllable impedance, voltage sample resistance RU1, divider resistance RU2With current sampling resistor RI,
In: the anode of adjustable DC power supply is connected with one end of fuse, and the other end of fuse is connected with one end of controllable impedance, can
Adjust the other end of inductance and the drain electrode of measured power MOSFET element and divider resistance RU2One end be connected, divider resistance RU2
The other end and voltage sample resistance RU1One end and sampled-data control system be connected, voltage sample resistance RU1The other end with
The cathode and current sampling resistor R of adjustable DC power supplyIOne end be connected and be grounded, current sampling resistor RIThe other end with
The source electrode and sampled-data control system of measured power MOSFET element are connected, and the grid of measured power MOSFET element connects sampling control
The switch control signal that system processed provides；
The sampled-data control system includes amplifier module, A/D module, CPU module, drive module and host computer；Wherein:
The amplifier module flows through R for receivingICurrent signal and RU1Voltage signal, and respectively to this two groups
Signal carries out conditioning shaping；
The A/D module be used for conditioning shaping after current signal and voltage signal carry out AD sampling；
The CPU module includes CPLD (Complex Programmable Logic Device, complex programmable logic
Device) and static storage module, wherein CPLD generates corresponding pulse signal after receiving the test instruction that host computer exports, the arteries and veins
It rushes signal and generates corresponding switch control signal after drive module power amplification and export to measured power MOSFET element
Grid, to control the switch state of measured power MOSFET element, while CPLD also receives the sampled signal number of A/D module output
According to and store into static storage module, CPLD transfers sampled signal data and is delivered to from static storage module when needed
Host computer；
The host computer is used to receive the test parameter of user setting input and refers to export corresponding test to CPU module
It enables, receives the sampled signal data that CPU module provides to which real-time display measured power MOSFET element is tested in avalanche capability
The voltage waveform between hourglass source electrode and the current waveform of Drain-Source is flowed through in the process, judges measured power MOSFET element
Whether avalanche breakdown occurs, the avalanche capability of measured power MOSFET element, conducting resistance and defeated are calculated according to voltage and current
Capacitor out.
Further, the test instruction of the host computer output includes test condition parameters and test pattern, wherein testing
Conditional parameter includes that the output voltage of adjustable DC power supply, the inductance value size of controllable impedance and pulse width, test pattern are
The test of single pulse avalanche capability or the test of repetition pulse avalanche capability.
Further, the amplifier module includes sampled voltage conditioning circuit and sample rate current conditioning circuit.
The sampled voltage conditioning circuit includes two operational amplifier U1~U2, seven resistance R1~R7 and three electricity
Hold C1~C3；Wherein, a termination voltage signal of resistance R1, the other end of resistance R1 and one end of resistance R2 and operation
The non-inverting input terminal of amplifier U1 is connected, and the other end of resistance R2 is connected with one end of one end of resistance R3 and capacitor C1, electricity
Hold the other end ground connection of C1, the operating voltage of another termination+5V of resistance R3, the inverting input terminal and output of operational amplifier U1
End is connected and one end of connecting resistance R7, the other end and one end of resistance R5, one end of capacitor C3 and the operation amplifier of resistance R7
The inverting input terminal of device U2 is connected, the output end phase of the other end of resistance R5 and the other end of capacitor C3 and operational amplifier U2
Connect and export the voltage signal after conditioning shaping, one end of the non-inverting input terminal of operational amplifier U2 and resistance R4, capacitor C2
One end and one end of resistance R6 are connected, and the other end of resistance R4 is connected and is grounded with the other end of capacitor C2, and resistance R6's is another
The operating voltage of one termination+5V.
The sample rate current conditioning circuit includes two operational amplifier U3~U24, four resistance R8~R11 and one
Capacitor C4；Wherein, the homophase input of operational amplifier U3 terminates the current signal, the inverting input terminal of operational amplifier U3 with
One end of one end of resistance R9, one end of capacitor C4 and resistance R8 is connected, and the other end ground connection of resistance R8, resistance R9's is another
End is connected with one end of the other end of capacitor C4, the output end of operational amplifier U3 and resistance R10, the other end of resistance R10
It is connected with one end of the non-inverting input terminal of operational amplifier U4 and resistance R11, the other end ground connection of resistance R11, operation amplifier
The inverting input terminal and output end of device U4 connects altogether and exports the current signal after conditioning shaping.
Further, the host computer calculates the avalanche capability of measured power MOSFET element according to following relationship；
Wherein: E is the avalanche capability of measured power MOSFET element, and L is the inductance value size of controllable impedance, VCCIt is adjustable
The output voltage of DC power supply, IASTo flow through the electric current of measured power MOSFET element Drain-Source in tpReach in period
Peak value, BVdsEnter breakdown potential of the avalanche condition (i.e. pulse falling edge rise) afterwards between hourglass source electrode for measured power MOSFET element
Pressure, tpCorrespond to pulse width time section (i.e. measured power MOSFET element turn-on time section).
Further, the host computer calculates the conducting resistance of measured power MOSFET element according to following relationship；
Wherein: Rds(on)For the conducting resistance of measured power MOSFET element, VdsFor tpMOSFET element is tested in period
Voltage between hourglass source electrode, IdFor tpThe electric current of measured power MOSFET element Drain-Source, t are flowed through in periodpIt corresponds to
Pulse width time section.
Further, the host computer calculate measured power MOSFET element output capacitance the specific implementation process is as follows:
(1) due to the electricity between measured power MOSFET element in avalanche capability test process after shut-off its hourglass source electrode
Damped oscillation can occur for corrugating, therefore N number of continuous sampled point X is intercepted out of this voltage signal damped oscillation wave band1~XNAs
Sample sequence, N are the natural number greater than 1；
(2) according to the following formula to this N number of sampled point X1~XNVoltage value pre-processed；
V'(Xi)=V (Xi)-VCC
Wherein: V'(Xi) and V1(Xi) it is respectively pretreatment front and back sampled point XiVoltage value, i be natural number and 0≤i≤
N, VCCFor the output voltage of adjustable DC power supply；
(3) for this N number of sampled point X1~XNPretreated voltage waveform is somebody's turn to do by the method for seeking maximum
Wave crest in voltage waveform each cycle of oscillation, is obtained 2n wave crest, and n is the half of the voltage waveform cycle of oscillation number；
(4) 2n wave crest is divided into two groups, seeks cycle of oscillation T using by poor methodd, specific algorithm formula is as follows:
Wherein: T1(1)、T1(2)…T1(n) generation time of n wave crest, T before corresponding to2(1)、T2(2)…T2(n) corresponding
For the generation time of rear n wave crest；
(5) measured power MOSFET element output capacitance C is finally calculated according to the following formulaoss；
Wherein: L is the inductance value size of controllable impedance.
Based on the above-mentioned technical proposal, the present invention has following advantageous effects:
1. the present invention is based on the power MOSFET device conducting resistance of attenuation oscillasion impulse and the test method of output capacitance,
Measurement method is easy, and installation cost is lower.
2. the avalanche capability, conducting resistance and output capacitance that measure power MOSFET device simultaneously may be implemented in the present invention,
It is easy to operate efficient.
Detailed description of the invention
Fig. 1 is the equivalent model figure of power MOSFET device to be measured.
Fig. 2 is the equivalent oscillation circuit schematic diagram in measuring circuit.
Fig. 3 is the circuit theory and structural schematic diagram of test device of the present invention.
Fig. 4 is the actual waveform schematic diagram of measured power MOSFET element dram-source voltage.
Fig. 5 is the waveform signal after pretreatment of measured power MOSFET element dram-source voltage damped oscillation wave band
Figure.
Fig. 6 is the electrical block diagram of amplifier module in test device of the present invention.
Fig. 7 is the measured power MOSFET element dram-source voltage in avalanche capability test process and flows through drain electrode-source
The waveform diagram of electrode current.
Specific embodiment
In order to more specifically describe the present invention, with reference to the accompanying drawing and specific embodiment is to technical solution of the present invention
It is described in detail.
As shown in figure 3, the power MOSFET device conducting resistance and output capacitance the present invention is based on attenuation oscillasion impulse are online
Test device, including front end avalanche test circuit and sample circuit and post-controlled module.
The structure of front end avalanche test circuit 101 include adjustable DC power supply V, fuse, controllable impedance L1, to power scale
MOSFET element and current sampling resistor RI；Adjustable DC power supply V anode is connect with fuse；The other end and inductance of fuse
L1 connection；The other end of inductance L1 is connect with the drain electrode of MOSFET element to be measured；The source electrode of MOSFET element to be measured is adopted with electric current
Sample resistance RIConnection；Current sampling resistor RIThe other end connect with the cathode of ground line and adjustable DC power supply V；It is to be measured
The grid of MOSFET element receives pulse signal；In the present embodiment, adjustable DC power supply V adjustable range is 0~100V, can commissioning
Examination inductance L1 adjustable range is 0~30mH.
The structure of rear end avalanche voltage current sampling circuit and control module includes current sampling resistor RI, voltage sample electricity
Hinder RU1, divider resistance RU2, amplifier module 102, A/D module 103, drive module 104, CPU module 105 and host computer 106；It is to be measured
The source electrode and current sampling resistor R of MOSFET elementIConnection；Current sampling resistor RIThe other end and ground line and adjustable DC
The cathode of power supply V connects；CPU module 105 is connect with drive module 104；Amplifier module 102 receives sampled voltage signal and sampling
Current signal, and conditioning shaping is carried out to signal, detectable voltage signals and sensed current signal are exported, is exported to A/D module 103,
A/D module 103 carries out analog-to-digital conversion, output to CPU module 105 according to the detectable voltage signals and sensed current signal received；
Host computer 106 is communicated with CPU module 105.
Avalanche voltage current sampling circuit includes power MOSFET device source electrode to be measured and current sampling resistor RIOne end
It is connected, current sampling resistor RIThe other end ground connection；Divider resistance in parallel between power MOSFET device drain electrode to be measured and source electrode
RU2With voltage sample resistance RU1.In the present embodiment, current sampling resistor RIUsing milliohm rank, voltage sample resistance RU1Using
Megaohm rank.
As shown in fig. 6, amplifier module 102 includes voltage amplifier module and electric current amplifier module, voltage amplifier module is by seven
A resistance R1~R7, three capacitor C1~C3 and two operational amplifier U1~U2 are constituted, wherein one end of resistance R1 is used as and adopts
The other end of sample voltage signal inputs, resistance R3 is connected with the electrode input end of one end of resistance R2 and operational amplifier U1,
The other end of resistance R2 is connected with one end of one end of resistance R3, capacitor C1, and the other end ground connection of capacitor C1, resistance R3's is another
Termination+5V supply voltage, the output end of the reverse input end of operational amplifier U1 and one end of resistance R7 and operational amplifier U1
It is connected, one end of resistance R4, one end of capacitor C2 are connected with the positive input of one end of resistance R3 and operational amplifier U2, electricity
The other end of the other end and capacitor C2 that hinder R4 is grounded, and the supply voltage of another termination+5V of resistance R6, resistance R7's is another
End, resistance R5 one end be connected with the reverse input end of one end of capacitor C3 and operational amplifier U2, the other end of resistance R5 and
The other end of capacitor C3 is connected with the output end of operational amplifier U2 to be constituted the output end of voltage amplifier module and exports detection electricity
Press signal.
Electric current amplifier module is made of four resistance R8~R11, a capacitor C4 and two operational amplifier U3~U4,
The positive input of middle operational amplifier U3 is as sampled voltage signal input part, reverse input end, the electricity of operational amplifier U3
One end of resistance R9 is connected with one end of one end of capacitor C4 and resistance R8, the other end ground connection of resistance R8, the other end of resistance R9,
The other end of capacitor C4 is connected with the output end of one end of resistance R10 and operational amplifier U3, the other end and resistance of resistance R10
One end of R11 is connected with the positive input of operational amplifier U4, and the other end ground connection of resistance R11, operational amplifier U4's is anti-
It is connected to input terminal with the output end of operational amplifier U4 and constitutes the output end of current sampling module and export sensed current signal.
A/D module 103 is connected with amplifier module 102 comprising voltage analog to digital conversion circuit and electric current analog to digital conversion circuit,
Voltage analog to digital conversion circuit and electric current analog to digital conversion circuit receive the detection voltage letter after amplifier module 102 improves shaping respectively
Number and sensed current signal, while analog-to-digital conversion is carried out to signal and is exported to control module.In the present embodiment A/D module 103 by
Two pieces of A/D chip compositions, AD sampling A/D chip use the AD9220 chip of Analog Device company.
Control module includes CPU module 105 and host computer 106；CPU module 105 includes that CPLD control centre and static state are deposited
Module is stored up, after CPLD control centre receives the test signal that host computer 106 exports, pulse signal is generated and controls MOSFET device to be measured
Part open or by, and receive A/D module 103 output sampled data, store to static storage module, can also be deposited from static state
It stores up module and reads data, be delivered to host computer 106；Host computer 106 for set instruction and output order include test condition and
Test pattern, avalanche test receive the detection voltage and sensed current signal that CPU module 105 exports after starting, and show tested
Dram-source voltage waveform and the current waveform figure for flowing through Drain-Source, judgement in MOSFET element avalanche capability test process
Whether tested MOSFET element occurs avalanche breakdown, analyzes test waveform, realizes the calculating of tested MOSFET element avalanche energy.
In the present embodiment, CPU module 105 is made of a MCU chip, and static storage module is made of two pieces of static RAM chips, host computer
106 are constructed based on MATLAB platform, and MCU uses the EPM570T144C5N chip of altera corp, and static RAM chip is adopted
With the IS61WV102416BLL chip of ISSI company.
Control module output order includes the test condition of setting and the test pattern of selection, and test condition includes straight-adjustable
Flow electric power output voltage, controllable impedance test size and pulse width, test pattern include the test of single pulse avalanche energy and
The test of repetition pulse avalanche energy.
The power MOSFET device conducting resistance of avalanche capability test platform and output capacitance are used in present embodiment
Test method includes the following steps:
(1) column is correspondingly arranged in host computer 106 input the adjustable direct voltage source, adjustable that the test of this avalanche capability uses
The parameters such as test value, avalanche capability test pattern, the pulse width of inductance, adjustment and exact p-value circuit are consistent, send out after the completion
It send output order to CPU module 105, starts avalanche capability test.
(2) by taking the test of pulse avalanche energy as an example, after starting avalanche capability test, CPU module 105 receives avalanche capability
Test job condition and test mode signal, the single pulse signal of output setting width control amplifier mould to drive module
Block 102 and A/D module 103 are started to work.
(3) single pulse signal controls turning on and off for power MOSFET device to be measured through drive module, is connected on non-pincers
Power MOSFET device to be measured in the inductive circuit of position formally enters avalanche capability test phase, when power MOSFET device is connected
When, inductive current rises, and power MOSFET device turns off after a certain period of time, at this time dram-source voltage VdsIt rises rapidly, such as schemes
Shown in 7, the energy stored on inductance during opening is consumed by power MOSFET device.
(4) the sampled voltage signal of test phase and sampled current signals pass through A/D module after the amplification of amplifier module 102
103 analog-to-digital conversions are exported to CPU module 105, and CPU module 105 exports sample rate current and sampled voltage signal to host computer
106, host computer 106 receives data, shows MOSFET element leakage current to be measured and drain electrode-source in avalanche energy test process respectively
Pole tension waveform diagram, while showing corresponding peak point current IASWith voltage BVds.Measured power MOSFET device is judged by waveform diagram
Whether snowslide damages part, and when non-snowslide damage, power MOSFET device in this test is calculated according to following formula
Avalanche energy:
Wherein: L is the inductance value size of controllable impedance L1, VCCFor the output voltage of adjustable DC power supply, IASFor flow through by
The electric current of power scale MOSFET element Drain-Source is in tpThe peak value reached in period, BVdsFor measured power MOSFET element
Breakdown voltage between avalanche condition (i.e. pulse falling edge rises) afterwards hourglass source electrode, tpCorrespond to pulse width time section.
Tested MOSFET element avalanche energy is calculated and be shown in host computer 106, judges whether snowslide damages MOSFET to be measured.
(5) as shown in fig. 7, to tpVoltage and current in period is analyzed, induction charging, and the electric current flowed through gradually increases
Add, there are conducting resistance, the voltage of Drain-Source is gradually increasing tested MOSFET element with the variation of electric current, obtains tpTime
Conduction resistance value in section:
Wherein: VdsFor tpMOSFET element dram-source voltage, I are tested in perioddFor tpIt is tested in period
The electric current that MOSFET element Drain-Source flows through.
According to the resulting R of above-mentioned calculatingds(on)Waveform is drawn, can must be tested MOSFET element from beginning to turn on to tpTime
Curve interior, that conducting resistance changes over time.
(6) Fig. 1 is the equivalent model of common non-ideal MOSFET element, wherein Cgd、CgsAnd CdsRespectively grid, leakage
Interelectrode capacity between pole and source electrode, LdAnd LsRespectively drain electrode and source electrode parasitic inductance；RgFor parasitic gate resistance；Input electricity
Hold the relationship such as following formula with interelectrode capacity:
Coss=Cgd+Cds
Since power MOSFET device is there are parasitic antenna, loop resistance, MOSFET element output capacitance and ring when shutdown
Oscillating circuit is constituted between the inductance of road, as shown in Fig. 2, wherein RsumFor resistance value total in second-order circuit, LsumFor second-order circuit
In total inductance (since test inductance L is much larger than parasitic inductance, LsumIt can be approximately test inductance L).
When snowslide damage does not occur for tested MOSFET element, actual power MOSFET device avalanche test voltage waveform
Attenuation oscillasion impulse can be generated when off, as shown in Figure 4；Intercept the power MOSFET device Drain-Source that host computer 106 obtains
The damped oscillation wave band of voltage waveform is further analyzed, N number of continuous sampled point X of the attenuation oscillasion impulse signal of voltage signal1
~XNAs sample sequence, N is the natural number for being greater than 1 of unrestricted choice.
(7) according to following formula to N number of sampled point X1~XNVoltage value pre-processed, obtain the pre- place of sampled point
Manage voltage value:
V'(Xi)=V (Xi)-VCC
Wherein: V'(Xi) and V1(Xi) it is respectively pretreatment front and back sampled point XiVoltage value, i be natural number and 0≤i≤
N。
Sampled voltage attenuation oscillasion impulse shape after pretreatment is as shown in Figure 5；On the basis of N number of sample voltage data,
The wave crest in sampled voltage damped oscillation waveform each cycle of oscillation is obtained by the method for seeking maximum, but works as frequency of oscillation
When higher, there are deviations for the wave crest and actual waveform that capture, to increase error；In order to reduce such error, use
Cycle of oscillation T is sought by poor methodd。
The wave crest in N number of pretreated sampled voltage waveform in each cycle of oscillation is extracted, it is total 2n, 2n is a
Wave crest is divided into two groups, obtains cycle of oscillation T according to following formulad:
Wherein: T1(1)、T1(2)…T1(n) generation time of n wave crest, T before corresponding to2(1)、T2(2)…T2(n) corresponding
For the generation time of rear n wave crest.
(8) when being accurately cycle of oscillation, circuit equivalent resistance is obtained according to following formula:
Wherein: V1(1)、V1(2)…V1It (n) is respectively T1(1)、T1(2)…T1(n) corresponding voltage value, V2(1)、V2(2)…
V2It (n) is respectively T2(1)、T2(2)…T2(n) corresponding voltage value, TdTo calculate gained cycle of oscillation, LsumIt is gone here and there for the circuit of selection
Translocation tries inductance.
Sampled voltage attenuation oscillasion impulse expression formula after pretreatment are as follows:
u1(t)=Asin (ωdt+θ)e-bt
Wherein:
Equivalent circuit series capacitance C is obtained according to following formulasum, i.e., tested MOSFET power device output capacitance Coss:
The above-mentioned description to embodiment is for that can understand and apply the invention convenient for those skilled in the art.
Person skilled in the art obviously easily can make various modifications to above-described embodiment, and described herein general
Principle is applied in other embodiments without having to go through creative labor.Therefore, the present invention is not limited to the above embodiments, ability
Field technique personnel announcement according to the present invention, the improvement made for the present invention and modification all should be in protection scope of the present invention
Within.
Claims (8)
1. a kind of test device of power MOSFET device conducting resistance and output capacitance based on attenuation oscillasion impulse, feature exist
In: the sampled-data control system of measured power MOSFET element and its peripheral test circuit and rear end including front end；The survey
Trying circuit includes adjustable DC power supply, fuse, controllable impedance, voltage sample resistance RU1, divider resistance RU2With current sample electricity
Hinder RI, in which: the anode of adjustable DC power supply is connected with one end of fuse, the other end of fuse and one end of controllable impedance
It is connected, the other end of controllable impedance and the drain electrode of measured power MOSFET element and divider resistance RU2One end be connected, partial pressure
Resistance RU2The other end and voltage sample resistance RU1One end and sampled-data control system be connected, voltage sample resistance RU1It is another
The cathode and current sampling resistor R of one end and adjustable DC power supplyIOne end be connected and be grounded, current sampling resistor RIIt is another
One end is connected with the source electrode of measured power MOSFET element and sampled-data control system, and the grid of measured power MOSFET element connects
The switch control signal that sampled-data control system provides；
The sampled-data control system includes amplifier module, A/D module, CPU module, drive module and host computer；Wherein:
The amplifier module flows through R for receivingICurrent signal and RU1Voltage signal, and respectively to this two groups of signals
Carry out conditioning shaping；
The A/D module be used for conditioning shaping after current signal and voltage signal carry out AD sampling；
The CPU module includes CPLD and static storage module, and the test that wherein CPLD receives host computer output generates after instructing
Corresponding pulse signal, the pulse signal generate corresponding switch control signal after drive module power amplification and export to quilt
The grid of power scale MOSFET element, to control the switch state of measured power MOSFET element, while CPLD also receives AD mould
The sampled signal data of block output is simultaneously stored into static storage module, and CPLD is transferred from static storage module and adopted when needed
Sample signal data is simultaneously delivered to host computer；
The host computer is used to receive the test parameter that user setting inputs and instructs to export corresponding test to CPU module,
The sampled signal data that CPU module provides is received to which real-time display measured power MOSFET element is in avalanche capability test process
Whether voltage waveform between middle hourglass source electrode and the current waveform for flowing through Drain-Source, judge measured power MOSFET element
Avalanche breakdown occurs, the avalanche capability, conducting resistance and output electricity of measured power MOSFET element are calculated according to voltage and current
Hold.
2. test device according to claim 1, it is characterised in that: the test instruction of the host computer output includes test
Conditional parameter and test pattern, wherein test condition parameters include the inductance of the output voltage of adjustable DC power supply, controllable impedance
It is worth size and pulse width, test pattern is that single pulse avalanche capability is tested or repetition pulse avalanche capability is tested.
3. test device according to claim 1, it is characterised in that: the amplifier module includes sampled voltage conditioning circuit
With sample rate current conditioning circuit.
4. test device according to claim 3, it is characterised in that: the sampled voltage conditioning circuit includes two operations
Amplifier U1~U2, seven resistance R1~R7 and three capacitor C1~C3；Wherein, a termination of the resistance R1 voltage letter
Number, the other end of resistance R1 is connected with the non-inverting input terminal of one end of resistance R2 and operational amplifier U1, and resistance R2's is another
End is connected with one end of one end of resistance R3 and capacitor C1, the other end ground connection of capacitor C1, another termination+5V's of resistance R3
Operating voltage, the inverting input terminal of operational amplifier U1 is connected with output end and one end of connecting resistance R7, the other end of resistance R7
Be connected with the inverting input terminal of one end of resistance R5, one end of capacitor C3 and operational amplifier U2, the other end of resistance R5 with
The other end of capacitor C3 and the output end of operational amplifier U2 are connected and export the voltage signal after conditioning shaping, operation amplifier
The non-inverting input terminal of device U2 is connected with one end of one end of resistance R4, one end of capacitor C2 and resistance R6, and resistance R4's is another
End is connected and is grounded with the other end of capacitor C2, the operating voltage of another termination+5V of resistance R6.
5. test device according to claim 3, it is characterised in that: the sample rate current conditioning circuit includes two operations
Amplifier U3~U24, four resistance R8~R11 and a capacitor C4；Wherein, the homophase input of operational amplifier U3 terminates institute
State current signal, the inverting input terminal of operational amplifier U3 and the one of one end of resistance R9, one end of capacitor C4 and resistance R8
End is connected, the other end ground connection of resistance R8, the other end and the other end of capacitor C4, the output end of operational amplifier U3 of resistance R9
And one end of resistance R10 is connected, the other end of resistance R10 and the non-inverting input terminal of operational amplifier U4 and resistance R11's
One end is connected, the other end of resistance R11 ground connection, and the inverting input terminal and output end of operational amplifier U4 connects altogether and to export conditioning whole
Current signal after shape.
6. test device according to claim 1, it is characterised in that: the host computer calculates tested according to following relationship
The avalanche capability of power MOSFET device；
Wherein: E is the avalanche capability of measured power MOSFET element, and L is the inductance value size of controllable impedance, VCCFor adjustable DC
The output voltage of power supply, IASTo flow through the electric current of measured power MOSFET element Drain-Source in tpThe peak reached in period
Value, BVdsEnter the breakdown voltage after avalanche condition between hourglass source electrode, t for measured power MOSFET elementpWhen corresponding to pulse width
Between section.
7. test device according to claim 1, it is characterised in that: the host computer calculates tested according to following relationship
The conducting resistance of power MOSFET device；
Wherein: Rds(on)For the conducting resistance of measured power MOSFET element, VdsFor tpMOSFET element drain-source is tested in period
Voltage between pole, IdFor tpThe electric current of measured power MOSFET element Drain-Source, t are flowed through in periodpCorrespond to pulse
Spaced time section.
8. test device according to claim 1, it is characterised in that: the host computer calculates measured power MOSFET element
Output capacitance the specific implementation process is as follows:
(1) due to the voltage wave between measured power MOSFET element in avalanche capability test process after shut-off its hourglass source electrode
Damped oscillation can occur for shape, therefore N number of continuous sampled point X is intercepted out of this voltage signal damped oscillation wave band1~XNAs sampling
Sequence, N are the natural number greater than 1；
(2) according to the following formula to this N number of sampled point X1~XNVoltage value pre-processed；
V'(Xi)=V (Xi)-VCC
Wherein: V'(Xi) and V1(Xi) it is respectively pretreatment front and back sampled point XiVoltage value, i be natural number and 0≤i≤N, VCC
For the output voltage of adjustable DC power supply；
(3) for this N number of sampled point X1~XNPretreated voltage waveform obtains the voltage by the method for seeking maximum
Wave crest in waveform each cycle of oscillation, is obtained 2n wave crest, and n is the half of the voltage waveform cycle of oscillation number；
(4) 2n wave crest is divided into two groups, seeks cycle of oscillation T using by poor methodd, specific algorithm formula is as follows:
Wherein: T1(1)、T1(2)…T1(n) generation time of n wave crest, T before corresponding to2(1)、T2(2)…T2(n) after corresponding to
The generation time of n wave crest；
(5) measured power MOSFET element output capacitance C is finally calculated according to the following formulaoss；
Wherein: L is the inductance value size of controllable impedance.
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