CN109904234B - Nanowire fence device manufacturing method - Google Patents
Nanowire fence device manufacturing method Download PDFInfo
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- CN109904234B CN109904234B CN201910156942.1A CN201910156942A CN109904234B CN 109904234 B CN109904234 B CN 109904234B CN 201910156942 A CN201910156942 A CN 201910156942A CN 109904234 B CN109904234 B CN 109904234B
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Abstract
The application provides a nanowire wrap-gate device and a manufacturing method thereof, wherein a fin extending in a first direction can be formed on a substrate, a pseudo gate extending in a second direction and covering the middle of the fin is formed on the fin, a first side wall and a second side wall are sequentially formed on the side wall of the pseudo gate, covering layers are formed on the fins on two sides of the pseudo gate, the first side wall is removed to form a first opening, a second epitaxial layer in the first opening is removed to form a gap penetrating through the second epitaxial layer in the second direction, the second epitaxial layer in the fin is cut off to form three parts, a blocking layer made of a dielectric material is formed in the gap, the blocking layer can separate the three parts of the second epitaxial layer, the pseudo gate is removed to form a second opening, the blocking layer is used as an etching stop layer to remove the second epitaxial layer in the second opening, therefore, the second epitaxial layer on the other side of the blocking layer cannot be damaged, and the length of the formed gate is the length of the pseudo gate in the first direction, the gate length is accurately controlled, and therefore the device performance is improved.
Description
Technical Field
The present disclosure relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a nanowire wrap gate device and a manufacturing method thereof.
Background
With the continuous development of integrated circuit manufacturing processes, the critical dimensions of semiconductor devices, especially field effect transistors (MOSFETs), are continuously reduced, even to nodes below 10nm, the short channel effect of the devices is more and more significant, and the conventional planar devices have not been able to meet the requirements of the devices in terms of performance and integration level.
At present, a three-dimensional device structure is provided, and the gate control capability is improved by increasing the number of gates, so that the device has stronger driving current, and the short channel effect can be effectively inhibited. The nanowire surrounding gate device is a multi-gate device, the channel region of the nanowire is completely surrounded by the gate of the nanowire, the nanowire surrounding gate device has better gate control capability and lower energy consumption, and the nanowire surrounding gate device is the most potential solution for silicon-based devices with nodes of 10nm or below. However, in the conventional manufacturing process, it is difficult to control the long size of the gate, and in addition, the parasitic capacitance between the gate and the source is too large, which affects the device performance.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a nanowire wrap gate device and a method for manufacturing the same, which effectively controls the gate length and improves the device performance.
To achieve the above object, an embodiment of the present application provides a method for manufacturing a nanowire wrap gate device, including:
providing a substrate, wherein a fin extending along a first direction is formed on the substrate, and the fin comprises a first epitaxial layer and a second epitaxial layer which are alternately stacked;
forming a dummy gate on the fin extending along a second direction and covering a middle portion of the fin, the first direction and the second direction being orthogonal in a plane of the substrate;
sequentially forming a first side wall and a second side wall on the side wall of the pseudo gate, and forming covering layers on the fins on two sides of the pseudo gate;
removing the first side wall to form a first opening;
removing the second epitaxial layer in the first opening to form a gap penetrating the second epitaxial layer along the second direction;
forming a barrier layer of dielectric material in the gap;
removing the dummy gate to form a second opening;
and removing the second epitaxial layer in the second opening by taking the barrier layer as an etching stop layer.
Optionally, the first epitaxial layer is epitaxial silicon, and the second epitaxial layer is epitaxial germanium or epitaxial germanium-silicon.
Optionally, the removing the second epitaxial layer in the first opening includes:
performing multiple oxidation removal processes, wherein the oxidation removal processes comprise: performing an oxidation process on the second epitaxial layer to form an oxide layer on the surface of the second epitaxial layer exposed in the first opening; and removing the oxide layer.
Optionally, the removing the oxide layer includes:
removing the oxide layer by dry etching, wherein etching gas of the dry etching comprises C 4 F 8 、 C 4 F 6 Or C 4 F 6 And CF 4 The mixed gas of (2).
Optionally, performing an oxidation process on the second epitaxial layer includes:
and selectively oxidizing the second epitaxial layer by using plasma self-limiting oxygen.
Optionally, the method further includes:
and respectively forming a gate dielectric layer and a gate electrode which surround the first epitaxial layer in the second opening.
Optionally, the gate dielectric layer includes a high-k dielectric material, and the dielectric constant of the barrier layer is smaller than that of the gate dielectric layer.
Optionally, forming a barrier layer in the gap includes:
and filling the gap and the first opening with a dielectric material to respectively form a barrier layer and a substitute side wall.
Optionally, after forming the second sidewall and before forming the covering layer, the method further includes:
and epitaxially growing a source drain region on the fins on two sides of the dummy gate.
The embodiment of the present application further provides a nanowire wrap gate device, including:
a substrate;
the fin extends along a first direction on the substrate, the fin comprises first epitaxial layers which are stacked at intervals, the fin comprises a first region located in the middle and second regions located at two ends of the first region, and second epitaxial layers are formed in intervals among the first epitaxial layers of the second regions;
the gate dielectric layer surrounds the first epitaxial layer of the first region;
filling the space between the first epitaxial layers of the first region and extending the grid of the first epitaxial layer covering the first region along the second direction, wherein the first direction and the second direction are orthogonal in the plane of the substrate;
and the barrier layer is made of a dielectric material and extends from one end of the second epitaxial layer to the other end along the second direction.
Optionally, the gate dielectric layer includes a high-k dielectric material, and the dielectric constant of the barrier layer is smaller than that of the gate dielectric layer.
Optionally, the nano wrap gate device further includes: and the source and drain regions are formed on the side walls of the fins of the second region.
The embodiment of the application provides a nanowire wrap gate device and a manufacturing method thereof, a fin extending in a first direction can be formed on a substrate, the fin comprises a first epitaxial layer and a second epitaxial layer which are stacked alternately, a pseudo gate which extends in a second direction and covers the middle of the fin is formed on the fin, a first side wall and a second side wall are sequentially formed on the side wall of the pseudo gate, a covering layer is formed on the fin on two sides of the pseudo gate to protect the fins on two sides of the pseudo gate, a first opening is formed by removing the first side wall, a second epitaxial layer in the first opening is removed, a gap penetrating through the second epitaxial layer in the second direction is formed, a barrier layer made of a dielectric material is formed in the gap, the pseudo gate is removed to form a second opening, the barrier layer is used as an etching stop layer, and the second epitaxial layer in the second opening is removed. In the embodiment of the application, form first side wall between the fin of false gate position and false gate both sides, get rid of behind the second epitaxial layer under first side wall and the first side wall, the second epitaxial layer in the fin is cut off, form the triplex, after the position of original second epitaxial layer and first side wall formed the barrier layer, the barrier layer can separate the triplex second epitaxial layer, like this when the regional second epitaxial layer of sculpture false gate, just can not form the damage to the second epitaxial layer of barrier layer opposite side, thereby the gate length of formation is the length of false gate along the first direction, accurate control gate length, thereby improve the device performance.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following descriptions are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flowchart illustrating a manufacturing method of a nanowire wrap gate device according to an embodiment of the present application;
fig. 2-7 show schematic structural diagrams in a process of forming a nanowire wrap-gate device according to a manufacturing method of an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the device structures are not enlarged partially in general scale for the sake of illustration, and the drawings are only examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background art, at present, the gate control capability can be improved by increasing the number of gates, so that the device has a stronger driving current, and thus the short channel effect can be effectively suppressed.
In the manufacturing process of the nanowire, a fin formed by alternately laminating a first epitaxial layer and a second epitaxial layer may be formed on a substrate, a gap may be formed by removing a portion of the second epitaxial layer, a gate may be formed in the gap, and the first epitaxial layer may serve as the nanowire to form a structure in which the nanowire is surrounded by the gate. In practice, however, the size of the gate is not easily controlled, resulting in uncontrollable performance of the resulting device.
Based on the above technical problem, an embodiment of the present application provides a nanowire wrap gate device and a manufacturing method thereof, a fin extending in a first direction may be formed on a substrate, the fin includes a first epitaxial layer and a second epitaxial layer that are stacked alternately, a dummy gate extending in a second direction and covering a middle portion of the fin is formed on the fin, a first side wall and a second side wall are sequentially formed on a side wall of the dummy gate, a covering layer is formed on the fin on two sides of the dummy gate to protect the fin on two sides of the dummy gate, the first side wall is removed to form a first opening, the second epitaxial layer in the first opening is removed to form a gap penetrating through the second epitaxial layer in the second direction, a barrier layer of a dielectric material is formed in the gap, the dummy gate is removed to form a second opening, and the second epitaxial layer in the second opening is removed by using the barrier layer as an etching stop layer. In the embodiment of the application, form first side wall between the fin of false gate position and false gate both sides, get rid of behind the second epitaxial layer under first side wall and the first side wall, the second epitaxial layer in the fin is cut off, form the triplex, after the position of original second epitaxial layer and first side wall formed the barrier layer, the barrier layer can separate the triplex second epitaxial layer, like this when the regional second epitaxial layer of sculpture false gate, just can not form the damage to the second epitaxial layer of barrier layer opposite side, thereby the gate length of formation is the length of false gate along the first direction, accurate control gate length, thereby improve the device performance.
In order to better understand the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to flowchart 1 and fig. 2-7.
Referring to fig. 1, a method for manufacturing a nanowire wrap gate device according to an embodiment of the present application may include the following steps:
s101, providing a substrate 100, wherein a fin 110 extending along a first direction AA is formed on the substrate 100, and the fin 110 includes a first epitaxial layer 111 and a second epitaxial layer 112 that are alternately stacked, as shown in fig. 2.
In the embodiment of the present application, the substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator), a iii-v compound, a bi-iv compound semiconductor, or the like. In the present embodiment, the substrate 100 is an SOI substrate including a stack of silicon, silicon oxide, and silicon. The overlying silicon layer may serve as an epitaxial starting layer.
A fin 110 is formed on the substrate 100, and the formed fin 110 may include a first epitaxial layer 111 and a second epitaxial layer 112, which are sequentially stacked. Specifically, the first epitaxial layer 111 may be epitaxially grown on the substrate 100, and then the second epitaxial layer 112 may be epitaxially grown on the first epitaxial layer 111, and the growth process may be reduced pressure epitaxy or molecular beam epitaxy. Wherein, first epitaxial layer 111 can be epitaxial silicon layer, and second epitaxial layer 112 can be germanium base film layer, and is specific, and germanium base film layer can be epitaxial germanium layer, also can be epitaxial silicon germanium layer, and epitaxial silicon germanium still can be the stromatolite of germanium layer and silicon germanium layer, also can be for silicon germanium layer, germanium layer and the silicon germanium layer that stacks gradually, and wherein, silicon germanium layer can be as transition layer between germanium layer and the silicon layer, reduces the epitaxy degree of difficulty, improves epitaxial quality.
The formed nanowire may be a spaced multi-layered stacked structure, and the first epitaxial layer 111 and the second epitaxial layer 112 are alternately stacked a plurality of times to form a stacked structure of epitaxial layers, as shown in fig. 2. Specifically, for n layers of nanowires, n times of alternating stacking of the first epitaxial layer 111 and the second epitaxial layer 112 may be performed. In a specific embodiment, the thickness of the first epitaxial layer 11 may be 5nm to 50nm, and the thickness of the second epitaxial layer 112 may be 5nm to 50nm, wherein the content of germanium in the second epitaxial layer 112 may be 5% to 100%, and preferably, may be 5% to 30%.
After a first epitaxial layer 111 and a second epitaxial layer 112 are epitaxially grown on a substrate 100, the first epitaxial layer 111 and the second epitaxial layer 112 cover the entire substrate 100, etching is performed according to a hard mask pattern, and the first epitaxial layer 111 and the second epitaxial layer 112 outside an area where a fin 110 is located are removed to form the fin 110. The hard mask may be silicon nitride, silicon oxide, or a stack of silicon nitride and silicon oxide.
S102, forming a dummy gate 120 extending along a second direction BB on the fin 110 and covering a middle portion of the fin 110, and sequentially forming a first sidewall 130 and a second sidewall 140 on sidewalls of the dummy gate 120, wherein the first direction AA and the second direction BB are orthogonal in a plane of the substrate 100, as shown in fig. 2 and 3.
Forming a dummy gate 120 covering the middle of the fin 110 on the fin 110, which may be specifically, depositing a dummy gate material, etching the dummy gate material through an anisotropic etching process, and leaving the dummy gate material in the middle of the fin 110 to form the dummy gate 120, as shown in fig. 2. The dummy gate 120 may be, for example, polysilicon or monocrystalline silicon.
To protect the region outside the middle of the fin 110, a protective layer (not shown), such as a silicon oxide layer, may be formed on the fin 110 before depositing the dummy gate material, and the dummy gate material may be deposited after depositing the protective layer.
The forming of the first sidewall 130 on the sidewall of the dummy gate 120 may specifically be depositing a first sidewall material, etching the first sidewall material by an anisotropic etching process, and retaining the first sidewall material with a certain thickness on the sidewall of the dummy gate 120 to form the first sidewall 130. The material of the first sidewall 130 may be amorphous carbon, and the deposition manner of the first sidewall 130 may be Atomic Layer Deposition (ALD). During the etching process of the first sidewall material, the fin 110 may be protected by the protective layer on the fin 110.
Forming the second sidewall 140 on the sidewall of the dummy gate 120 may specifically be depositing a second sidewall material, and etching the second sidewall material by an anisotropic etching process, including forming the second sidewall 140 on the sidewall of the dummy gate 120 with a certain thickness. The second sidewall spacers 140 may be a single-layer or multi-layer structure, and may be a low-k dielectric material, such as a silicon nitride material. During the etching process of the second spacer material, the protective layer on the fin 110 may protect the fin 110.
It is understood that after the second sidewall 140 is formed with the first sidewall 130, the second sidewall 140 is outside the first sidewall 130. Of course, if the protective layer is formed on the fin 110, the protective layer may be removed after the second sidewall 140 is formed.
After forming the second sidewall spacers 140 on the sidewalls of the dummy gate 120, source and drain regions 150 may be further formed in the fin 110 on both sides of the dummy gate 120. Specifically, the source/drain regions 150 may be formed by ion implantation, epitaxial growth, or other suitable manners, and in the embodiment of the present application, silicon germanium may be selectively epitaxially grown on the exposed fins 110 on both sides of the dummy gate 120 as the source/drain regions 150, as shown in fig. 3.
S103, forming a capping layer 160 on the fin 110 on both sides of the dummy gate 120, and removing the first sidewall 130 to form a first opening 170, as shown in fig. 4 and 5.
A capping layer 160 is formed on the fins 110 on both sides of the dummy gate 120, and the capping layer 160 may protect the fins 110 therebelow, as shown with reference to fig. 4. Fig. 4A is a cross-sectional view along direction CC of fig. 4, where the cross-section is at the location of the cap layer 160, and the cross-section does not expose the stack of layers in the fin 110, as described with reference to fig. 4.
Specifically, the capping layer 160 may be formed on the top and sidewalls of the dummy gate 120, the first sidewall 130 and the second sidewall 140, so as to protect these regions in a later process. The capping layer 160 may be formed by deposition through a suitable deposition method, and the deposited capping layer may be planarized, for example, by a Chemical Mechanical Polishing (CMP) process to expose the dummy gate 120, so as to form the capping layer 160. The material of the capping layer 160 may be, for example, undoped silicon oxide (SiO) 2 ) Doped silicon oxide (e.g., borosilicate glass, borophosphosilicate glass, etc.), silicon nitride (Si) 3 N 4 ) Or other low k dielectric materials, etc.
After forming the cap layer 160, the first sidewall 130 may be removed to form a first opening 170, as shown in fig. 5, and fig. 5A is a cross-sectional view along the direction CC in fig. 5, wherein the cross-sectional view is at the cap layer 160 position, and the cross-section does not expose the stack of layers in the fin 110, as shown in fig. 5. As can be seen, the first sidewall 130 between the second sidewall 140 and the dummy gate 120 is removed, and a first opening 170 is formed. The method for removing the first side wall 130 may be dry etching, for example, by plasma etching.
S104, the second epitaxial layer 112 in the first opening 170 is removed to form a gap 170 'penetrating the second epitaxial layer 112 along the second direction BB, and a barrier layer 180 of a dielectric material is formed in the gap 170', as shown with reference to fig. 5 and 6.
After the etching process to remove the first sidewall 130, the fin 110 under the first sidewall 130 is exposed, so that the exposed second epitaxial layer 112 in the fin 110 can be removed by using the dummy gate 120, the second sidewall 140 and the covering layer 160 as masks, thereby forming a gap 170' along the second direction BB and penetrating the second epitaxial layer 112, as shown in fig. 5B, where fig. 5B is a cross-sectional view of DD in fig. 5, where the cross-sectional view is at the position of the fin 110, and the cross-section exposes the stack of the fin 110, as shown in fig. 5. The gap 170' may divide the second epitaxial layer 112 into three portions in the second direction BB, i.e., the second epitaxial layer 112 in the fin 110 under the capping layer 160 on both sides and the second epitaxial layer 112 in the fin 110 under the dummy gate 120.
In the embodiment of the present invention, the second epitaxial layer 112 in the first opening 170 is removed by wet etching the germanium-based film layer, for example, by hydrogen peroxide H 2 O 2 Hydrofluoric acid HF and acetic acid CH 3 The mixed COOH solution etches the second epitaxial layer 112, and also can etch through gas molecular reaction, for example, etching germanium layer at high temperature through chloric acid HCl gas.
In the embodiment of the present application, preferably, the second epitaxial layer 112 in the first opening 170 is removed, and may also be removed by a multiple oxidation removal process. The oxidation removal process, specifically, may be performed by performing an oxidation process of the second epitaxial layer 112 to form an oxide layer on the surface of the second epitaxial layer 112 included in the first opening, and then removing the oxide layer on the second epitaxial layer 112.
The oxidation process of the second epitaxial layer 112 may specifically be to selectively oxidize the second epitaxial layer 112 by using plasma self-limited oxygen, and in this process, the second epitaxial layer 112 is more oxidized than the first epitaxial layer 111. Wherein the oxidant may be oxygen O 2 Or ozone O 3 . After the oxide layer is grown on the second epitaxial layer 112, the grown oxide may be precisely etched using the etching gas. Specifically, the oxide layer can be removed by dry etching, and the etching gas of the dry etching comprises C 4 F 8 Gas, C 4 F 6 Gas, or C 4 F 6 And CF 4 The mixed gas has higher etching speed and higher selection ratio to the oxide of the germanium-based film layer.
In the oxidation removal process, the second epitaxial layer 112 is oxidized within a certain thickness, and the first epitaxial layer 111 is less oxidized, so that the oxide of the generated second epitaxial layer 112 can be etched, the selective etching gas has a larger etching selectivity for the second epitaxial layer 112 and the first epitaxial layer 111, and the oxide of the first epitaxial layer 111 or the oxide of the first epitaxial layer 111 cannot be excessively removed in the etching process, so that the oxide can be oxidized and removed many times, and the fast and accurate etching can be realized, and generally, the etching accuracy can be accurate to the quasi-atomic level.
Preferably, the thickness of the oxide layer after each oxidation can be controlled to be 1-10A by controlling process parameters in the oxidation process, and the etching precision can be accurately controlled to be quasi-atomic level by etching with high selection ratio and repeating the steps of oxidation and etching.
In some embodiments, the first epitaxial layer 111 is silicon and has a thickness of 5nm to 50nm, and the second epitaxial layer 112 is silicon germanium and has a thickness of 5nm to 50nm, wherein the germanium content may be 5% to 100%. In the oxidation process, the air pressure can be controlled to be 5-100 mT, the radio frequency power is 100-1000W, the oxygen flow is 5-200 sccm, the time is 1-10 s, and the substrate temperature is 0-150 ℃, so that the thickness of an oxide layer after oxidation each time can be controlled to be 1-10A.
In these particular embodiments, different etch gases and etch processes may be used to achieve precise etching. In some applications, by C 4 F 8 The gas etches the oxide on the second epitaxial layer 112, and the specific implementation can control the gas pressure to be 5-100 mT, the radio frequency power is 100-1000W, C 4 F 8 The gas flow is 5 sccm-200 sccm, the duration is 1-10, the substrate temperature is controlled at 0-150 ℃, C 4 F 8 The etch selectivity of the gas to the second epitaxial layer 112 and the first epitaxial layer 111 is typically greater than 10:1, which removes the oxide layer formed on the second epitaxial layer 112. Since the thickness of the oxide layer generated each time is 1 to 10A, the thickness of the oxide layer etched each time is 1 to 10A, that is, the thickness of the second epitaxial layer 112 etched each time is 1 to 10A.
In other applications, by C 4 F 6 Gas and CF 4 The gas etches the oxide on the second epitaxial layer 112, and the pressure can be controlled to be 5-100 mT, the radio frequency power is 100-1000W, C 4 F 6 The flow rate of the gas is 5 sccm-200 sccm, and CF is introduced at the same time 4 The flow rate of the gas is 5 sccm-200 sccm, the duration is 1-10 s, and the substrate temperature is controlled to be 0-150 ℃, so that the generated second epitaxial layer 112 can be oxidizedThe layer is removed.
In still other applications, by C 4 F 6 The gas etches the oxide on the second epitaxial layer 112, and the pressure can be controlled to be 5-100 mT, the radio frequency power is 100-1000W, C 4 F 6 The flow rate of the gas is 5 sccm-200 sccm, the duration is 1-10 s, and the substrate temperature is controlled at 0-150 ℃, so that the generated oxide layer on the second epitaxial layer 112 can be removed.
After forming the gap 170 'through the second epitaxial layer 112, a barrier layer 180 may also be formed in the gap 170', as shown with reference to fig. 6 and 6A, fig. 6A being a cross-sectional view along direction DD in fig. 6, where the cross-sectional location is at the location of the fin 110, and the cross-section exposes the stack of fins 110, as shown with reference to direction DD in fig. 5. Specifically, the gap 170' and the first opening 170 may be filled with a dielectric material to form the barrier layer 180 and the substitute sidewall spacer, respectively, where the dielectric material may be a material with a lower dielectric constant, or a dielectric material with a lower dielectric constant than the high-k dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. The barrier layer 180 may be deposited by any suitable deposition method and the deposited barrier layer may be planarized.
S105, removing the dummy gate 120 to form a second opening, and removing the second epitaxial layer 112 in the second opening by using the barrier layer 180 as an etching stop layer, as shown in fig. 7.
Since the barrier layer 180 is along the second direction BB and divides the second epitaxial layer 112 into three portions, i.e., the second epitaxial layer 112 in the fin 110 under the capping layer 160 on both sides and the second epitaxial layer 112 in the fin 110 under the dummy gate 120, after the dummy gate 120 is removed, the fin 110 under the dummy gate 129 is exposed in the second opening, so that etching of the second epitaxial layer 112 in the second opening can be performed to release the first epitaxial layer 111. The manner of etching the second epitaxial layer 112 may be wet etching, dry etching, or the above-mentioned multiple oxidation removal process. In addition, during the etching process of the second epitaxial layer 112, the barrier layer 180 may serve as an etch stop layer, so that the etching process for the second epitaxial layer 112 may not extend to the other side of the barrier layer 180, and the etching width of the second epitaxial layer 112 in the AA direction may be controlled.
After etching the second epitaxial layer 112 in the second opening, a gap 170' is formed through the second epitaxial layer 112, and the remaining first epitaxial layer 111 is layered. In the embodiment of the present application, partial etching or modification of the first epitaxial layer 111 may be performed according to actual needs, so that the remaining first epitaxial layer 111 has a desired size and/or linear morphology, and further, the first epitaxial layer 111 having a cylindrical or elliptic cylindrical morphology may be used as a nanowire channel.
In the embodiment of the present application, a gate dielectric layer (not shown) and a gate electrode 190 may be further formed in the second opening, respectively, and surround the first epitaxial layer, as shown in fig. 7. Wherein the gate dielectric layer comprises a high-k dielectric material and the barrier layer 180 may be selected from a dielectric material having a dielectric constant less than that of the gate dielectric layer. After the gate electrode 190 is formed, steps such as deposition of a covering layer, contact between a source drain electrode and a gate electrode, and the like may be performed to form a nanowire wrap gate device.
After the nano wrap gate device is formed, since the blocking layer 180 is formed between the gate and the second side 140, which is equivalent to the second sidewall 140 and the blocking layer 180 are formed between the source and the gate, and the dielectric constant of the blocking layer 180 is small, the capacitance of the parasitic capacitance between the source and the gate is small, that is, the blocking layer 180 can be used as an etching stop layer of the second epitaxial layer 112 of the gate region, and can also reduce the parasitic capacitance between the source and the gate, thereby improving the performance of the device.
The embodiment of the application provides a manufacturing method of nanowire wrap gate device, the fin that can be formed with the first direction extension on the substrate, the fin includes first epitaxial layer and the second epitaxial layer of alternate stack-up, form the pseudo-gate that extends and cover the middle part of fin along the second direction on the fin, form first side wall and second side wall on the lateral wall of pseudo-gate in proper order, and form the fin of overburden in order to protect the pseudo-gate both sides on the fin of pseudo-gate both sides, it forms first opening to get rid of first side wall, get rid of the second epitaxial layer in the first opening, in order to form the clearance that runs through the second epitaxial layer along the second direction, form dielectric material's barrier layer in the clearance, get rid of pseudo-gate in order to form the second opening, use the barrier layer as the etching stop layer, get rid of the second epitaxial layer in the second opening. In the embodiment of the application, form first side wall between the fin of false gate position and false gate both sides, get rid of behind the second epitaxial layer under first side wall and the first side wall, the second epitaxial layer in the fin is cut off, form the triplex, after the position of original second epitaxial layer and first side wall formed the barrier layer, the barrier layer can separate the triplex second epitaxial layer, like this when the regional second epitaxial layer of sculpture false gate, just can not form the damage to the second epitaxial layer of barrier layer opposite side, thereby the gate length of formation is the length of false gate along the first direction, accurate control gate length, thereby improve the device performance.
Based on the above method for manufacturing a nanowire wrap gate device, an embodiment of the present application further provides a nanowire wrap gate device, and as shown in fig. 7, the nanowire wrap gate device provided in the embodiment of the present application includes:
a substrate 100;
a fin 110 extending in a first direction on the substrate 100, the fin 110 including first epitaxial layers 111 stacked at intervals, the fin 110 including a first region located in a middle portion and second regions located at two ends of the first region, a second epitaxial layer 112 being formed in an interval between the first epitaxial layers 111 of the second regions;
a gate dielectric layer surrounding the first epitaxial layer 111 of the first region;
a gate 190 filling a space between the first epitaxial layers 111 of the first region and extending to cover the first epitaxial layers of the first region along the second direction, the first direction and the second direction being orthogonal in a plane of the substrate;
a barrier layer 180 between the gates in the space between the second epitaxial layer 112 and the first epitaxial layer 111 of the first region, the barrier layer 180 being a dielectric material and extending from one end of the second epitaxial layer to the other along the second direction.
Optionally, the gate dielectric layer includes a high-k dielectric material, and the dielectric constant of the barrier layer is smaller than that of the gate dielectric layer.
Optionally, the nano wrap gate device further includes: and source and drain regions formed on sidewalls of the fin 110 of the second region.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the memory device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference may be made to the partial description of the method embodiments for relevant points.
The foregoing is merely a preferred embodiment of the present application and, although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application are still within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (9)
1. A method of fabricating a nanowire wrap gate device, comprising:
providing a substrate, wherein a fin extending along a first direction is formed on the substrate, and the fin comprises a first epitaxial layer and a second epitaxial layer which are alternately stacked;
forming a dummy gate on the fin extending along a second direction and covering a middle portion of the fin, the first direction and the second direction being orthogonal in a plane of the substrate;
sequentially forming a first side wall and a second side wall on the side wall of the pseudo gate, and forming covering layers on the fins on two sides of the pseudo gate;
removing the first side wall to form a first opening;
removing the second epitaxial layer in the first opening to form a gap penetrating through the second epitaxial layer along the second direction;
forming a barrier layer of dielectric material in the gap;
removing the dummy gate to form a second opening;
and removing the second epitaxial layer in the second opening by taking the barrier layer as an etching stop layer.
2. The method of manufacturing of claim 1, wherein the first epitaxial layer is epitaxial silicon and the second epitaxial layer is epitaxial germanium or epitaxial silicon germanium.
3. The method of manufacturing of claim 2, wherein the removing the second epitaxial layer in the first opening comprises:
performing multiple oxidation removal processes, wherein the oxidation removal processes comprise: performing an oxidation process on the second epitaxial layer to form an oxide layer on the surface of the second epitaxial layer exposed in the first opening; and removing the oxide layer.
4. The method of manufacturing according to claim 3, wherein the removing the oxide layer includes:
removing the oxide layer by dry etching, wherein etching gas of the dry etching comprises C 4 F 8 、C 4 F 6 Or C 4 F 6 And CF 4 The mixed gas of (1).
5. The method of manufacturing of claim 3, wherein performing the oxidation process of the second epitaxial layer comprises:
and selectively oxidizing the second epitaxial layer by using plasma self-limiting oxygen.
6. The manufacturing method according to claim 1, further comprising:
and respectively forming a gate dielectric layer and a gate electrode which surround the first epitaxial layer in the second opening.
7. The method of claim 6, wherein the gate dielectric layer comprises a high-k dielectric material, and the barrier layer has a dielectric constant less than that of the gate dielectric layer.
8. The method of manufacturing of claim 1, wherein forming a barrier layer in the gap comprises:
and filling the gap and the first opening with a dielectric material to respectively form a barrier layer and a substitute side wall.
9. The method of manufacturing according to claim 1, wherein after forming the second sidewall and before forming the capping layer, further comprising:
and epitaxially growing source and drain regions on the fins on two sides of the dummy gate.
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