CN109901880B - Spinlock hardware circuit and electronic equipment - Google Patents
Spinlock hardware circuit and electronic equipment Download PDFInfo
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- CN109901880B CN109901880B CN201910151740.8A CN201910151740A CN109901880B CN 109901880 B CN109901880 B CN 109901880B CN 201910151740 A CN201910151740 A CN 201910151740A CN 109901880 B CN109901880 B CN 109901880B
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Abstract
The invention discloses a spinlock hardware circuit and an electronic device, wherein the hardware circuit comprises a safety protection unit, an address judgment unit, a write data judgment unit, a write judgment unit, a read control unit and a spinlock state register unit, wherein: the safety protection unit is used for monitoring whether the read-write access sent by the bus is the safety access sent by the CPU, responding if the read-write access is the safety access, and otherwise rejecting the access request of the bus; the address judging unit is used for inquiring the bus write address, converting the write address of the bus into the selection information corresponding to the spinlock register unit to be accessed, and sending the conversion result to the write data judging unit and the write judging unit. According to the technical scheme, the spinlock control algorithm is realized through hardware, and software control is simple. A higher level of security protection is achieved by a hardware level of security access control. Hardware control is also faster than software control.
Description
Technical Field
The invention relates to the field of hardware circuits, in particular to a spinlock hardware circuit and electronic equipment.
Background
With the rapid development of the multi-core processor, a processing mechanism when the multi-core processor concurrently processes becomes more and more important. Spinlock is an important and effective mechanism for avoiding errors in multi-core parallel processing. However, the current spinlock treatment has more obvious problems. Firstly, software control is complex, spinlock needs to designate a storage area as an area for storing the lock state, and the method of designating the area by software in the memory is complex in software control and insufficient in safety degree, and is easy to be broken by hackers. But the software processing operation speed is also relatively slow.
Disclosure of Invention
Therefore, a spinlock hardware circuit and an electronic device are needed to be provided, and the problems that the safety degree of the existing spinlock is insufficient and the software control is complex are solved.
In order to achieve the above object, the inventor provides a spinlock hardware circuit, including a security protection unit, an address judgment unit, a write data judgment unit, a write judgment unit, a read control unit, and a spinlock status register unit, wherein:
the safety protection unit is used for monitoring whether the read-write access sent by the bus is the safety access sent by the CPU, responding if the read-write access is the safety access, and otherwise rejecting the access request of the bus;
the address judging unit is used for inquiring the bus write address, converting the write address of the bus into the selection information corresponding to the spinlock register unit to be accessed, and sending the conversion result to the write data judging unit and the write judging unit;
the write data judging unit is used for judging whether the spinlock register needs to be written or not and sending a judgment result to the write judging unit;
the write judging unit writes the spinlock register according to the register unit selection information input by the address judging unit and the judgment result whether the write can be performed and the write data sent by the write data judging unit;
the spinlock register unit is used for storing the lock state information of spinlock and sending the state information to the write data judging unit and the read control unit;
the read control unit is used for reading according to a read command of the bus.
Further, the device also comprises an address table storage unit which is used for storing the address of the spinlock register unit and used for the address judgment unit to inquire.
Further, an address random allocation unit is included for randomly allocating the address of the spinlock register unit,
further, the data writing unit comprises a path selection unit, a first all-zero judgment unit, a second all-zero judgment unit, a logical or unit and a path switch unit, wherein:
the path selection unit is used for gating the data state of the spinlock register unit according to the address judgment signal sent by the address judgment unit and sending the data state to the first all-zero judgment unit;
the first all-zero judging unit is used for judging whether the spinlock register state is all zero or not and sending a judging result to the logic OR unit;
the second all-zero judgment unit is used for judging whether the bus write data is all zero or not and sending a judgment result to the logic OR unit;
the logic OR unit is used for performing logic OR operation processing on the two input all-zero judgment results and sending the processing result to the access switch unit;
if the output result of the logic or unit is high, the data can be written, the path switch for writing the data is opened, if the output result is low, the data cannot be written, and the data writing path is closed.
Further, the safety protection unit is configured to determine a prot signal in a command sent by the bus, where a high prot signal indicates that the access is a safe access.
Further, the register unit comprises a spinlock state register group and a corresponding start-stop address.
The invention provides electronic equipment which comprises a spinlock hardware circuit, a bus and a processor, wherein the processor is connected with the spinlock hardware circuit through the bus, and the spinlock hardware circuit is the spinlock hardware circuit.
Different from the prior art, the technical scheme realizes the spinlock control algorithm through hardware, and software control is simple. A higher level of security protection is achieved by a hardware level of security access control. Hardware control is also faster than software control.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration according to an embodiment;
fig. 2 is a schematic structural diagram of a write data determining unit according to an embodiment.
Description of reference numerals:
101. a safety protection unit; 102. An address judging unit;
103. a write data judgment unit; 104. A write judgment unit;
105. a read control unit; 106. A spinlock status register unit;
107. an address table storage unit; 108. An address random allocation unit;
201. a path selection unit; 202. A first all-zero judgment unit;
203. a second all-zero judgment unit; 204. A logical OR unit;
205. a path switch unit.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 2, the present embodiment provides a spinlock hardware circuit, which includes a security protection unit 101, an address determination unit 102, a write data determination unit 103, a write determination unit 104, a read control unit 105, and a spinlock status register unit 106, wherein: the safety protection unit is used for monitoring whether the read-write access sent by the bus is the safety access sent by the CPU, responding if the read-write access is the safety access, and otherwise rejecting the access request of the bus; the address judging unit is used for inquiring the bus write address, converting the write address of the bus into the selection information corresponding to the spinlock register unit to be accessed, and sending the conversion result to the write data judging unit and the write judging unit; the write data judging unit is used for judging whether the spinlock register needs to be written or not and sending a judgment result to the write judging unit; the write judging unit writes the spinlock register according to the register unit selection information input by the address judging unit and the judgment result whether the write can be performed and the write data sent by the write data judging unit; the spinlock register unit is used for storing the lock state information of spinlock and sending the state information to the write data judging unit and the read control unit; the read control unit is used for reading according to a read command of the bus.
In the invention, the safety protection unit can judge the safety of the bus command, and the address judgment unit can operate the corresponding spinlock register unit. Whether to write control in spinlock can be realized by the write data judging unit and the write judging unit. The spinlock register unit realizes the storage of the lock state information of spinlock. The units realize the function of spinlock through hardware, and improve the speed. The software does not need to be controlled, and the use is convenient. And the safety protection unit is used for monitoring whether the read-write access is the safety access sent by the CPU or not, and responding only when the safety access is carried out. Therefore, the situation that data is broken when a hacker controls the CPU to directly access the circuit after breaking the CPU can be avoided. Only when a hacker breaks the entrance of the secure world, the security access can be sent out, so that the security defense capability is greatly improved through the security protection unit.
For background knowledge of the secure world and the non-secure world, reference may be made to the prior publications:
https://blog.csdn.net/zhouhuacai/article/details/78177364。
the address of the spinlock register unit of the present application may be directly stored in the address determination unit, or may be stored in a separate storage unit, and then the present invention further includes an address table storage unit 107, configured to store the address of the spinlock register unit for the address determination unit to query.
In some embodiments, the address of the spinlock register unit may be a fixed address. Or in some embodiments, the addresses are random for increased security. The hardware circuit of the present invention further includes an address random allocation unit 108 for randomly allocating an address of the spinlock register unit. The allocation timing may be when the circuit is powered on to operate, and the allocated address may be stored in a corresponding storage location, such as the address table storage unit in the above embodiment. Therefore, the physical registers corresponding to the same address can be ensured to be different when the circuit works every time, and the safety is ensured.
The data writing unit is used for judging that the spinlock register state is all zero and the bus data writing is all zero, and outputting a signal result which can be written to the writing judging unit. The specific hardware circuit can be realized as follows: the data writing unit comprises a path selecting unit 201, a first all-zero judging unit 202, a second all-zero judging unit 203, a logical or unit 204 and a path switching unit 205, wherein: the path selection unit is used for gating the state of the corresponding spinlock register unit according to the address judgment signal sent by the address judgment unit and sending the state to the first all-zero judgment unit; the first all-zero judging unit is used for judging whether the spinlock register state is all zero or not and sending a judging result to the logic OR unit; all zeros indicate that each bit of the register state is zero, and the output of all zeros is yes, and the output of all zeros is not no. The second all-zero judgment unit is used for judging whether the bus write data is all zero or not and sending a judgment result to the logic OR unit; similarly, all zeros indicate that each bit is zero, and a yes result is output when all zeros are not output. The logic OR unit is used for performing logic OR operation processing on the two input all-zero judgment results and sending the processing result to the access switch unit; if the output result of the logic or unit is high, namely one is all zero, the data can be written, a path switch for writing the data is opened, and if the output result is low, the data cannot be written, and a data writing path is closed. This achieves that when the spinlock register state is non-all-zero, it indicates that the CPU has used this state register set and therefore cannot be written with new data. Only when the spinlock register state is all zero, indicating that the CPU has not used this set of state registers, can the register set be written with new data. Then when the write data is all zero, any register set can be cleared.
The safety protection unit judges whether the access of the bus is safe or not, can judge whether the bus command meets a preset rule or contains a special signal or not, and if the bus command meets or contains the special signal, the bus command can be considered to be safe. Or the prot signal can be judged, the safety protection unit judges the prot signal in the command sent by the bus, if the prot signal is high, the access is safe access, a corresponding request can be made, otherwise, the request is not responded, and an error mark can be returned.
In order to realize the storage and corresponding functions of spinlock information, the register unit comprises a spinlock state register group and a corresponding start-stop address.
The invention provides electronic equipment which comprises a spinlock hardware circuit, a bus and a processor, wherein the processor is connected with the spinlock hardware circuit through the bus, and the spinlock hardware circuit is the spinlock hardware circuit. The spinlock hardware circuit of the electronic equipment realizes the spinlock control algorithm through hardware, and software control is simple. A higher level of security protection is achieved by a hardware level of security access control. Hardware control is also faster than software control.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (7)
1. The spinlock hardware circuit is characterized by comprising a safety protection unit, an address judgment unit, a write data judgment unit, a write judgment unit, a read control unit and a plurality of spinlock state register units, wherein:
the safety protection unit is used for monitoring whether the read-write access sent by the bus is the safety access sent by the CPU, responding if the read-write access is the safety access, and otherwise rejecting the access request of the bus;
the address judging unit is used for inquiring the bus write address, converting the write address of the bus into the selection information corresponding to the spinlock register unit to be accessed, and sending the conversion result to the write data judging unit and the write judging unit;
the write data judging unit is used for judging whether the spinlock register needs to be written or not and sending a judgment result to the write judging unit;
the write judging unit writes the spinlock register according to the register unit selection information input by the address judging unit and the judgment result whether the write can be performed and the write data sent by the write data judging unit;
the spinlock register unit is used for storing the lock state information of spinlock and sending the state information to the write data judging unit and the read control unit;
the read control unit is used for reading according to a read command of the bus.
2. The spinlock hardware circuit of claim 1, wherein: the device also comprises an address table storage unit which is used for storing the address of the spinlock register unit and used for the address judgment unit to inquire.
3. A spinlock hardware circuit as claimed in claim 1 or 2, wherein: the random allocation unit of the address is also included for randomly allocating the address of the spinlock register unit.
4. The spinlock hardware circuit of claim 1, wherein: the data writing unit comprises a path selection unit, a first all-zero judgment unit, a second all-zero judgment unit, a logic OR unit and a path switch unit, wherein:
the path selection unit is used for gating the data state of the spinlock register unit according to the address judgment signal sent by the address judgment unit and sending the data state to the first all-zero judgment unit;
the first all-zero judging unit is used for judging whether the spinlock register state is all zero or not and sending a judging result to the logic OR unit;
the second all-zero judgment unit is used for judging whether the bus write data is all zero or not and sending a judgment result to the logic OR unit;
the logic OR unit is used for performing logic OR operation processing on the two input all-zero judgment results and sending the processing result to the access switch unit;
if the output result of the logic or unit is high, the data can be written, the path switch for writing the data is opened, if the output result is low, the data cannot be written, and the data writing path is closed.
5. The spinlock hardware circuit of claim 1, wherein: the safety protection unit is used for judging a prot signal in a command sent by the bus, and if the prot signal is high, the access is safe access.
6. The spinlock hardware circuit of claim 1, wherein: the register unit comprises a spinlock state register group and a corresponding start-stop address.
7. An electronic device, characterized in that: the method comprises a spinlock hardware circuit, a bus and a processor, wherein the processor is connected with the spinlock hardware circuit through the bus, and the spinlock hardware circuit is the spinlock hardware circuit of any one of claims 1 to 6.
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| CN201910151740.8A CN109901880B (en) | 2019-02-28 | 2019-02-28 | Spinlock hardware circuit and electronic equipment |
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| CN201910151740.8A CN109901880B (en) | 2019-02-28 | 2019-02-28 | Spinlock hardware circuit and electronic equipment |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102473224A (en) * | 2009-12-22 | 2012-05-23 | 英特尔公司 | Method and apparatus to provide secure application execution |
| CN103902419A (en) * | 2014-03-28 | 2014-07-02 | 华为技术有限公司 | Method and device for testing caches |
| CN107357648A (en) * | 2017-05-25 | 2017-11-17 | 吕锦柏 | The implementation method of spin lock when a kind of multi-core CPU accesses resource |
| CN108875381A (en) * | 2017-05-15 | 2018-11-23 | 南京大学 | A kind of design scheme for the messaging service module for supporting kernel module to be isolated |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140282564A1 (en) * | 2013-03-15 | 2014-09-18 | Eli Almog | Thread-suspending execution barrier |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102473224A (en) * | 2009-12-22 | 2012-05-23 | 英特尔公司 | Method and apparatus to provide secure application execution |
| CN103902419A (en) * | 2014-03-28 | 2014-07-02 | 华为技术有限公司 | Method and device for testing caches |
| CN108875381A (en) * | 2017-05-15 | 2018-11-23 | 南京大学 | A kind of design scheme for the messaging service module for supporting kernel module to be isolated |
| CN107357648A (en) * | 2017-05-25 | 2017-11-17 | 吕锦柏 | The implementation method of spin lock when a kind of multi-core CPU accesses resource |
Non-Patent Citations (1)
| Title |
|---|
| 基于TrustZone的应用程序完整性保护研究与实现;袁野;《中国优秀硕士学位论文全文数据库 信息科技辑》;20180415(第4期);I138-147 * |
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