CN109887883A - A kind of array substrate and its manufacturing method - Google Patents
A kind of array substrate and its manufacturing method Download PDFInfo
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- CN109887883A CN109887883A CN201910114510.4A CN201910114510A CN109887883A CN 109887883 A CN109887883 A CN 109887883A CN 201910114510 A CN201910114510 A CN 201910114510A CN 109887883 A CN109887883 A CN 109887883A
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Abstract
The present invention provides a kind of array substrate and its manufacturing method, including pixel region and terminal region；Pixel region includes grid, gate insulating layer, metal oxide semiconductor layer, source electrode and drain electrode, and the first insulating layer, second insulating layer, common electrode, third insulating layer, pixel electrode, the 4th via hole, pixel electrode passes through the 4th via hole and drain electrode is connected；Terminal region includes grid, gate insulating layer, metal oxide semiconductor layer, source electrode and drain electrode, the first insulating layer, second insulating layer, third insulating layer, pixel electrode, the 5th via hole, and pixel electrode passes through the 5th via hole and gate turn-on.The present invention performs etching photoresist, third insulating layer, the first insulating layer by pixel region simultaneously, terminal region performs etching third insulating layer, the first insulating layer, gate insulating layer simultaneously, the influence that pixel region spends quarter to the first insulating layer, second insulating layer and drain surface can be reduced, impedance at via hole is reduced.
Description
Technical field
The present invention relates to display device manufacturing technology field, in particular to a kind of array substrate and its manufacturing method.
Background technique
Liquid crystal display device is a kind of current most popular panel display apparatus, and liquid crystal display panel includes opposite sets
The array substrate and color membrane substrates set, wherein array substrate is produced by multiple tracks patterning processes to forming multiple film figures
Shape, every one of patterning processes all include the techniques such as exposure mask, exposure, development, etching and removing, in order to reduce liquid crystal display panel
Price and the yield for improving product, technical staff are being dedicated to reducing the number of patterning processes.
In general, BCE technique generally uses 8 light shield techniques, by using MTM, (Multi-Tones Mask, masstone are covered
Film) technology, 8 original light shields can be reduced to 6 light shield techniques, but terminal region is used the in 6 light shield techniques
One inorganic insulation layer, the second inorganic insulation layer, three layers of gate insulating layer etch together, so that pixel electrode and grid be enable to lead
It is logical, since the first inorganic insulation layer of terminal region and the second inorganic insulation layer overall thickness areAnd pixel region first is inorganic absolutely
Edge layer and the second inorganic insulation layer overall thickness only haveWhen terminal region use by the first inorganic insulation layer, second it is inorganic absolutely
Edge layer, three layers of gate insulating layer when etching together, necessarily cause the first inorganic insulation layer of pixel region and the second inorganic insulation layer to go out
Existing 100% crosses and carves, and it is faster than the second inorganic insulation layer that pixel region crosses hole location organic insulator etch rate, organic insulation occurs
Layer is backwards to inside the second inorganic insulation layer and forms chamfering (Taper), and pixel electrode is easy to appear broken string in this chamfering position；This
Outside, there is the case where " hangnail " in the first inorganic insulation layer and the second inorganic insulation layer contact position, and surface irregularity is also easy to lead
Addressed pixel electrode breaks, to influence through hole impedance；More long because spending the time at quarter, drain (Drain) material C u table at via hole
Face will receive the influence of dry etching etching gas, and thinning phenomenon can occur for film thickness.
Summary of the invention
The object of the present invention is to provide a kind of array substrate and its manufacturing methods, it is intended to solve pixel electrode in prior art
It is easy to appear broken string crossing hole site, leads to the problem that through hole impedance is excessive.
The present invention provides a kind of manufacturing method of array substrate, and array substrate includes being located in the middle pixel region and positioned at side
The terminal region of edge, includes the following steps:
S1: grid is formed on the pixel region of glass substrate and terminal region respectively using the first metal；
S2: the gate insulating layer of covering grid is formed, semiconductor layer is formed above gate insulating layer, using the second metal
It forms the source electrode and drain electrode for being located at the semiconductor layer two sides of pixel region and forms the metal being located above the semiconductor layer of terminal
Contact layer, wherein the source electrode and drain electrode of pixel region with two side contacts of semiconductor layer, the metal contact layer of terminal region with partly lead
Body layer overlying contact；
S3: forming the first insulating layer of covering source electrode, drain electrode and metal contact layer, forms the second of the first insulating layer of covering
Insulating layer；Exposure falls the part second insulating layer above the drain electrode of pixel region and forms the first via hole for being located at drain electrode top；Together
When etch away terminal region metal contact layer two sides part second insulating layer and formed be located at metal contact layer two sides second
Via hole；
S4: forming common electrode above the second insulating layer of pixel region, etches away being total to above the first via hole of pixel region
Energization pole forms third via hole, while etching away the first insulating layer of part positioned at terminal region；
S5: covering forms third insulating layer on the basis of step S4, coats photoresist above third insulating layer；
S6: being exposed pixel region and terminal region photoresist using intermediate tone mask version, by the third via hole of pixel region
Interior photoresist Partial exposure falls, and the photoresist of the second via bottom of terminal region all remove by exposure, terminal region the second via hole side
Photoresist on wall still retains, and the photoresist above part metals contact layer all fall and form the contact of the first metal by exposure
Hole；
S7: performing etching photoresist, third insulating layer and the first insulating layer at the third via hole of pixel region simultaneously, is formed
The 4th via hole positioned at drain electrode top；Third insulating layer, the first insulating layer and gate insulating layer in second via hole of terminal region
It performs etching simultaneously and forms the 5th via hole above grid, while the third insulating layer and first above metal contact layer
Insulating layer performs etching the second metal contact hole to be formed above metal contact layer；
S8: photoresist on pixel region and terminal region third insulating layer is removed；
S9: covering semi-transparent conductive material on the basis of step S8, forms the pixel electricity for being located at pixel region and terminal region
Pole, pixel electrode are connected by the drain electrode of the 4th via hole and pixel region and are connected, and pixel electrode passes through the 5th via hole and terminal region grid
Pole connection conducting, pixel electrode are connect by the second metal contact hole with metal contact layer.
Further, first insulating layer and third insulating layer are inorganic insulation layer.
Further, the material of first insulating layer and third insulating layer is one kind or combination of silicon nitride and silica.
Further, the second insulating layer is organic insulator.
Further, the semiconductor layer is IGZO semiconductor.
The present invention provides a kind of array substrate, including pixel region and terminal region；Pixel region includes grid, is located above grid
Gate insulating layer, the metal oxide semiconductor layer above gate insulating layer, be located at metal-oxide semiconductor (MOS)
The source electrode and drain electrode of layer two sides, the first insulating layer above source electrode and drain electrode, second above the first insulating layer are absolutely
Edge layer, the common electrode above second insulating layer, the third insulating layer above common electrode and be located at third insulate
The pixel electrode of layer top, drain electrode top are provided with the 4th via hole, and pixel electrode is connected by the 4th via hole and drain electrode；Terminal region packet
Include grid, the gate insulating layer above grid, the semiconductor layer above gate insulating layer, on semiconductor layer
Source electrode and drain electrode, the second insulating layer above the first insulating layer, is located at the first insulating layer above source electrode and drain electrode
Third insulating layer above second insulating layer, the pixel electrode above third insulating layer have the 5th via hole on grid, as
Plain electrode passes through the 5th via hole and gate turn-on.
Further, the metal oxide semiconductor layer is IGZO semiconductor.
Further, first insulating layer, third insulating layer are inorganic insulation layer.
Further, first insulating layer, third insulating layer material be one kind or combination of silicon nitride and silica.
Further, the second insulating layer is organic insulator.
The present invention is by using intermediate tone mask method, to photoresist, third insulating layer, first at pixel region third via hole
Insulating layer performs etching simultaneously, carries out simultaneously at the second via hole of terminal region to third insulating layer, the first insulating layer, gate insulating layer
Etching, etching Shi Duoyi layer photoresist are protected, it is possible to reduce pixel region is to the first insulating layer, second insulating layer and drain electrode table
The influence at quarter is crossed in face, so that pixel electrode be avoided to break, reduces impedance at via hole.
Detailed description of the invention
Fig. 1 is that the manufacturing method first step of array substrate of the present invention forms grid；
Fig. 2 be array substrate of the present invention manufacturing method second step formation gate insulating layer, metal oxide semiconductor layer,
Source electrode and drain electrode；
Fig. 3 is that the manufacturing method third step of array substrate of the present invention forms the first insulating layer and second insulating layer；
Fig. 4 is that the 4th step of manufacturing method of array substrate of the present invention forms common electrode；
Fig. 5 and Fig. 6 is that manufacturing method the 5th step to the 8th step of array substrate of the present invention forms the 4th via hole and the 5th mistake
Hole；
Fig. 7 is that the 9th step of manufacturing method of array substrate of the present invention forms pixel electrode.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate
It the present invention rather than limits the scope of the invention, after the present invention has been read, those skilled in the art are to of the invention each
The modification of kind equivalent form falls within the application range as defined in the appended claims.
The present invention provides a kind of array substrate, and array substrate includes being located in the middle pixel region and the terminal positioned at edge
Area, the manufacturing method of array substrate, includes the following steps:
S1: as shown in Figure 1, forming grid 2 on the pixel region of glass substrate 1 and terminal region respectively using the first metal；
S2: as shown in Fig. 2, forming the gate insulating layer 3 of covering grid 2；Semiconductor layer is formed above gate insulating layer 3
4 (semiconductor layer 4 is IGZO semiconductor (metal-oxide semiconductor (MOS)) in the present embodiment)；It is formed using the second metal and is located at pixel
The source electrode 5 of 4 two sides of semiconductor layer in area and drain electrode 6 and formation are located at the metal contact layer of 4 top of semiconductor layer of terminal region
56, wherein the source electrode 5 of pixel region and drain electrode 6 with two side contacts of semiconductor layer 4, the metal contact layer 56 of terminal region with partly lead
4 overlying contact of body layer, the width of metal contact layer 56 are not more than the width of the semiconductor layer 4 of terminal region；
S3: as shown in figure 3, forming 7 (the first insulation of the first insulating layer of covering source electrode 5, drain electrode 6 and metal contact layer 56
Layer 7 is inorganic insulation layer, and the material of the first insulating layer 7 is one kind or combination of silicon nitride and silica)；Form covering first absolutely
The second insulating layer 8 of edge layer 7 (second insulating layer 8 is organic insulator (JAS))；The portion of 6 top of drain electrode of pixel region is fallen in exposure
Divide second insulating layer 8 and forms the first via hole 9 for being located at 6 top of drain electrode；56 liang of metal contact layer of terminal region are etched away simultaneously
The part second insulating layer 8 of side simultaneously forms the second via hole 10 for being located at 56 two sides of metal contact layer；
S4: as shown in figure 4, forming common electrode 11 first above the second insulating layer of pixel region 8, picture is then etched away
The common electrode 11 of plain 9 top of the first via hole of area simultaneously forms third via hole 12, while etching away positioned at the part first of terminal region
Insulating layer 7；
S5: as shown in figure 5, on the basis of step S4 covering formed third insulating layer 13 (third insulating layer 13 be it is inorganic
Insulating layer, the material of third insulating layer 13 are one kind or combination of silicon nitride and silica), it is coated above third insulating layer 13
Photoresist 14；
S6: as shown in figure 5, being exposed using intermediate tone mask version to pixel region and terminal region photoresist 14, by pixel
14 Partial exposure of photoresist in the third via hole 12 in area falls, and all exposure removes the photoresist 14 of 10 bottom of the second via hole of terminal region
Fall, the photoresist 14 on 10 side wall of the second via hole of terminal region still retains, and the photoresist 14 of 56 top of part metals contact layer is complete
Portion's exposure is fallen and forms the first metal contact hole 20；
S7: as shown in Figure 5 and Figure 6, exhausted to photoresist 14, third insulating layer 13, first at the third via hole 12 of pixel region
Edge layer 7 performs etching simultaneously, forms the 4th via hole 15 for being located at 6 top of drain electrode；The in second via hole 10 of terminal region simultaneously
Three insulating layers 13, the first insulating layer 7 and gate insulating layer 3 perform etching simultaneously and form the 5th via hole above grid 2
16, while the third insulating layer 13 of 56 top of metal contact layer and the first insulating layer 7 perform etching to be formed positioned at metal contact layer 6
Second metal contact hole 21 of top；
S8: remaining photoresist 14 is removed；
S9: as shown in fig. 7, covering semi-transparent conductive material (such as ITO) on the basis of step S8, formation is located at picture
The pixel electrode 17 in plain area and terminal region, pixel electrode 17 are connect by the 4th via hole 17 with drain electrode 6 respectively, and pixel electrode 17 is logical
It crosses the 5th via hole 16 to connect with the grid 2 of terminal region, pixel electrode 17 is connected by the second metal contact hole 21 with metal contact layer 6
It connects.The present invention provides a kind of array substrate, as shown in fig. 7, comprises pixel region and terminal region；Pixel region includes grid 2, is located at grid
Gate insulating layer 3, the semiconductor layer 4 above gate insulating layer 3, the source for being located at 4 two sides of semiconductor layer of 2 top of pole
Pole 5 and drain electrode 6, the first insulating layer 7 above source electrode 5 and drain electrode 6, the second insulating layer above the first insulating layer 7
8, the common electrode 11 above second insulating layer 8, the third insulating layer 13 above common electrode 11 and be located at third
The pixel electrode 17 of 13 top of insulating layer, 6 top of drain electrode are provided with the 4th via hole 15, and pixel electrode 17 passes through the 4th via hole 15 and leakage
Pole 6 connects and is connected；Wherein, semiconductor layer 4 is IGZO semiconductor, and the first insulating layer 7 and third insulating layer 13 are inorganic insulation
The material of layer, the first insulating layer 7 and third insulating layer 13 is one kind or combination of silicon nitride and silica, and second insulating layer 8 is
Organic insulator.
Terminal region includes grid 2, the gate insulating layer 3 above grid 2, partly leading above gate insulating layer 3
Body layer 4, the first insulating layer 7 above metal contact layer 56, is located at the at the metal contact layer 56 on semiconductor layer 4
The second insulating layer 8 of one insulating layer, 7 top, is located at third insulating layer 13 at the third insulating layer 13 above second insulating layer 8
The pixel electrode 17 of top, tool has on metal contact layer 56 and is located at two the 5th via holes there are two the 5th via hole 16 on grid 2
The second metal contact hole 21 between 16, pixel electrode 17 are connect and are connected with grid 2 by the 5th via hole 16, pixel electrode 17
It is connect by the second metal contact hole 21 with metal contact layer 56；Wherein, metal oxide semiconductor layer 4 is IGZO semiconductor,
First insulating layer 7 and third insulating layer 13 are inorganic insulation layer, and the material of the first insulating layer 7 and third insulating layer 13 is silicon nitride
And one kind or combination of silica, second insulating layer 8 are organic insulator.
The present invention by using intermediate tone mask version, at the third via hole of pixel region to photoresist, third insulating layer and
First insulating layer performs etching simultaneously, to third insulating layer, the first insulating layer and gate insulating layer at the second via hole of terminal region
Perform etching simultaneously, pixel region performs etching Shi Duoyi layer photoresist and protected, it is possible to reduce pixel region to the first insulating layer,
Second insulating layer and drain surface cross the influence at quarter, so that pixel electrode be avoided to break, reduce impedance at via hole.
Claims (10)
1. a kind of manufacturing method of array substrate, array substrate includes being located in the middle pixel region and the terminal region positioned at edge,
It is characterized by comprising following steps:
S1: grid is formed on the pixel region of glass substrate and terminal region respectively using the first metal；
S2: the gate insulating layer of covering grid is formed, semiconductor layer is formed above gate insulating layer, is formed using the second metal
The metal being located above the semiconductor layer of terminal region positioned at the source electrode and drain electrode of the semiconductor layer two sides of pixel region and formation connects
Contact layer, wherein the source electrode and drain electrode of pixel region with two side contacts of semiconductor layer, the metal contact layer and semiconductor of terminal region
Layer overlying contact；
S3: forming the first insulating layer of covering source electrode, drain electrode and metal contact layer, forms the second insulation of the first insulating layer of covering
Layer；Exposure falls the part second insulating layer above the drain electrode of pixel region and forms the first via hole for being located at drain electrode top；In the same time
The part second insulating layer of the metal contact layer two sides of eating away terminal region simultaneously forms the second via hole for being located at metal contact layer two sides；
S4: forming common electrode above the second insulating layer of pixel region, etches away the common electricity above the first via hole of pixel region
Pole forms third via hole；
S5: covering forms third insulating layer on the basis of step S4, coats photoresist above third insulating layer；
S6: being exposed pixel region and terminal region photoresist using intermediate tone mask version, will be in the third via hole of pixel region
Photoresist Partial exposure falls, and the photoresist of the second via bottom of terminal region all remove by exposure, in the second via sidewall of terminal region
Photoresist still retain, all exposure is fallen and forms the first metal contact hole for photoresist above part metals contact layer；
S7: photoresist, third insulating layer and the first insulating layer are performed etching simultaneously at the third via hole of pixel region, formation is located at
The 4th via hole above draining；Third insulating layer, the first insulating layer and gate insulating layer in second via hole of terminal region are simultaneously
It performs etching and forms the 5th via hole above grid, while third insulating layer and the first insulation above metal contact layer
Layer performs etching the second metal contact hole to be formed above metal contact layer；
S8: photoresist on pixel region and terminal region third insulating layer is removed；
S9: covering semi-transparent conductive material on the basis of step S8, forms the pixel electrode for being located at pixel region and terminal region, as
Plain electrode is connected by the drain electrode of the 4th via hole and pixel region and is connected, and pixel electrode is connect by the 5th via hole with terminal region grid
Conducting, pixel electrode are connect by the second metal contact hole with metal contact layer.
2. the manufacturing method of array substrate according to claim 1, it is characterised in that: first insulating layer and third are exhausted
Edge layer is inorganic insulation layer.
3. the manufacturing method of array substrate according to claim 2, it is characterised in that: first insulating layer and third are exhausted
The material of edge layer is one kind or combination of silicon nitride and silica.
4. the manufacturing method of array substrate according to claim 1, it is characterised in that: the second insulating layer is organic exhausted
Edge layer.
5. the manufacturing method of array substrate according to claim 1, it is characterised in that: the semiconductor layer is that IGZO is partly led
Body.
6. array substrate made from -5 any one manufacturing methods according to claim 1, it is characterised in that: including pixel region and end
Sub-district；Pixel region includes grid, the gate insulating layer above grid, the semiconductor layer above gate insulating layer, divides
Not Wei Yu the source electrode and drain electrodes of semiconductor layer two sides, the first insulating layer above source electrode and drain electrode, be located at the first insulating layer
The second insulating layer of top, the common electrode above second insulating layer, the third insulating layer above common electrode and
Pixel electrode above third insulating layer；Drain electrode top is provided with the 4th via hole, and pixel electrode passes through the 4th via hole and drain electrode
Conducting；Terminal region includes grid, the gate insulating layer above grid, the semiconductor layer above gate insulating layer, position
In the metal contact layer on semiconductor layer, the first insulating layer above metal contact layer, above the first insulating layer
Second insulating layer, the third insulating layer above second insulating layer and the pixel electrode above third insulating layer, grid
Extremely upper tool has the second metal contact hole being located between two the 5th via holes on metal contact layer there are two the 5th via hole, as
Plain electrode is connected by the second metal contact hole with metal contact layer by the 5th via hole and gate turn-on, pixel electrode.
7. array substrate according to claim 6, it is characterised in that: the semiconductor layer is IGZO semiconductor.
8. array substrate according to claim 7, it is characterised in that: first insulating layer and third insulating layer are inorganic
Insulating layer.
9. array substrate according to claim 8, it is characterised in that: the material of first insulating layer and third insulating layer
For one kind or combination of silicon nitride and silica.
10. array substrate according to claim 6, it is characterised in that: the second insulating layer is organic insulator.
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| CN201910114510.4A CN109887883B (en) | 2019-02-14 | 2019-02-14 | Array substrate and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910114510.4A CN109887883B (en) | 2019-02-14 | 2019-02-14 | Array substrate and manufacturing method thereof |
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| CN109887883A true CN109887883A (en) | 2019-06-14 |
| CN109887883B CN109887883B (en) | 2020-11-06 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564454A (en) * | 2020-05-19 | 2020-08-21 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150162358A1 (en) * | 2013-12-11 | 2015-06-11 | Mitsubishi Electric Corporation | Active matrix substrate and method for manufacturing the same |
| CN106356376A (en) * | 2015-07-15 | 2017-01-25 | 乐金显示有限公司 | Ultra high density thin film transistor substrate having low line resistance structure and method for manufacturing the same |
| CN106932986A (en) * | 2017-04-17 | 2017-07-07 | 深圳市华星光电技术有限公司 | The preparation method of array base-plate structure and array base palte |
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2019
- 2019-02-14 CN CN201910114510.4A patent/CN109887883B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150162358A1 (en) * | 2013-12-11 | 2015-06-11 | Mitsubishi Electric Corporation | Active matrix substrate and method for manufacturing the same |
| CN106356376A (en) * | 2015-07-15 | 2017-01-25 | 乐金显示有限公司 | Ultra high density thin film transistor substrate having low line resistance structure and method for manufacturing the same |
| CN106932986A (en) * | 2017-04-17 | 2017-07-07 | 深圳市华星光电技术有限公司 | The preparation method of array base-plate structure and array base palte |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564454A (en) * | 2020-05-19 | 2020-08-21 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN111564454B (en) * | 2020-05-19 | 2022-07-12 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
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