CN109887846A - The preparation process of anti-radiation power MOSFET - Google Patents

Abstract

The invention discloses the preparation process of anti-radiation power MOSFET a kind of.The described method includes: the first area of the active area of oxidation circular wafer forms silicon dioxide masking layer, inject to form P+ type p-well by boron ion after etching silicon dioxide masking layer-selective；Oxidation wafer surface forms silicon dioxide layer and injects to form N-type JFET by phosphonium ion after silicon dioxide layer selective etch；It coats photoresist on circular wafer surface and carries out selectivity and expose generation graphical window, inject to form p-type p-well by boron ion；It coats photoresist on circular wafer surface and carries out selectivity and expose generation graphical window, inject to form N-type Source by arsenic and phosphonium ion；Circular wafer surface is cleaned, and thermal oxide is carried out to the circular wafer surface after cleaning and generates silica as gate dielectric layer；Gate dielectric layer preparation process postposition has arrived after the completion of active area, JFET, p-well, Source preparation, improves the capability of resistance to radiation of MOSFET.

Description

The preparation process of anti-radiation power MOSFET

Technical field

The present invention relates to the VDMOS product related fields that is suitable for space or aerospace applications, in particular to one The preparation process of the anti-radiation power MOSFET of kind.

Background technique

Longitudinal double diffusion metal oxide field effect transistor (VDMOSFET) largely is used in power electronic equipment at present, Power MOSFET switching speed, input impedance, frequency characteristic and in terms of have clear superiority, be widely used in On the high frequency switch power or converter of various voltage and current grades, and its negative temperature coefficient for having and the safe work of width Make the performance advantages such as area to highlight.In spatial power field of electronic systems, such as communications satellite, meteorological satellite, GPS(global location System) and Earthwatch satellite on, power MOSFET because of its high switching speed, low conduction loss, small space hold, And it is more used widely.

Work will also have other than meeting conventional basic electricity parameter request in the MOSFET element of the outer space The long-term capability of resistance to radiation for bearing various ionising radiations, high energy particle and cosmic ray etc. in space.Power MOSFET device Threshold voltage (Vth), breakdown voltage (BVdss), leakage current (Idss), mutual conductance (gm) and conducting resistance (Rdson) etc. are all by this The influence of class ionising radiation should all have anti-integral dose radiation (TID) and anti-single particle applied to the device of aerospace field The abilities such as effect (SEE).The power MOSFET for being suitable for this application environment should carry out " anti-spoke by designing and manufacturing technique Penetrate reinforcing (radiation hardened) ".

VDMOS device in space environment application, single particle effect becomes it to be made in a large amount of heavy ion space environments Major limitation, single particle effect mainly include single event burnout (SEB) and single event gate rupture (SEGR).Heavy ion incidence Such as Fig. 1 is influenced, to single event burnout the study found that a high energy ion 01 generates electricity along its incident path in semiconductor Lotus " sheath ", if the drain bias of VDMOS device is more than some value, the hole electronics 03- 02 increases density, causes electric current close Degree is more than 10⁴A/ cm², hole 02, which is understood, constantly to be driven to below the surface of N-channel MOS FET and VDMOS device active layer, it is easy to The pressure drop for being near or above 0.7V is generated, enters second breakdown to open and induce bipolar transistor existing for parasitism, The entire energy of power supply can be gathered in the place that the operating mode starts on chip, and temperature, which can be acutely increased up, burns.Simple grain Sub- grid are worn, and are referred in power MOSFET, after heavy ion passes through gate dielectric layer, cause to form conductive path in gate dielectric layer 05 Destructive burn.There are two the mechanism for causing single event gate rupture: first is that the plasma formed along high-energy heavy ion incidence Silk stream local damage caused by gate medium；Second is that grid leak overlay region Si/SiO₂The hole 02 at interface accumulates.Heavy ion is situated between from grid At matter layer 05 when incidence, it is contemplated that the presence of grid biased, the hole 02 electronics 03- that heavy ion generates in silicon is right, in electric field It drifts about under effect to different directions, hole 02 drifts about to grid rapidly, and in the Si-SiO of grid and the handover of body silicon₂Interface is tired Product, causes the potential of interface to increase, and then be consequently increased the potential difference of 05 two sides of gate dielectric layer, when electric field strength is more than When the critical field strength of punch-through effect occurs for gate dielectric layer 05, gate dielectric layer 05 punctures.The thickness for increasing grid can improve device The single event gate rupture effect of part, but the increase of grid thickness is unfavorable for anti-integral dose radiation (TID) performance of device, and synthesis is needed to examine Consider the quality and performance for improving grid, improves device anti-single particle grid and wear (SEGR) ability.

Power MOSFET ionizing radiation-resistant ability, significant portion are influenced by device gate.05 mass of gate dielectric layer and performance, When grid and body silicon interface quality etc. are poor, being embodied in band structure then is that more energy levels and interfacial state are introduced in forbidden band, Under single-particle radiation environment, it is easier to transition occur and puncture grid.The study found that the thermal process of grid experience is more, it is limited by The globality of the influence of the atmosphere such as temperature and ambient windstream, 05 internal structure of gate dielectric layer can be deteriorated, and oxide-trapped charge is close Degree increases, and plasma filament stream and local damage are also bigger when high energy particle passes through；Interface Si-SiO simultaneously₂Lattice mismatch, Interfacial state caused by dangling bonds, thermal stress, foreign atom etc. and trapped charge 04 are also more, also make it easier to capture hole 02 etc. Charge accumulated is caused, and then more easily produces the breakdown of grid.

Summary of the invention

In order to solve problems in the prior art, the embodiment of the invention provides the technique systems of anti-radiation power MOSFET a kind of Preparation Method.The technical solution is as follows:

In a first aspect, providing the preparation process of anti-radiation power MOSFET a kind of, which comprises

Aoxidizing, there is the first area of the active area of circular wafer of silicon substrate epitaxial material to form silicon dioxide masking layer, to described two It injects to form P+ type p-well by boron ion after silicon oxide mask layer selective etch；

The surface for aoxidizing the second area of the active area of the circular wafer forms silicon dioxide masking layer, covers to the silica It injects to form the area N-type JFET by phosphonium ion after covering layer-selective etching；

It coats photoresist on the circular wafer surface and carries out selectivity and expose generation graphical window, inject to be formed by boron ion P-type p-well；

It coats photoresist on the circular wafer surface and carries out selectivity and expose generation graphical window, pass through arsenic and phosphonium ion injects Form N-type Source；

The circular wafer surface is cleaned, and thermal oxide is carried out to the circular wafer surface after cleaning and generates silica as grid Dielectric layer；

Polycrystalline silicon deposit is carried out to the circular wafer, phosphonium ion injection is carried out to the polysilicon, by the polysilicon Polysilicon gate is formed after photoetching and etching；

Dielectric deposition and electrode layer preparation, generate interlayer dielectric layer and electrode draws layer.

Optionally, it injects to form P+ type p-well by boron ion after the etching to the silicon dioxide masking layer-selective, Include:

Injection element is boron ion, and the ion beam energy range of injection B ion is 40KeV to 100KeV, the B ion of injection Dosage range is 1.2*10¹⁴cm^-3To 1.2*10¹⁶cm^-3, obtain the P+ type p-well.

Optionally, it injects to form N-type JFET by phosphonium ion after the etching to the silicon dioxide masking layer-selective Area, including;

Injection element is phosphorus P ion, and the ion beam energy range for injecting P ion is 60KeV to 120KeV, the P ion of injection Dosage range is 0.8*10¹¹cm^-3To 1*10¹³cm^-3, obtain the area the N-type JFET.

It is optionally, described that p-type p-well is formed by ion implanting, comprising:

Injection element is boron ion, and the ion beam energy range of injection B ion is 40KeV to 110KeV, the B ion of injection Dosage range is 2*10¹³cm^-3To 2*10¹⁵cm^-3, p-well annealing knot is then carried out, annealing time range is 50min to 200min Between, obtain the p-type p-well.

It is optionally, described to inject to form N-type Source by arsenic and phosphonium ion, comprising:

Injection element one is arsenic As ion, injection element two is phosphorus P ion, forms the N-type Source.

Optionally, the ion beam energy range for injecting As ion is 70KeV to 160KeV, the dosage model of the As ion of injection It encloses for 1*10¹⁵cm^-3To 1*10¹⁷cm^-3。

Optionally, the ion beam energy range for injecting P ion is 50KeV to 120KeV, the dosage range of the P ion of injection For 7*10¹⁴cm^-3To 7*10¹⁶cm^-3。

Optionally, described and to after cleaning the circular wafer surface carry out thermal oxide generate silica as gate medium Layer, comprising:

It is realized under oxidizing atmosphere in high temperature diffusion furnace tube, the temperature range that oxidation process uses is 750 DEG C to 1050 DEG C, is formed Silicon dioxide gate dielectric layer with a thickness of 500 angstroms to 1500 angstroms.

Optionally, it is described to the wafer surface carry out polysilicon (Poly-Si) deposit, and to polysilicon carry out phosphorus from Son injection, comprising:

Injection element is phosphorus P ion, and the ion beam energy range for injecting P ion is 30KeV to 80KeV, the agent of the P ion of injection Amount range is 1*10¹⁵cm^-3To 1*10¹⁷cm^-3。

Optionally, the generation interlayer dielectric layer, comprising:

Form the interlayer dielectric layer in such a way that TEOS boron-doping B p-doped P decomposes deposit, the interlayer dielectric layer with a thickness of 0.5 um to 1.5 um.

Optionally, the generation electrode draws layer, comprising:

Aluminium Al silicon Si copper Cu alloy media film is obtained as electrode by sputtering mode and draws layer, and the electrode draws the thickness of layer For 2 um to 4um.

Technical solution provided in an embodiment of the present invention has the benefit that

After the completion of above-mentioned preparation method is by preparing gate dielectric layer preparation process postposition to active area, JFET, p-well, Source, After the completion of gate dielectric layer preparation, other pyroprocesses are no longer carried out, and then avoid going up and down repeatedly in other high temperature preparation process The impact of temperature and the accumulation of high-temperature time reduce the influence of high temperature and atmosphere to gate dielectric layer quality.In addition, above-mentioned preparation method Compared with the gate dielectric layer that usual preparation process obtains, gate dielectric layer inner structural integrity is more preferable, dangling bonds and trap Charge density is low, the Si-SiO of gate dielectric layer and its lower body silicon₂Interface interface state density is small, does not easily cause charge accumulated, mentions Resistance to sparking energy under high gate dielectric layer radiation environment, enhances the capability of resistance to radiation of such power MOSFET.The present invention is real The technical solution of example offer is provided, it is simple flow, easy to operate, it can economically realize.

Detailed description of the invention

To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.

Fig. 1 is the schematic diagram of the heavy ion incidence provided in one embodiment of the invention.

Fig. 2 is the structural schematic diagram of the anti-radiation power MOSFET provided in one embodiment of the invention.

Specific embodiment

To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention Formula is described in further detail.

The preparation process of anti-radiation power MOSFET a kind of is present embodiments provided, also, referring to FIG. 2, it shows The structural schematic diagram for having gone out the MOSFET that this method is prepared, in conjunction with Fig. 2, this method comprises:

First, aoxidizing, there is the first area of the active area of circular wafer of silicon substrate epitaxial material 101 to form silicon dioxide masking layer, It injects to form P+ type p-well by boron ion after etching the silicon dioxide masking layer-selective.

Wherein, the ion of injection is boron ion, and the ion beam energy range of injection B ion is 40KeV to 100KeV, note The dosage range of the B ion entered is 1.2*10¹⁴cm^-3To 1.2*10¹⁶cm^-3.First area is a part of the active area of circular wafer Region, to this and without limitation.

Second, the surface for aoxidizing the second area of the active area of the circular wafer forms silicon dioxide masking layer, to described It injects to form the area N-type JFET by phosphonium ion after the etching of silicon dioxide masking layer-selective.

The ion of injection is phosphorus P ion, and the ion beam energy range for injecting P ion is 60KeV to 120KeV, the P of injection The dosage range of ion is 0.8*10¹¹cm^-3To 1*10¹³cm^-3, obtain the area the N-type JFET.

Third, the circular wafer surface coat photoresist and carry out selectivity expose generate graphical window, by boron from Son injection forms p-type p-well.

The ion of injection is B ion, and the ion beam energy range of injection B ion is 40KeV to 110KeV, the B of injection from The dosage range of son is 2*10¹³cm^-3To 2*10¹⁵cm^-3, then carry out p-well anneal knot, annealing time range be 50min extremely Between 200min.

In addition, above mentioned P+ type p-well and p-type p-well collectively constitutes the p-well 102 in Fig. 2.

4th, coat photoresist on the circular wafer surface and carry out selectivity and expose to generate graphical window, by arsenic and Phosphonium ion injects to form N-type Source103.

In actual implementation, during forming N-type Source103, arsenic As ion and phosphorus P ion can be injected.And And the ion beam energy range for injecting As ion is 70KeV to 160KeV, the dosage range of the As ion of injection is 1*10¹⁵cm^-3To 1*10¹⁷cm^-3, the ion beam energy range for injecting P ion is 50KeV to 120KeV, and the dosage range of the P ion of injection is 7*10¹⁴cm^-3To 7*10¹⁶cm^-3。

5th, the circular wafer surface is cleaned, and thermal oxide is carried out to the circular wafer surface after cleaning and generates dioxy SiClx is as gate dielectric layer 104.

The generating process of thermal oxide includes: to realize under oxidizing atmosphere in high temperature diffusion furnace tube, the temperature that oxidation process uses Spending range is 750 DEG C to 1050 DEG C, and the silicon dioxide gate dielectric layer of formation is with a thickness of 500 angstroms to 1500 angstroms.

Common MOSFET gate dielectric layer 104 prepares the front half section in whole flow process, namely is placed on the area JFET and p-well Between even also want forward；The preparation process postposition of gate dielectric layer 104 in this method has arrived the second half section of whole flow process, namely The preparation process of gate dielectric layer 104 is after the preparations such as active area, P+ ring, the area JFET, p-well, Source completion；This method grid are situated between After the completion of the preparation of matter layer, there is no other pyroprocesses, it is possible to reduce after the completion of the preparation of gate dielectric layer 104, in other processing procedures The accumulation of the pyroprocess impact of heating and cooling and high-temperature time repeatedly reduces the influence of high temperature and atmosphere to gate dielectric layer 104.With The gate dielectric layer that usual preparation process obtains is compared, and 104 inner structural integrity of gate dielectric layer is more preferable, dangling bonds and trap Charge density is low, Si-SiO₂Interface interface state density is small, does not easily cause charge accumulated, improves gate dielectric layer resistance to sparking Can, enhance the capability of resistance to radiation of such power MOSFET.

6th, polycrystalline silicon deposit is carried out to the circular wafer, phosphonium ion injection is carried out to the polysilicon, by described Polysilicon gate 105 is formed after the photoetching and etching of polysilicon.

Wherein, the ion of injection is P ion, and the ion beam energy range for injecting P ion is 30KeV to 80KeV, injection The dosage range of P ion is 1*10¹⁵cm^-3To 1*10¹⁷cm^-3。

7th, dielectric deposition and electrode layer preparation, generation interlayer dielectric layer 106 and electrode draw layer 107.

Optionally, the generation interlayer dielectric layer, comprising:

Form the interlayer dielectric layer in such a way that TEOS boron-doping B p-doped P decomposes deposit, the interlayer dielectric layer with a thickness of 0.5 um to 1.5 um.

The generation electrode draws layer, comprising:

Aluminium Al silicon Si copper Cu alloy media film is obtained as electrode by sputtering mode and draws layer, and the electrode draws the thickness of layer For 2 um to 4um.

The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.

Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..

The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of preparation process of anti-radiation power MOSFET, which is characterized in that the described method includes:

Aoxidizing, there is the first area of the active area of circular wafer of silicon substrate epitaxial material to form silicon dioxide masking layer, to described two It injects to form P+ type p-well by boron ion after silicon oxide mask layer selective etch；

The surface for aoxidizing the second area of the active area of the circular wafer forms silicon dioxide masking layer, covers to the silica It injects to form the area N-type JFET by phosphonium ion after covering layer-selective etching；

It coats photoresist on the circular wafer surface and carries out selectivity and expose generation graphical window, inject to be formed by boron ion P-type p-well；

It coats photoresist on the circular wafer surface and carries out selectivity and expose generation graphical window, pass through arsenic and phosphonium ion injects Form N-type Source；

The circular wafer surface is cleaned, and thermal oxide is carried out to the circular wafer surface after cleaning and generates silica as grid Dielectric layer；

Polycrystalline silicon deposit is carried out to the circular wafer, phosphonium ion injection is carried out to the polysilicon, by the polysilicon Polysilicon gate is formed after photoetching and etching；

Dielectric deposition and electrode layer preparation, generate interlayer dielectric layer and electrode draws layer.

2. the method according to claim 1, wherein after the etching to the silicon dioxide masking layer-selective It injects to form P+ type p-well by boron ion, comprising:

Injection element is boron ion, and the ion beam energy range of injection B ion is 40KeV to 100KeV, the B ion of injection Dosage range is 1.2*10¹⁴cm^-3To 1.2*10¹⁶cm^-3, obtain the P+ type p-well.

3. the method according to claim 1, wherein after the etching to the silicon dioxide masking layer-selective It injects to form the area N-type JFET by phosphonium ion, including;

Injection element is phosphorus P ion, and the ion beam energy range for injecting P ion is 60KeV to 120KeV, the P ion of injection Dosage range is 0.8*10¹¹cm^-3To 1*10¹³cm^-3, obtain the area the N-type JFET.

4. the method according to claim 1, wherein described inject to form p-type p-well by boron ion, comprising:

Injection element is boron ion, and the ion beam energy range of injection B ion is 40KeV to 110KeV, the B ion of injection Dosage range is 2*10¹³cm^-3To 2*10¹⁵cm^-3, p-well annealing knot is then carried out, annealing time range is 50min to 200min Between, obtain the p-type p-well.

5. the method according to claim 1, wherein described inject to form N-type Source by arsenic and phosphonium ion, Include:

Injection element one is arsenic As ion, injection element two is phosphorus P ion, forms the N-type Source.

6. according to the method described in claim 5, it is characterized in that,

The ion beam energy range for injecting As ion is 70KeV to 160KeV, and the dosage range of the As ion of injection is 1* 10¹⁵cm^-3To 1*10¹⁷cm^-3；And/or

The ion beam energy range for injecting P ion is 50KeV to 120KeV, and the dosage range of the P ion of injection is 7*10¹⁴cm^-3 To 7*10¹⁶cm^-3。

7. method according to any one of claims 1 to 6, which is characterized in that described and to the circular wafer table after cleaning Face carries out thermal oxide and generates silica as gate dielectric layer, comprising:

It is realized under oxidizing atmosphere in high temperature diffusion furnace tube, the temperature range that oxidation process uses is 750 DEG C to 1050 DEG C, is formed Silicon dioxide gate dielectric layer with a thickness of 500 angstroms to 1500 angstroms.

8. method according to any one of claims 1 to 6, which is characterized in that described to carry out polycrystalline to the wafer surface Silicon (Poly-Si) deposit, and phosphonium ion injection is carried out to polysilicon, comprising:

Injection element is phosphorus P ion, and the ion beam energy range for injecting P ion is 30KeV to 80KeV, the agent of the P ion of injection Amount range is 1*10¹⁵cm^-3To 1*10¹⁷cm^-3。

9. method according to any one of claims 1 to 6, which is characterized in that the generation interlayer dielectric layer, comprising:

Form the interlayer dielectric layer in such a way that TEOS boron-doping B p-doped P decomposes deposit, the interlayer dielectric layer with a thickness of 0.5 um to 1.5 um.

10. method according to any one of claims 1 to 6, which is characterized in that the generation electrode draws layer, comprising:

Aluminium Al silicon Si copper Cu alloy media film is obtained as electrode by sputtering mode and draws layer, and the electrode draws the thickness of layer For 2 um to 4um.