CN109887844A - A kind of double buried layer mos gate control thyristors and preparation method - Google Patents
A kind of double buried layer mos gate control thyristors and preparation method Download PDFInfo
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Abstract
The present invention provides a kind of double buried layer mos gate control thyristors and preparation method, and double buried layer mos gate control thyristors include: substrate and drift region；Double N buried layers, surface texture are successively provided in drift region from bottom to up；The cathode and grid and the anode of substrate lower end surface of surface texture upper surface are set.The present invention is able to ascend device opening speed, inhibits the snapback phenomenon in base resistance control thyristor (BRT) and Emitter-Switched Thyristor (EST) opening process, it solves multi cell and opens inconsistence problems, it is even to alleviate current distribution is uneven, improves device and opens reliability.
Description
Technical field
The present invention relates to power semiconductor technologies field more particularly to a kind of double buried layer mos gate control thyristors and preparation sides
Method.
Background technique
It is compared, MOS with insulated gate bipolar transistor (IGBT, Insulated Gate Bipolar Transistor)
Grid-controlled transistor (mos gate control thyristor: MOS-gated thyristor) is with conducting resistance is low, current density is high, unlatching is fast
The advantages such as fast are spent, are had broad application prospects in fields such as pulse powers.Mos gate control thyristor mainly includes four layers of N-
The thyristor structure that P-N-P material is constituted, passes through NMOS (Metal Oxide Semiconductor Field Effect Transistor: MOSFET, Metal
Oxide Semiconductor Field Effect Transistor, N-channel field effect transistor: NMOS) injection electronics electricity
Stream, which opens thyristor internal positive feedback, makes break-over of device, and PMOS (P-channel field-effect transistor (PEFT) transistor: PMOS) extracts feedback current and interrupts
Positive feedback turns off device.Current mos gate control thyristor mainly includes MOS control thyristor (MCT, MOS Controlled
Thyristor), base resistance control thyristor (BRT, Base Resistance Controlled Thyristor) and transmitting
The devices such as pole Switched Thyristors (EST, Emitter Switched Thyristor).
Compared with MCT, the advantage that there is technique to be compatible with IGBT phase by BRT and EST, but in opening process working condition from
IGBT mode is transformed into thyristor mode, and strong conductance modulation occurs, and device on-resistance can be made rapid drawdown, curve of output occur
There is snapback phenomenon, will cause in multi cell device and open inconsistent problem, constraint device performance influences device work
Make reliability.
For example, as shown in Figure 1, common base resistance control thyristor (BRT) major part is tetra- layer material structure of N-P-N-P
At thyristor (1,2,4,5,6 in Fig. 1), further include two surface MOSFET:NMOS (1,2,4 in Fig. 1) and PMOS (in Fig. 1
2,4,3) and parasitic-PNP transistor (in Fig. 13,4,5,6).In addition, BRT also includes three electrodes: anode A (10), cathode K
(7) and grid G (8).
Therefore, when grid 8 applies forward bias, NMOS conducting, PMOS shutdown, NMOS current trigger thyristor structure,
Internal positive feedback is opened, break-over of device is made；When grid 8 applies negative bias, NMOS shutdown, PMOS conducting, PMOS extract the base area P
Hole current interrupts thyristor internal positive feedback, turns off device.Due to device there are parasitic-PNP transistor (3 on the right side of Fig. 1,
4,5,6), BRT is worked in low current in IGBT mode, and there are snap-back phenomenon (as shown in Figure 2) for output characteristics；In addition,
Since PMOS turn-off capacity is weak, cause BRT turn-off speed slower, shutdown power consumption is larger.
Summary of the invention
Double buried layer mos gate control thyristors provided by the invention and preparation method are able to ascend device opening speed, inhibit base
Area's resistance controls the snapback phenomenon in thyristor (BRT) and Emitter-Switched Thyristor (EST) opening process, solves polynary
Born of the same parents open inconsistence problems, and alleviation current distribution is uneven is even, improve device and open reliability.
In a first aspect, the present invention provides a kind of double buried layer mos gate control thyristors, comprising:
Substrate and drift region；
Double N buried layers, surface texture are successively provided in drift region from bottom to up；
The cathode and grid and the anode of substrate lower end surface of surface texture upper surface are set.
Optionally, double N buried layers include:
First N buried layer of the first surface structure lower end on the left of drift region is set, so that it forms electricity in thyristor
Sub- potential well；
2nd N buried layer of the second surface structure lower end on the right side of drift region is set, so that it is in parasitic triode area
Form hole barrier.
Optionally, the first N buried layer is oppositely arranged with the 2nd N buried layer.
Optionally, the size of the electronics potential well is corresponding with the doping concentration of the first N buried layer；
Preferably, the size of the hole barrier is corresponding with the doping concentration of the 2nd N buried layer.
Optionally, the first N buried layer and the spacing between the 2nd N buried layer are corresponding with thyristor type.
Second aspect, the present invention provide a kind of double buried layer mos gate control thyristor preparation methods, comprising:
Prepare substrate and drift region；
Double N buried layers, surface texture are successively prepared in drift region from bottom to up；
It metallizes in surface texture upper surface and substrate lower end surface, preparation forms cathode, grid, anode.
Optionally, pair N buried layers that prepare in drift region include:
First surface structure lower end on the left of drift region prepares the first N buried layer, so that it forms electronics in thyristor
Potential well；
Second surface structure lower end on the right side of drift region prepares the 2nd N buried layer, so that its shape in parasitic triode area
At hole barrier.
Optionally, the first N buried layer is oppositely arranged with the 2nd N buried layer.
Optionally, the size of the electronics potential well is corresponding with the doping concentration of the first N buried layer；
Preferably, the size of the hole barrier is corresponding with the doping concentration of the 2nd N buried layer.
Optionally, the first N buried layer and the spacing between the 2nd N buried layer are corresponding with thyristor type.
Double buried layer mos gate control thyristors provided in an embodiment of the present invention and preparation method, double buried layer mos gate control crystalline substance locks
Pipe is respectively formed it in thyristor and parasitic triode area mainly by being provided with double N buried layer areas in drift region
On the one hand electronics potential well and hole barrier can extract electronic current and enter thyristor, improve effective trigger current density；Another party
Face can prevent hole current from entering parasitic triode, improve the hole current density for entering the base area thyristor P, the two collective effect
Promote positive feedback to establish, thyristor is accelerated to open, improves device opening speed, inhibits output snapback phenomenon, promote device
Functional reliability.
Detailed description of the invention
Fig. 1 is that base resistance controls thyristor (BRT) and firing current distribution schematic diagram in the prior art；
Fig. 2 is the schematic diagram that base resistance controls thyristor (BRT) output characteristic curve in the prior art；
Fig. 3 is the structural schematic diagram of the double buried layer mos gate control thyristors of one embodiment of the invention；
Fig. 4 is the structural schematic diagram of another embodiment of the present invention double channel mos gate control thyristor；
Fig. 5 is the structural schematic diagram of another embodiment of the present invention single-channel MOS grid-controlled transistor；
Fig. 6 is the schematic diagram of the double buried layer mos gate control thyristor opening process electronic current distributions of the present invention；
Fig. 7 is the schematic diagram of the double buried layer mos gate control thyristor opening process hole current distributions of the present invention；
Fig. 8 is the output characteristic curve of the double buried layer mos gate control thyristors of the present invention；
Fig. 9 is the opening feature curve of the double buried layer mos gate control thyristors of the present invention；
Figure 10 is the flow chart of the double buried layer mos gate control thyristor preparation methods of the present invention；
Figure 11 is the flow chart of the double buried layer mos gate control thyristor preparation process of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of double buried layer mos gate control thyristors, as shown in figure 3, the thyristor includes:
Substrate and drift region；
Double N buried layers, surface texture are successively provided in drift region from bottom to up；
The cathode and grid and the anode of substrate lower end surface of surface texture upper surface are set.
Double buried layer mos gate control thyristors provided in an embodiment of the present invention are mainly buried by being provided with double N in drift region
Floor area, and it is made to be respectively formed electronics potential well and hole barrier in thyristor and parasitic triode area, it on the one hand can extract electricity
Electron current enters thyristor, improves effective trigger current density；On the other hand hole current can be prevented to enter parasitic triode, mentioned
Height enters the hole current density of the base area thyristor P, and the two collective effect promotes positive feedback to establish, and accelerates thyristor to open, mentions
High device opening speed inhibits output snapback phenomenon, promotes device functional reliability.
Wherein, as shown in figure 3, structure described in the present embodiment successively includes anode A 27, substrate (20 He of P++ layer from the bottom to top
N+ layers 19), the drift region N- 18, double N buried layers 23, surface texture (15,16,17), grid oxic horizon 26, cathode K24 and grid
G25.Device main body is the thyristor 28 and surface NMOS (15,16,18) and PMOS that left side 15,16,18,19,20 is constituted
(16,18,17), device right side 17,18,19,20 constitute parasitic PNP triodes 29.
Optionally, as shown in figure 3, double N buried layers 23 include:
First N buried layer 21 of the first surface structure lower end on the left of drift region is set, and it is located in thyristor 28,
So that it forms electronics potential well in thyristor 28；
2nd N buried layer 22 of the second surface structure lower end on the right side of drift region is set, and it is located in triode 29,
So that it forms hole barrier in parasitic triode 29.
Optionally, the first N buried layer is oppositely arranged with the 2nd N buried layer.
Specifically, as shown in figure 3, double buried layer mos gate control thyristors described in the present embodiment there are three kinds of working conditions: 1. sun
Apply negative bias between pole A and cathode K, PN junction is in reverse bias between P++ layer 20 and N+ layer 19, between anode and cathode
There is no current flowing, device is in reverse blocking state；2. it is small to apply forward bias, grid G voltage between anode A and cathode K
When threshold voltage, surface NMOS is not turned on, and can not generate IGBT group electric current, still not have between device anode and cathode
There is current flowing, device is in forward blocking state at this time；3. applying forward bias and grid G electricity between anode A and cathode K
When pressure is greater than threshold voltage, NMOS conducting in surface generates electronic current and flows into drift region, and triggering thyristor structure is opened, at this time
Device is in forward conduction state.
When mos gate control thyristor anode A applies forward bias, grid G voltage is increased to threshold voltage or more by low level
When, device will turn on state by blocking state:
1, NMOS electronic current in surface first passes through conducting channel and laterally circulates across the base area P 16, then flows downwardly into N- drift
Area 18 is moved, as the ideal base drive current of lower section width base area PNP transistor (16,18,19,20), thyristor 28 is triggered and opens.By
In the parasitic PNP triode of presence, and 16 17 junction depths of the area junction depth ratio P+ of the base area P are big, and part electronic current can be pushed into three poles of right side
Area under control (as shown in Fig. 1 curve 11), so that the effective trigger current density of thyristor 28 declines.And mos gate control described in the present embodiment
In thyristor, the first N buried layer 21 forms electronics potential well in thyristor 28, can extract surface electronic electric current and enter thyristor 28,
Effective trigger current density is greatlyd improve, thyristor is accelerated to open.As shown in fig. 6, mos gate control thyristor described in the present embodiment
Electronic current distribution in opening process, curve 58,59,60 are electron flow path diameter.
2, after electronic current is downwardly into N+ buffer layer 19 by the drift region N- 18, P++ layer 20 can be promoted by P++ layers and N+
Hole injection occurs upwards and enters to maintain charge balance for PN junction between layer 19.A large amount of hole currents successively flow into N+ layers upwards
19, the drift region N- 18, until being drawn into the base area P 16 by reverse-biased N-/P knot.Also due to there is parasitic PNP triode, part
Hole current directly can be drawn into cathode K (as shown in Fig. 1 curve 13) by the reverse-biased N-/P+ knot in right side, make into the base area P 16
Hole current density decline.In mos gate control thyristor described in the present embodiment, the 2nd N buried layer 22 is formed in parasitic PNP triode
Hole barrier prevents the hole current to circulate upwards from being drawn into cathode by reverse-biased N-/P+ knot, and hole current is promoted to enter a left side
Hole current density in the base area thyristor P 16 is greatly improved in the side base area P 16, and thyristor is accelerated to open.As shown in fig. 7, this implementation
The example mos gate control thyristor opening process hole current distribution, curve 61,62,63,64 is hole flow path.
Therefore, double N buried layers 21 described in the present embodiment form electronics potential well and hole barrier, and it is effective can to improve simultaneously thyristor
Trigger current density, the enhancing base area P hole current density, accelerate thyristor area to open, and improve mos gate control thyristor and open speed
Degree inhibits output characteristics snapback phenomenon.As shown in Fig. 8 output characteristic curve, with common mos gate control thyristor (dotted line) phase
Than mos gate control thyristor output characteristic described in the present embodiment does not have snapback phenomenon.As shown in Fig. 9 opening feature curve, this
Mos gate control thyristor (solid line) opening speed described in embodiment is faster than common mos gate control thyristor (dotted line).
In addition, buried layer electronics potential well and the size of hole barrier are closely related with doping concentration: improving buried layer doping concentration
Electronics potential well can be increased, improve hole barrier, the inhibiting effect of promotion and snapback phenomenon to device opening speed is more
Strongly.
Optionally, the size of the electronics potential well is corresponding with the doping concentration of the first N buried layer 21；
Preferably, the size of the hole barrier and the doping concentration of the 2nd N buried layer 22 with it is corresponding.
Optionally, the first N buried layer 21 and the spacing between the 2nd N buried layer 22 are corresponding with thyristor type.
Specifically, entering the base area P 16 while the first N buried layer 21 extraction electronics enters thyristor to hole and existing
Certain inhibiting effect, therefore, the spacing of the first N buried layer 21 and the 2nd N buried layer 22 will affect device opening speed promotion and
The inhibition of snapback phenomenon.When buried layer spacing is excessive, electronics extraction effect and hole barrier act on relatively weak, device performance
It is promoted unobvious；When buried layer spacing is too small, electronics extraction effect and hole barrier effect clash, device performance promoted also by
To influence.Therefore, the present embodiment is by the first N buried layer 21 and the 2nd N buried layer 22 set in the mos gate control thyristor
Between spacing reasonably optimizing value is carried out according to thyristor type and practical application request, device can be promoted to the maximum extent
Opening speed inhibits snapback phenomenon.
Double N buried structure designs described in the present embodiment can also be used for Emitter-Switched Thyristor (EST), such as Fig. 4 and Fig. 5 institute
Show, respectively using the double channel of double N buried layers (39,53), single-groove road Emitter-Switched Thyristor (EST) structure.
The embodiment of the present invention also provides a kind of double buried layer mos gate control thyristor preparation methods, as shown in Figure 10 and Figure 11, institute
The method of stating includes:
S11, substrate and drift region are prepared；
S12, double N buried layers, surface texture are successively prepared in drift region from bottom to up；
S13, it metallizes in surface texture upper surface and substrate lower end surface, preparation forms cathode, grid, anode.
Double buried layer mos gate control thyristor preparation methods provided in an embodiment of the present invention, mainly by being made in drift region
Standby double N buried layer areas, and it is made to be respectively formed electronics potential well and hole barrier in thyristor and parasitic triode area, on the one hand may be used
It extracts electronic current and enters thyristor, improve effective trigger current density；On the other hand hole current can be prevented to enter parasitism three
Pole pipe improves the hole current density for entering the base area thyristor P, and the two collective effect promotes positive feedback to establish, and accelerates thyristor
It opens, improves device opening speed, inhibits output snapback phenomenon, promote device functional reliability.
Wherein, as shown in figure 3, according to the structure of the method preparation from the bottom to top successively including anode in the present embodiment
A27, substrate (P++ layer 20 and N+ layer 19), the drift region N- 18, double N buried layers 23, surface texture (15,16,17), grid oxic horizon
26, cathode K24 and grid G 25.Device main body is the thyristor 28 and surface NMOS that left side 15,16,18,19,20 is constituted
(15,16,18) and PMOS (16,18,17), device right side 17,18,19,20 constitute parasitic PNP triodes 29.
Optionally, as shown in figure 11, pair N buried layers that prepare in drift region include:
First surface structure lower end on the left of drift region prepares the first N buried layer, so that it forms electronics in thyristor
Potential well；
Second surface structure lower end on the right side of drift region prepares the 2nd N buried layer, so that its shape in parasitic triode area
At hole barrier.
Optionally, the first N buried layer is oppositely arranged with the 2nd N buried layer.
Optionally, the size of the electronics potential well is corresponding with the doping concentration of the first N buried layer；
Preferably, the size of the hole barrier is corresponding with the doping concentration of the 2nd N buried layer.
Optionally, the first N buried layer and the spacing between the 2nd N buried layer are corresponding with thyristor type.
The method of the present embodiment can be used for preparing the technical solution of above structure embodiment, realization principle and technology
Effect is similar, and details are not described herein again.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of double buried layer mos gate control thyristors characterized by comprising
Substrate and drift region；
Double N buried layers, surface texture are successively provided in drift region from bottom to up；
The cathode and grid and the anode of substrate lower end surface of surface texture upper surface are set.
2. thyristor according to claim 1, which is characterized in that double N buried layers include:
First N buried layer of the first surface structure lower end on the left of drift region is set, so that it forms electronics gesture in thyristor
Trap；
2nd N buried layer of the second surface structure lower end on the right side of drift region is set, so that it is formed in parasitic triode area
Hole barrier.
3. thyristor according to claim 2, which is characterized in that the first N buried layer is oppositely arranged with the 2nd N buried layer.
4. thyristor according to claim 2 or 3, which is characterized in that the size of the electronics potential well is buried with the first N
The doping concentration of layer is corresponding；
Preferably, the size of the hole barrier is corresponding with the doping concentration of the 2nd N buried layer.
5. according to thyristor described in claim 2-4 any one, which is characterized in that the first N buried layer is buried with the 2nd N
Spacing between layer is corresponding with thyristor type.
6. a kind of double buried layer mos gate control thyristor preparation methods characterized by comprising
Prepare substrate and drift region；
Double N buried layers, surface texture are successively prepared in drift region from bottom to up；
It metallizes in surface texture upper surface and substrate lower end surface, preparation forms cathode, grid, anode.
7. preparation method according to claim 6, which is characterized in that described to prepare double N buried layers in drift region and include:
First surface structure lower end on the left of drift region prepares the first N buried layer, so that it forms electronics potential well in thyristor；
Second surface structure lower end on the right side of drift region prepares the 2nd N buried layer, so that it forms sky in parasitic triode area
Cave potential barrier.
8. preparation method according to claim 7, which is characterized in that the first N buried layer is opposite with the 2nd N buried layer to be set
It sets.
9. preparation method according to claim 7 or 8, which is characterized in that the size of the electronics potential well and the first N
The doping concentration of buried layer is corresponding；
Preferably, the size of the hole barrier and the doping concentration of the 2nd N buried layer with it is corresponding.
10. according to any preparation method of claim 7-9, which is characterized in that the first N buried layer and the 2nd N
Spacing between buried layer is corresponding with thyristor type.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809167A (en) * | 2021-08-10 | 2021-12-17 | 西安理工大学 | BRT with buried layer and manufacturing method thereof |
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| US20090072242A1 (en) * | 2007-09-18 | 2009-03-19 | Cree, Inc. | Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication |
| CN105679819A (en) * | 2016-03-18 | 2016-06-15 | 电子科技大学 | Reverse conducting MOS gate-controlled thyristor and fabrication method thereof |
| CN109616517A (en) * | 2018-12-12 | 2019-04-12 | 中国科学院微电子研究所 | Base resistance controls thyristor, Emitter-Switched Thyristor and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923051A (en) * | 1996-04-24 | 1999-07-13 | Abb Research Ltd. | Field controlled semiconductor device of SiC and a method for production thereof |
| CN1689144A (en) * | 2002-08-14 | 2005-10-26 | 先进模拟科技公司 | Isolated complementary MOS devices in epi-less substrate |
| US20090072242A1 (en) * | 2007-09-18 | 2009-03-19 | Cree, Inc. | Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication |
| CN105679819A (en) * | 2016-03-18 | 2016-06-15 | 电子科技大学 | Reverse conducting MOS gate-controlled thyristor and fabrication method thereof |
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| CN113809167A (en) * | 2021-08-10 | 2021-12-17 | 西安理工大学 | BRT with buried layer and manufacturing method thereof |
| CN113809167B (en) * | 2021-08-10 | 2024-01-09 | 西安理工大学 | BRT with buried layer and manufacturing method thereof |
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