CN109874387B

CN109874387B - Modular multilevel converter with cells organized into clusters

Info

Publication number: CN109874387B
Application number: CN201680088483.2A
Authority: CN
Inventors: S·诺加; A·纳米; F·迪吉库伊曾; K·伊尔维斯; 冈崎佑平
Original assignee: ABB Schweiz AG
Current assignee: Hitachi Energy Co ltd
Priority date: 2016-09-19
Filing date: 2016-09-19
Publication date: 2020-05-15
Anticipated expiration: 2036-09-19
Also published as: CN109874387A; WO2018050256A1

Abstract

A modular multilevel converter comprising phase legs with cells organized in clusters and a converter control structure comprising control target control means (12), at least one cluster selection means (14A, 4B) and cluster control means (16A, 16J), one cluster control cell per cluster, wherein the control target control means (12) determines the number of cells of a phase leg that need to be used in order to meet a control target

And informing the cluster selection means (14A), the cluster selection means (14A) obtaining a cluster voltage measurement value from each cluster control means (16A, 16J)

At least one first cluster (CL1) is selected based on the acquired cluster voltage measurements using an inter-cluster priority scheme and the first cluster control means (16A) is instructed to control the cells of the first cluster, which then selects the cells according to an intra-cluster cell priority scheme and controls them to change the conductive state.

Description

Modular multilevel converter with cells organized into clusters

Technical Field

The present invention relates to a modular multilevel converter, and a method and a computer program product for controlling cells in the modular multilevel converter.

Background

Modular multilevel converters are of interest for use in many different power transmission environments. They may for example be used as voltage source converters in Direct Current (DC) power transmission systems, such as High Voltage Direct Current (HVDC), and Alternating Current (AC) power transmission systems, such as Flexible Alternating Current Transmission Systems (FACTS).

In these converters there are a plurality of cascaded cells, each comprising a plurality of switches and energy storage elements providing cell voltages, wherein the cells can be controlled to assist in forming a waveform in a phase leg by inserting or extracting cell voltages from the phase leg.

At the same time, the voltage levels to be provided by these converters have increased, for example to achieve increased power transfer capability with the same or lower converter losses. Voltage levels of 800kV and above are known to have been used in Ultra High Voltage Direct Current (UHVDC) systems, for example.

One obvious way to enhance the transmission capacity is by simply stacking multiple cells together. However, when doing so, additional problems may arise.

It may be difficult to modulate the voltage synthesizing the multiple cells at a reasonably low switching frequency. It may be difficult to achieve sufficient insertion time for each unit in order to achieve proper switching action. It may be difficult to obtain a control structure capable of handling multiple input/output (I/O) signals.

The present invention is provided to address one or more of these issues.

Disclosure of Invention

The invention aims to provide sufficient cell insertion time for a modular multilevel converter with a plurality of cells.

According to a first aspect, the object is achieved by a modular multilevel converter comprising at least one phase leg with a plurality of series-connected cells, wherein the cells are configured to provide at least one voltage contribution, the at least one voltage contribution assisting in the formation of an alternating current waveform, and wherein the cells of the phase leg are organized into clusters, the converter further comprising a converter control structure comprising control target control means, at least one cluster selection means and a plurality of cluster control means, one cluster control means per cluster,

wherein the control target controlling means is configured to determine the number of cells of the phase leg that need to be used during the current time interval in order to meet the control target, and to notify the cluster selecting means of the number,

the cluster selection means is configured to:

cluster voltage measurements are obtained from each cluster control device,

selecting at least one first cluster based on the acquired cluster voltage measurements using an inter-cluster priority scheme, an

Instructing the first cluster control means to control the selected cells of the first cluster for allowing the control objective to be met, and

the first cluster control apparatus is configured to: according to the intra-cluster cell priority scheme, cells of the first cluster are selected and the selected cells are controlled to change the conducting state in the current time interval.

According to a second aspect, the object is achieved by a method of controlling cells in a modular multilevel converter comprising at least one phase leg having a plurality of series-connected cells, the cells being configured to provide at least one voltage contribution, the at least one voltage contribution assisting in the formation of an alternating current waveform, and wherein the cells of the phase leg are organized into clusters, the method being performed in a converter control structure and comprising:

determining the number of cells of the phase leg that need to be used during the current time interval in order to meet the control objective,

a cluster voltage measurement is taken from each cluster,

According to the intra-cluster cell priority scheme, cells of the first cluster are selected and the selected cells are controlled to change the conduction state in the current time interval for allowing the converter control structure to meet the control target.

According to a third aspect, the object is achieved by a computer program product for controlling cells in a modular multilevel converter comprising at least one phase leg having a plurality of series-connected cells, the cells being configured to provide at least one voltage contribution, the at least one voltage contribution assisting in the formation of an alternating current waveform, and wherein the cells of the phase leg are organized into clusters, the computer program product comprising a data carrier with computer program code configured to cause a converter control structure to:

a cluster voltage measurement is taken from each cluster,

The present invention has many advantages. The distributed control architecture may reduce I/O requirements and computational tasks for individual control devices. The converter can meet the requirements of a low-loss and small three-phase alternating current filter, and has independent reactive power control and black start capability. Also, the number of cells per arm can be increased without increasing control structure capability, control complexity, and without degrading capacitor voltage balancing capability. By using the clustering concept, factory assembly can be done to a greater extent. Cluster assembly can also be performed where the converter is to be installed to meet these requirements. The cluster can be adapted to a maximum suitable size and weight for transport (e.g., a container). In addition, larger devices may also be factory tested and soldered in clusters, thereby speeding up field work and commissioning and reducing the likelihood of new failure (infant failures). Maintenance and repair can be made easier since the entire cluster can be kept as a spare and easily replaced.

Drawings

The invention will be described with reference to the accompanying drawings, in which:

figure 1 schematically shows a modular multilevel voltage source converter connected between a pole and ground and comprising cells grouped in clusters,

figure 2 schematically shows a converter control architecture provided for a voltage source converter and control unit cluster,

figure 3 schematically shows the variation of the cell voltage and the cluster voltage measurements between the first and second upper voltage levels and the first and second lower voltage levels,

figure 4 shows a flow chart of a number of method steps performed by the control target control means of the converter control architecture,

figure 5 shows a flow chart of a number of method steps performed by the cluster selection means of the converter control architecture,

figure 6 shows a number of method steps performed by the cluster control means of the converter control architecture,

figure 7 schematically shows a first way of controlling the units of a cluster,

figure 8 schematically shows a second way of controlling the units of a cluster,

fig. 9 schematically shows a third way of controlling the cells of a cluster, an

Fig. 10 schematically shows a computer program product computer program medium comprising computer program code for implementing at least part of the control structure.

Detailed Description

Hereinafter, a detailed description will be given of preferred embodiments of the present invention.

Fig. 1 shows a simplified variant of a multilevel converter in the form of a cell-based voltage source converter 10 or a Modular Multilevel Converter (MMC). Inverters are used to convert between Alternating Current (AC) and Direct Current (DC). The converter 10 in fig. 1 comprises a three-phase bridge consisting of a plurality of phase legs. In this case there are three phase legs. However, it should be appreciated that as an alternative there may be, for example, only two phase legs. Thus, there is a first phase leg PL1, a second phase leg PL2 and a third phase leg PL 3. The phase leg is more particularly connected between a first DC terminal DC1, which may be connected to a first pole P1 of a DC power transmission system, such as a High Voltage Direct Current (HVDC) power transmission system, and a second DC terminal DC2, which may be connected to ground, wherein the midpoint of the phase leg is connected to the corresponding alternating current terminal ACA, ACB, ACC. In this example, the phase leg is divided into two halves: a first upper half and a second lower half, wherein such halves are also referred to as phase arms.

Furthermore, the first DC pole P1 has a first potential Udp, which may be positive. Therefore, the first pole P1 may also be referred to as a positive pole. The AC terminals ACA, ACB, ACC may in turn be connected to an AC system, such as a Flexible Alternating Current Transmission System (FACTS), for example via a transformer. The phase arm between the first pole P1 and the first AC terminals ACA, ACB and ACC may be referred to as a first phase arm or an upper phase arm, and the phase arm between the first AC terminal and ground may be referred to as a second phase arm or a lower phase arm.

HVDC systems may more specifically be ultra high voltage direct current systems (UHVDC) operating at 800kV and above.

As mentioned above, a voltage source converter of the type shown in fig. 1 is only one example of a modular multilevel converter in which the invention may be used. For example, a current transformer may be used as a reactive compensation device, such as a static VAR compensator.

The voltage source converter 10 depicted in fig. 1 has an asymmetric unipolar configuration. It is therefore connected between the pole and ground. Alternatively, it may be connected in a symmetrical unipolar configuration or a symmetrical bipolar configuration. In a symmetrical unipolar configuration, the second DC terminal DC2 would be connected to a second pole having a second negative potential, which may be as large as the first potential but of opposite polarity. In a symmetric bipolar configuration, a second pole is also present. In a bipolar configuration there will also be third and fourth phase arms in the phase leg, where the second and third phase arms will be connected to ground, the first phase arm is connected between the positive voltage of the first pole P1 and the second phase arm, and the fourth phase arm is connected between the negative voltage of the second pole and the third phase arm. The first AC terminal of a phase leg will be disposed between the first and second phase arms in a symmetrical bipolar configuration, while the second AC terminal of the same phase leg will be disposed between the third and fourth phase arms. Further, the phase arm is connected to the AC terminal via a phase reactor.

The phase leg of the voltage source converter 10 in the example in fig. 1 comprises a cell (cell). A cell is a unit (unit) that can be switched to provide a voltage contribution to the voltage formed on the corresponding AC terminal. The cell then comprises one or more energy storage elements in parallel with one or both branches with switches, for example in the form of capacitors, wherein the switches can be switched to start facilitating the formation of the waveform by inserting a voltage contribution corresponding to the voltage of the energy storage elements. When the cell is to stop contributing to the formation of the waveform, the cell can also be exited by the operation of the switch.

The cells are advantageously connected in series or cascade in the phase leg.

In the simplified example given in fig. 1, there are six cells connected in series or cascaded in each phase leg. Thus, the upper phase arm of the first phase leg PL1 comprises six units C1p1, C2p1, C3p1, C4p1, C5p1 and C6p1, while the lower phase arm of the first phase leg PL1 comprises six units C1n1, C2n1, C3n1, C4n1, C5n1 and C6n 1. A first phase leg voltage Uvppa is present across the cells of the upper phase leg and a first phase leg current Ivppa flows in the upper phase leg. When the upper phase arm is connected to the first pole P1, it can also be considered to be a positive phase arm. A second phase leg voltage Uvpna is present across the cells of the lower phase leg, and a second phase leg current Ivpna flows in the lower phase leg. Further, the upper phase arm is linked to the AC terminal ACA via a first or upper arm reactor larm 1, while the lower phase arm is linked to the same AC terminal ACA via a second or lower arm reactor larm 2. In a similar manner, the upper phase arm of the second phase leg PL2 comprises six units C1p2, C2p2, C3p2, C4p2, C5p2 and C6p2, while the lower phase arm of the second phase leg PL2 comprises six units C1n2, C2n2, C3n2, C4n2, C5n2 and C6n 2. Finally, the upper phase arm of the third phase leg PL3 comprises six units C1p3, C2p3, C3p3, C4p3, C5p3 and C6p3, while the lower phase arm of the third phase leg PL3 comprises six units C1n3, C2n3, C3n3, C4n3, C5n3 and C6n 3. Further, the upper phase arm is coupled to the corresponding AC terminals ACB and ACC via corresponding first or upper arm reactors Lbarm1 and Lcarm1, respectively, while the lower phase arm is coupled to the same AC terminals ACB and ACC via corresponding second or lower arm reactors Lbarm2 and Lcarm2, respectively.

The number of cells provided in fig. 1 is merely an example for illustrating the principle for organizing cells. It must therefore be emphasized that the number of cells in a phase leg may be rather high, such as for example one thousand.

To improve the way such high numbers of cells are handled, the cells are grouped or organized into clusters, and each cluster may include a fixed number of phase arm cells physically close to each other. In fig. 1, only clusters in the upper phase are shown. In this example, the cells C1n1 and C2n1 form a first cluster CL1, the cells C3n1 and C4n1 form a second cluster CL2, and the cells C5n1 and C6n1 form a third cluster CL 3. It has to be emphasized that a cluster may comprise more than two units. An exemplary number of alternatives given later is 10.

The same type of clustering is also performed in the other phase arms.

The contribution of a cell in the phase leg to meeting a voltage reference, which may be set to provide a waveform meeting a control objective, is typically controlled by providing a control signal to the cell to control the cell's contribution to meeting the voltage reference in order to achieve some power transfer, such as active or reactive power transfer. The unit may thus be controlled for achieving various goals, of which the shape of the waveform may be one. For the control unit, a converter control structure is provided. The converter control architecture for the phase leg comprises a control target control device 12, one or more cluster selection devices 14 and a plurality of

cluster control devices

16a, 16B, 16C, one cluster control device per cluster. Thus, there is a first cluster control means 16A for controlling the cells C1p1 and C2p1 in the first cluster CL1, a second cluster control means 16B for controlling the cells C3p1 and C4p1 in the second cluster CL2, and a third cluster control means 16C for controlling the cells C5p1 and C6o1 in the third cluster CL 3. The cells C1p1, C2p1, C3p1, C4p1, C5p1 and C6p1 report cell voltage, current and temperature to the corresponding

cluster control devices

16A, 16B and 16C and receive control signals from the

cluster control devices

16A, 16B and 16C, which is indicated by the double dashed arrows. The cluster control means 16A, 16B and 16C also communicate with the cluster selection means 14, which communication is also indicated by a dashed double arrow. The cluster selection means 14 in turn communicate with the control target control means 12, which is also indicated by a double-dashed arrow. Communication may be provided via a communication channel, such as an optical communication channel.

As described above, the illustrated control structure is provided for one phase arm. A similar control structure may be provided for each phase arm. In this case, the control-target control device 12 may be common to two cluster selection devices 14, wherein one cluster selection device is provided for the upper phase leg and the other cluster selection device is provided for the lower phase leg. As an alternative, it is possible that there is only one cluster selection means for the entire phase leg, which is particularly advantageous in case a full-bridge cell is used. Furthermore, the same type of structure may be provided for all phase legs. In this case, the control target control device 12 is also common to all the phase legs. Alternatively, one control target control device may be provided for each phase leg.

The control structure may be implemented by one or more computers. It may also be implemented, by way of example, using one or more Field Programmable Gate Arrays (FPGAs).

In the control structure, the

cluster control devices

16A, 16B, 16C are typically arranged close to the cluster of a unit, while the other devices are located at a distance from the unit. The cluster control means 16A, 16B, 16C may be connected to the cluster selection means via a cable, e.g. by optical fibres.

Fig. 2 schematically shows a control structure of a phase leg, in which there is a common control target control device 12, two

cluster selection devices

14A and 14B (one cluster selection unit per phase arm), and a plurality of cluster control devices, of which the only cluster control device shown is the cluster control device of the upper phase arm and then only the first cluster control device 16A and the last cluster control device 16J are shown. Also, in this example, there are 1000 cells in each phase leg, with each cluster including 10 cells. To simplify the figure, only the first and tenth cells of the first cluster and the first thousand cells of (the tenth cluster) are shown. Further, of the controls provided by the

cluster control devices

16A and 16J, only the control performed by the first cluster control device 16A associated with the first cluster CL1 is indicated. All of which are included merely to simplify the understanding of various aspects of the invention.

In the figure, the control target control device 12 is shown to acquire the control value P as the desired active power value and reactive power value^*、Q^*And desired cell capacitor value

(i.e., the desired cell voltage value of the energy storage element). The control target control device 12 is also shown to provide an upper limit voltage index or phase arm voltage reference to the first cluster selection device 14A

And provides a lower bound voltage index or phase leg voltage reference to the second cluster selection means 14B

The control target control device 14 is further shown to receive the average upper phase leg voltage from the first cluster selection device 14A

And receives the average lower phase leg voltage from the second cluster selection device 14B

Furthermore, the first cluster selection means 14A is shown to provide the first cluster control means 16A with a cluster index

And receives the average cell voltage level from the first cluster control device 16A

And information indicating the potentially excluded units. The information indicating the potentially excluded cell is here the maximum allowed index n_maxAnd a minimum allowed index n_minIn the form of (1). The first cluster selection means 14A is further shown to send the cluster index to the last cluster control means 14J of the upper phase leg

The first cluster control means 16A are again shown to send control signals S to the first and tenth units of the first cluster CL1₁And S₁₀And cell voltage measurement values v are obtained from these cells_C1And v_C10。

As can be seen in fig. 2, the converter should comprise a large number of cells, such as one thousand cells. This leads to various problems such as difficulty in modulating the voltage at reasonably low switching frequencies, difficulty in achieving sufficient insertion time for each cell to achieve proper switching action, and difficulty in obtaining a control structure capable of handling thousands of input/output (I/O) signals.

Of these problems, the insertion time may be the most severe.

To solve this, it is proposed that the control strategy is executed by a converter control structure.

How such control according to the control strategy is performed will now be described with reference to fig. 3, 4, 5 and 6, wherein fig. 3 shows cell voltage variations, fig. 4 shows a flow chart of a number of method steps performed by the control target control device 12, fig. 5 shows a flow chart of a number of method steps performed by the first cluster selection device 14A, and fig. 6 shows method steps performed by the selected cluster control device (e.g. the first cluster control device 16A).

As can be understood from fig. 3, the cell voltage is not static, but varies. The capacitors of the cells inserted in the phase leg are typically charged or discharged, depending on the direction of the current through the phase leg, with positive currents typically charging the cell capacitors and negative currents discharging the cell capacitors. Further, the cell voltage is allowed to vary between the first upper limit voltage level V1UL and the first lower limit voltage level V1LL, where cells that have reached the first upper limit voltage level V1UL are not allowed to be charged and cells that have reached the first lower limit voltage level V1LL are not allowed to be discharged. This means that cells at the first upper voltage level V1UL are not inserted for positive arm current, while cells at the first lower voltage level V1LL are not inserted for negative arm current. Then, a cell having a cell voltage close to the first upper limit voltage level may have a cell voltage variation V_CMAXWhile cells having a cell voltage near the first lower voltage limit level V1LL may have a cell voltage variation V_CMIN。

Furthermore, this principle can also be followed at the cluster level. The cluster control 16 may obtain cell voltages of the cells and form a cluster voltage measurement, such as a cell voltage average V_CAVEThe cluster voltage measurement is allowed to vary between a second upper voltage level V2UL and a second lower voltage level V2LL, wherein the second upper voltage level V23UL is advantageously lower than the first upper voltage level V1UL and the second lower voltage level V2LL is higher than the first lower voltage level V1 LL. The cluster voltage measurements may be used to guide the selection of the cluster.

Thus, each cell control device acquires the cell voltages of the cells in the cluster and performs three activities. The first activity is to compare the respective cell voltages with a first upper limit voltage level V1UL to determine if any cell voltages are equal to or above the first upper limit voltage level V1UL, and the second activity is to compare the respective cell voltages with a first lower limit voltage level V1LL to determine if any cell voltages are equal to or below the first lower limit voltage levelV1 LL. In this way, it is determined which cells to exclude in case the cluster is to be used to control the cells with the positive arm current and the negative arm current, respectively. By determining the previously mentioned maximum cluster index n_maxAnd minimum cluster index n_minTo determine the potentially excluded cells and provide these indices to the first cluster selection means 14A. Without excluding any units, the value of these indices will be equal to the total number of cluster units and zero cluster units. However, in the case where any cell has reached the first upper voltage level V1UL, then the maximum cluster index n_maxWill be reduced by an amount corresponding to the nominal cell voltage. In a similar manner, cells at or below the first lower voltage level V1LL will result in a minimum cluster index n_minBy an amount corresponding to the nominal cell voltage. The maximum and minimum cluster indices are then reported to the cluster selection device 14A. It can be seen that in this way information about potentially excluded cells in terms of both current directions is determined and reported to the cluster selection means, step 32. It should be recognized here that other ways of notification of potentially excluded cells may be used, such as directly giving the number of excluded cells for the first current arm direction and another number of excluded cells for the opposite current direction.

A third activity performed by each cell control means is to combine the values of the cell voltages in order to obtain the aforementioned cluster voltage measurement value, which then represents the voltage level of the cluster. This can be obtained as an average value of the cell voltage

Or average cell voltage. Another possibility is to use a sum. Alternatively, a median value of the cell voltage may be determined. The cluster voltage measurement is then also reported to the first cluster selection device 14A. Thereby, also the cluster voltage measurement value is determined and reported to the first cluster selecting means 14A, step 34.

The control performed by the control structure will now be described in more detail with respect to the upper phase arm of the first phase leg.

The control target control means 12 first determines the voltage to be provided in the upper phase leg for achieving the control target in the current time interval, step 18. In this example, the control objective is to have the desired active power P^*And desired reactive power Q^*With desired balanced cell voltage

And (4) matching. This control is merely an example of a control target and is known. The capacitor voltage control may more specifically be an open loop control or a closed loop control.

The active and reactive power control may be based on conventional measurements of active and reactive power (not shown), while the cell voltage balancing may be based on measured cell voltage average voltages in the upper and lower phase legs

And

to proceed with. Based on this data, the control-target control device 12 then determines the voltage reference for the upper phase leg in a manner known per se

And a voltage reference for the lower phase leg

Upper phase leg voltage reference

Essentially specifying the voltage or number of cells in the upper phase leg that are needed to help meet the reference (i.e., to meet the control objective) in the current time interval. Based on how many units were needed in the previous time interval, it can then be known how many units to insert or to eject in the current time interval.

Then, the cluster is switched to the first clusterSelection means 14A transmit reference

And thereby informs the first cluster selection means 14A of the cell voltage to be controlled, step 20.

Since control may be used to form the waveform, some cells may already be inserted into the phase arm, and therefore the cluster selection means knows how many additional cells need to be inserted, or how many already inserted cells need to be retired or removed.

Thus, the first cluster selecting means 14A receives a voltage reference, i.e. voltage insertion information on how many cells are needed in the current time interval for satisfying the control target, step 22, from the control target controlling means 12. It also indexes n by the maximum cluster_maxAnd minimum cluster index n_minReceives information from each cluster control means about the average cell voltage and the indication relating to the potentially excluded cell, step 24.

The cluster selection means 14A also has knowledge about the direction of the phase leg current. The cluster selection means 14A then selects the cluster to be inserted or to be withdrawn, step 26, based on the voltage reference, the current direction and the inter-cluster priority scheme (inter-cluster priority scheme) related to the phase leg current direction. The cluster selection means 14A here typically selects the cluster with the highest or lowest average cell voltage for insertion or withdrawal, wherein in case the current is the positive arm current charging the cell, the cluster with the lowest average cell voltage may be selected for insertion, or the cluster with the highest average cell voltage may be selected for withdrawal, and in case the current is the negative arm current discharging the cell, the cluster with the highest average cell voltage may be selected for insertion, or the cluster with the lowest average cell voltage may be selected for withdrawal.

Thereafter the cluster selection means 14A command the selected cluster control means to control the selected units of the first cluster for allowing the control target to be met, and in a way that avoids the use of the excluded units, step 28. As an indicationFor example, the cluster control device may be the first cluster control device 16A. The command may be generated by sending the modified cluster index to cluster control device 16A

To complete.

The units of the cluster are typically operated as one entity. All units except the excluded unit may be inserted or exited in the current time interval in general. This means that if no cell is excluded, the cluster index

Will correspond to the insertion of all cells in the cluster. However, when there are units to be excluded, i.e. not used, then the cluster index may be reduced by an amount corresponding to the number of excluded units. This means that the commands of the first cluster control means for controlling the units may comprise commands to omit excluded units from the control.

Furthermore, if no cell is excluded, there may be no need for other cluster participating cells to be inserted or withdrawn in order to reach the desired voltage level. However, if one or more cells are excluded from the cluster, it is highly likely that this level cannot be obtained.

Thus, in order to reach the desired voltage level, the cluster selection means may command the further cluster control means to control the desired number of cells needed to reach the phase arm, e.g. to compensate the voltage of the excluded cells, step 30. This means that if e.g. two further units need to be inserted, the cluster selection means 14A instructs the other cluster control means to insert two units, and if two units need to be exited, the cluster selection means instructs the other cluster control means to exit two units (which have previously been inserted into the selected cluster). This means that the excluded cell can be compensated by another cluster. The cluster associated with the further cluster control device may be a cluster of lower priority than the first cluster, e.g. the next cluster in order of priority. It may also be a special dedicated unit compensation cluster.

In other words, the cluster control means thus inserts the cell at the voltage limit, regardless of the original reference voltage at the cluster selection means. Thus, the actual insertion index may no longer be the same. The reference insertion index of the cluster control means may be corrected at the cluster selection means in such a way that the actual insertion index may be as close as possible to the reference voltage. The correction may be done by adding or subtracting an additional interpolation index to or from the reference voltage.

It may also be mentioned here that the cluster selection means may not make the change of cluster index, but the cluster control means itself adapts based on the number of excluded cells. However, the cluster selection means may still have to compensate for the excluded cells.

It may further be mentioned here that the required voltage change may also require more cells than in the cluster. In this case it is possible to command another cluster control means to control one or more units, even if all units of the selected cluster are not potentially excluded.

The selected cluster control device, which in the given example may be the first cluster control device 16A, then proceeds and selects the cell to operate and thereafter controls the selected cell to change the conducting state (i.e. insert or withdraw from the phase arm) in the current time interval, wherein the insertion/withdrawal may be performed according to an intra-cluster cell priority scheme related to the arm current direction, step 36. Thus, cells within the first upper or lower voltage level are selected, and cells at, above or below that voltage level are excluded, and other cells are controlled. For example, the selected cells may be processed in a priority order defined by the respective cell voltages. When there is a negative phase leg current, the cell with the highest cell voltage may be inserted first, and when there is a positive phase leg current, the cell with the lowest cell voltage may be inserted first. In a similar manner, the cell with the lowest cell voltage may be exited first when a negative phase leg current is present, and the cell with the highest cell voltage may be exited first when a positive phase leg current is present.

The priority order of the cells may also be organized at voltage zero crossings. Thus, the cluster selection means as well as each cluster control means may change the priority at the current zero crossing.

As can be seen in fig. 3, the cluster selection means obtains intra-cluster balance by adjusting the cluster voltage measurements (e.g. average capacitor voltage) of the clusters to within a certain frequency band. The cluster control means in turn obtain an intra-cluster balancing which adjusts the individual capacitor voltages in the cluster to within another frequency band, wherein each frequency band may be designed according to the acceptable capacitor voltages.

Furthermore, the manner in which elements in the cluster are inserted or exited in the current time interval may be performed according to some schemes. For example, a two-level scheme (two-level scheme) may be used, enabling the insertion or ejection of all cells simultaneously, a multi-level scheme (multistep scheme) may be used, in which cells are inserted in order step by step, or a random level scheme (random level scheme) may be used, in which a first group of cells is inserted first and then a second group of cells is inserted. The first case is shown in fig. 7, where a change of 20kV is made simultaneously for a first cluster CL1 of ten cells, each cell having a cell voltage of 2.5 kV. The second case is shown in fig. 8, where the change from 0 to 20kV is made in a number of equally sized steps, one step per unit. A third case is shown in fig. 9, where a change from 0 to 20kV is made using a random level, here in the form of two steps, of 10kV for the first cluster CL 1. In this case, half of the cells may be used for the first stage and half of the cells may be used for the second stage. Here, it may be mentioned that a voltage level of 2.5kV (which is also an example) may also be used in order to provide an error margin for the operation.

Furthermore, it is possible to use the first scheme shown in fig. 7 when the cell voltages are balanced, and to use the second and third schemes when the cell voltages are unbalanced. Therefore, the selection of the scheme can be made based on whether the respective cell voltages are balanced.

The choice of scheme can also be determined based on the Total Harmonic Distortion (THD) required for the three-phase converter voltage and the time required for the calculations and communications.

The present invention has many advantages.

It can be seen that the clusters can be considered as variable voltage sources, with harmonic cancellation occurring inside the clusters. That is, modulation and cell voltage balancing occur inside the cluster, thereby enabling significant simplification and benefits.

The distributed control architecture may reduce the I/O requirements and computational tasks of a single controller. Thus, the current source based thyristor converter rated at several GW currently installed can be replaced with an MMC based converter. The controller can achieve low loss, small three-phase ac filter requirements, independent reactive power control, and black start capability. Also, the number of cells per arm can be increased without increasing control structure capability, control complexity, and without degrading capacitor voltage balancing capability.

By using the clustering concept, factory assembly can be done to a greater extent. Cluster assembly may also be performed where equipment is to be installed to meet these requirements. The cluster can be adapted to a maximum suitable size and weight for transport (e.g., a container). In addition, larger devices can also be factory tested and soldered in clusters, thereby speeding up field work and commissioning and reducing the likelihood of novice failure.

Maintenance and repair can be made easier because the entire cluster can be kept as a spare cluster and easily replaced due to the use of simple interfaces for cooling and control signals. Given a simple interface, it is even conceivable to exchange clusters (by robots) automatically (hot-plug) during operation. In this way, maintenance interruptions can be avoided, reducing or even reversing the gap in reliability compared to conventional AC-based grid technologies.

In a preferred embodiment, the cluster control means may be provided at a potential close to the cells in the cluster. In this way, the control of the fiber link docking switch and the collection of signals do not have to measure the full voltage. The functions of the cluster control means may include modulation, cell capacitor voltage balancing and protection features. Thus, at least some low latency communications may remain within the cluster.

The auxiliary power required by the cluster may be taken, for example, from the capacitor voltage of one or more of the cells. Other options include fiber-over-fiber (power-over-fiber) or micro-turbines in the cooling water circuit.

The cluster control means may require only one bi-directional communication channel. Thus, two or more redundant fibers, each capable of handling the communication needs of a cluster, may be routed to each cluster control device along different physical paths without excessive cost. This may increase fault tolerance and thus reliability. In summary, this amounts to a much lower cost and increased reliability of the fiber optic communication link.

By implementing standard interfaces (cooling medium, control, electrical), interoperability clusters from different manufacturers can be achieved.

Another option is to have the clusters internally cooled and insulated by an alternative medium other than air (e.g., oil, SF6 gas, or other quality insulating or cooling medium). This can pave the way for a more compact design.

According to a further variant, the cluster may comprise units having different topologies and/or semiconductor technologies. One example is a combination of using 90% half bridge cells equipped with HV Gate Commutated Thyristors (GCTs) and 10% full bridge cells equipped with SiC MOSFETs of lower blocking voltage. In this configuration, the GCT can operate at the fundamental frequency while the SiC MOSFETs operate at a higher frequency. This allows for harmonic requirements to be met, although most semiconductors operate at a fundamental frequency. The result will be the use of HV semiconductors and a reduction in overall semiconductor losses.

Furthermore, the clusters may be connected in parallel with the thyristor switches. The clusters to be bypassed, i.e. the clusters in which all cells will provide a zero voltage contribution of the waveform, can then be bypassed by thyristor switches. This has the advantage of reducing conduction losses in the converter.

In the above description half-bridge cells are assumed. However, a full bridge cell may be used as well.

As mentioned above, the control structure may be implemented in the form of discrete components. However, it may also be implemented in the form of one or more processors, wherein the accompanying program memory comprises computer program code which, when run on the processor, performs the required control functions. A computer program product carrying such code may be provided as a data carrier, such as one or more CD ROM discs or one or more memory sticks carrying computer program code which, when loaded into a wave analyser, performs the wave analyser functions described above. One such data carrier in the form of a CD ROM disc 38 carrying computer program code 40 is shown in fig. 10.

It will be obvious from the foregoing discussion that the invention may be varied in many ways. It is therefore to be understood that the invention is solely limited by the following claims.

Claims

1. A modular multilevel converter (10) comprising at least one phase leg with a plurality of series connected cells (C1p1, C2p1, C3p1, C4p1, C5p1, C6p1), said cells being configured for providing at least one voltage contribution, said at least one voltage contribution assisting in the formation of an alternating current waveform, and wherein said cells of a phase leg are organized into clusters (CL1, CL2, CL3),

the converter further comprises a converter control structure comprising a control target control device (12), at least one cluster selection device (14, 14A, 14B) and a plurality of cluster control devices (16A, 16B, 16C, 16J), one cluster control device per cluster,

wherein

The control target control device (12) is configured to: determining the number of cells of a phase leg that need to be used during a current time interval in order to meet a control objective

And towards the clusterThe selection means (14A) informs of the number,

the cluster selection means (14A) is configured to:

obtaining a cluster voltage measurement from each cluster control device (16A, 16J)

And an indication relating to a potentially excluded cell within the corresponding cluster,

selecting at least one first cluster (CL1) based on the acquired cluster voltage measurements using an inter-cluster priority scheme, and

instructing a first cluster control means (16A) to control the selected units of the first cluster as one entity for allowing the control objective to be fulfilled, wherein all units except the excluded unit are to be inserted or taken out in the current time interval, and

commanding at least one other cluster control means to control the desired number of cells reaching the phase leg and any further cells needed to compensate the voltage of the excluded cell, and

the first cluster control means (16A) is configured to: selecting a cell of the first cluster and controlling the selected cell to change the conductive state in the current time interval according to an intra-cluster cell priority scheme.

2. The modular multilevel converter (10) of claim 1, wherein the excluded cells comprise cells excluded for the first current direction due to having a cell voltage equal to or higher than a first upper limit voltage level (V1UL) and/or cells excluded for the second current direction due to having a cell voltage equal to or lower than a first lower limit voltage level (V1 LL).

3. The modular multilevel converter (10) of claim 2, wherein the cluster voltage measurement is allowed to vary between a second upper voltage level (V2UL) and a second lower voltage level (V2LL), wherein the second upper voltage level (V2UL) is lower than the first upper voltage level (V1UL) and the second lower voltage level (V2LL) is higher than the first lower voltage level (V1 LL).

4. The modular multilevel converter (10) according to any of claims 1 to 3, wherein the cluster selection means and each cluster control means are configured to change the priority scheme at current zero crossings.

5. The modular multilevel converter (10) according to any of claims 1 to 3, wherein the selected cluster control means is operable to control the cells according to a two-level scheme or a random level scheme based on whether individual cell voltages are balanced.

6. The modular multilevel converter (10) according to any of claims 1 to 3, wherein each cluster further comprises a thyristor switch in parallel with the cluster, the thyristor switch being operable to conduct if the cluster is to be bypassed.

7. A method of controlling cells in a modular multilevel converter (10), the controlling modular multilevel converter (10) comprising at least one phase leg having a plurality of series connected cells (C1p1, C2p1, C3p1, C4p1, C5p1, C6p1), the cells being configured for providing at least one voltage contribution, the at least one voltage contribution assisting in the formation of an alternating current waveform, and wherein the cells of a phase leg are organized into clusters (CL1, CL2, CL3), the method being performed in a converter control structure (12, 14, 14A, 14B, 16A, 16B, 16C, 16J) and comprising:

determining (18) the number of cells of the phase leg that need to be used during the current time interval in order to meet the control objective

Obtaining (from each cluster (CL1, CL2, CL3) < 2 >24) Clustered voltage measurements

And an indication relating to a potentially excluded cell within the cluster,

selecting (26) at least one first cluster (CL1) based on the acquired cluster voltage measurements using an inter-cluster priority scheme, wherein all cells in the first cluster except excluded cells are to be controlled as one entity by being inserted or fetched in the current time interval,

selecting (36) a cell of the first cluster and controlling the selected cell to change the conduction state in the current time interval for allowing the converter control structure to meet the control target, according to an intra-cluster cell priority scheme, and

controlling (30) the desired number of cells reaching the phase leg and any further cells needed to compensate the voltage of the excluded cells.

8. The method of claim 7, wherein the excluded cells include cells excluded for a first current direction due to having a cell voltage equal to or higher than a first upper voltage level (V1UL), and/or cells excluded for a second current direction due to having a cell voltage equal to or lower than a first lower voltage level (V1 LL).

9. The method of claim 8, wherein the cluster voltage measurement is allowed to vary between a second upper voltage level (V2UL) and a second lower voltage level (V2LL), wherein the second upper voltage level (V2UL) is lower than the first upper voltage level (V1UL) and the second lower voltage level (V2LL) is higher than the first lower voltage level (V1 LL).

10. The method of any of claims 7 to 9, wherein the controlling of the selected unit in the first cluster comprises: the cells are controlled according to a two-level scheme or a random level scheme based on whether individual cell voltages are balanced.

11. A computer readable storage medium for controlling cells in a modular multilevel converter (10), the modular multilevel converter (10) comprising at least one phase leg having a plurality of series connected cells (C1p1, C2p1, C3p1, C4p1, C5p1, C6p1), the cells being configured for providing at least one voltage contribution, the at least one voltage contribution assisting in the formation of an alternating current waveform, and wherein the cells of a phase leg are organized into clusters (CL1, CL2, CL3), the computer readable storage medium comprising computer program code (40) stored thereon, which when executed by a processor causes a converter control structure (12, 14, 14A, 14B, 16A, 16B, 16C, 16J):

determining the number of cells of a phase leg that need to be used during a current time interval in order to meet a control objective

Obtaining cluster voltage measurements from each cluster (CL1, CL2, CL3)

And an indication relating to a potentially excluded cell within the cluster, wherein the excluded cell,

selecting at least one first cluster (CL1) based on the acquired cluster voltage measurements using an inter-cluster priority scheme, wherein all cells in the first cluster except excluded cells are to be controlled as one entity by being inserted or taken out in the current time interval,

selecting a cell of the first cluster and controlling the selected cell to change the conduction state in the current time interval for allowing the converter control structure to meet the control target, according to an intra-cluster cell priority scheme, and

the desired number of cells to reach the phase leg and any additional cells needed to compensate for the voltage of the excluded cells are controlled.