CN109873035A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN109873035A
CN109873035A CN201711262580.1A CN201711262580A CN109873035A CN 109873035 A CN109873035 A CN 109873035A CN 201711262580 A CN201711262580 A CN 201711262580A CN 109873035 A CN109873035 A CN 109873035A
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metal gates
clearance wall
dielectric layer
semiconductor element
hard mask
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CN109873035B (zh
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林静龄
梁文安
黄振铭
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202211053337.XA priority Critical patent/CN115621319A/zh
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Priority to US15/859,775 priority patent/US10679903B2/en
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Priority to US16/859,959 priority patent/US11569133B2/en
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法为，首先形成一鳍状结构于一基底上，然后形成一第一栅极结构以及一第二栅极结构于鳍状结构上以及一层间介电层环绕第一栅极结构以及第二栅极结构，将第一栅极结构以及第二栅极结构转换为第一金属栅极以及第二金属栅极，形成一硬掩模于第一金属栅极以及第二金属栅极上，去除部分硬掩模、第二金属栅极以及部分鳍状结构以形成一开口，再形成一介电层于凹槽内以形成一单扩散隔离结构。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种分隔鳍状结构以形成单扩散隔离(single diffusion break,SDB)结构的方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
在现行的鳍状场效晶体管元件制作工艺中，鳍状结构周围形成浅沟隔离后通常会以蚀刻方式去除部分鳍状结构与浅沟隔离形成凹槽，然后填入绝缘物以形成单扩散隔离结构并将鳍状结构分隔为两部分。然而现今单扩散隔离结构与金属栅极的制作工艺在搭配上仍存在许多问题，因此如何改良现有鳍状场效晶体管制作工艺与架构即为现今一重要课题。
发明内容
本发明一实施利公开一种制作半导体元件的方法。首先形成一鳍状结构于一基底上，然后形成一第一栅极结构以及一第二栅极结构于鳍状结构上以及一层间介电层环绕第一栅极结构以及第二栅极结构，将第一栅极结构以及第二栅极结构转换为第一金属栅极以及第二金属栅极，形成一硬掩模于第一金属栅极以及第二金属栅极上，去除部分硬掩模、第二金属栅极以及部分鳍状结构以形成一开口，再形成一介电层于凹槽内以形成一单扩散隔离结构。
本发明另一实施利公开一种半导体元件，其主要包含一鳍状结构设于基底上、一栅极结构设于鳍状结构上以及一层间介电层环绕栅极结构以及一单扩散隔离结构设于层间介电层以及鳍状结构内。其中单扩散隔离结构又细部包含一下半部以及一上半部设于下半部上，其中上半部以及下半部包含不同宽度。
附图说明
图1为本发明一实施例制作一半导体元件的上视图；
图2为图1中沿着切线AA'的剖面示意图；
图3至图10为接续图2制作一半导体元件的方法示意图；
图11为本发明一实施利的半导体元件的结构示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 浅沟隔离 18 栅极结构
20 栅极结构 22 栅极结构
24 栅极结构 26 栅极介电层
28 栅极材料层 30 间隙壁
32 源极/漏极区域 34 外延层
36 接触洞蚀刻停止层 38 层间介电层
40 介质层 42 高介电常数介电层
44 功函数金属层 46 低阻抗金属层
48 金属栅极 50 金属栅极
52 金属栅极 54 金属栅极
56 凹槽 58 硬掩模
60 图案化光致抗蚀剂 62 开口
64 开口 66 开口
68 衬垫层 70 介电层
72 单扩散隔离结构 74 气孔
76 下半部 78 上半部
具体实施方式
请参照图1至图10，其中图1为本发明一实施例制作一半导体元件的上视图，图2为图1中沿着切线AA'的剖面示意图，图3至图10则为接续图2制作一半导体元件的方法示意图。如图1至图2所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板。然后于形成多个鳍状结构14于基底12上。在本实施例中，设于基底12上的鳍状结构14虽以四根为例，但所设置的鳍状结构数量均可依据产品需求任意调整，并不局限于此。
依据本发明的优选实施例，鳍状结构14较佳通过侧壁图案转移(sidewall imagetransfer,SIT)等技术制得，其程序大致包括：提供一布局图案至电脑***，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构14。另外，鳍状结构14的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构14。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。
然后形成一浅沟隔离(shallow trench isolation,STI)16环绕鳍状结构14。在本实施例中，形成浅沟隔离16的方式可先利用一可流动式化学气相沉积(flowable chemicalvapor deposition,FCVD)制作工艺形成一氧化硅层于基底12上并完全覆盖鳍状结构14。接着利用化学机械研磨(chemical mechanical polishing,CMP)制作工艺并搭配蚀刻制作工艺去除部分氧化硅层，使剩余的氧化硅层低于鳍状结构14表面以形成浅沟隔离16。
接着于鳍状结构14上形成栅极结构18、20、22、24或虚置栅极。在本实施例中，栅极结构18、20、22、24的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，可先依序形成一栅极介电层或介质层、一由多晶硅所构成的栅极材料层以及一选择性硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分栅极材料层与部分栅极介电层，然后剥除图案化光致抗蚀剂，以于鳍状结构14上形成各由图案化的栅极介电层26与图案化的栅极材料层28所构成的栅极结构18、20、22、24。
然后在栅极结构18、20、22、24侧壁分别形成至少一间隙壁30，接着于间隙壁30两侧的鳍状结构14以及/或基底12中形成源极/漏极区域32及/或外延层34，并选择性于源极/漏极区域32及/或外延层34的表面形成一金属硅化物(图未示)。在本实施例中，间隙壁30可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁以及一主间隙壁。其中偏位间隙壁与主间隙壁可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。源极/漏极区域32可依据所置备晶体管的导电型式而包含不同掺质，例如可包含P型掺质或N型掺质。
接着先形成一接触洞蚀刻停止层36并覆盖栅极结构18、20、22、24及浅沟隔离16表面，再形成一层间介电层38于接触洞蚀刻停止层36上。然后进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)去除部分层间介电层38以及部分接触洞蚀刻停止层36并暴露出由多晶硅材料所构成的栅极材料层28，使栅极材料层28上表面与层间介电层38上表面齐平。
如图3所示，随后进行一金属栅极置换制作工艺将栅极结构18、20、22、24转换为金属栅极。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构18、20、22、24中的栅极材料层28甚至栅极介电层26，以于层间介电层38中形成凹槽(图未示)。
接着依序形成一选择性介质层40或栅极介电层、一高介电常数介电层42、一功函数金属层44以及一低阻抗金属层46于凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层46、部分功函数金属层44以及部分高介电常数介电层42以形成金属栅极48、50、52、54。以本实施例利用后高介电常数介电层制作工艺所制作的栅极结构为例，所形成的各金属栅极48、50、52、54较佳包含一介质层40或栅极介电层、一U型高介电常数介电层42、一U型功函数金属层44以及一低阻抗金属层46。
在本实施例中，高介电常数介电层42包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层44较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层44可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层44可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层44与低阻抗金属层46之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层46则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
随后如图4所示，进行一蚀刻制作工艺去除部分低阻抗金属层46、部分功函数金属层44以及部分高介电常数介电层42以形成凹槽56。
如图5所示，然后形成一硬掩模58于各凹槽56内，其中硬掩模58除了填满各凹槽56外又同时设于接触洞蚀刻停止层36以及层间介电层38上方。在本实施例中，硬掩模58较佳由氮化硅所构成，但不局限于此。
接着如图6所示，形成一图案化掩模，利如一图案化光致抗蚀剂60于硬掩模58上，其中图案化光致抗蚀剂60较佳包含一开口62暴露出部分硬掩模58表面。
然后如图7所示，利用图案化光致抗蚀剂60为掩模进行一蚀刻制作工艺或更具体而言一道或一道以上蚀刻制作工艺依序去除部分硬掩模58、部分接触洞蚀刻停止层36、部分间隙壁30以及部分金属栅极52，以于金属栅极52正上方的层间介电层38以及硬掩模58内形成开口64，之后再去除图案化光致抗蚀剂60。在本实施例中，用来去除部分硬掩模58的蚀刻气体较佳包含四氟化碳(CF4)，但不局限于此。
如图8所示，接着利用被图案化的硬掩模58为掩模进行另一蚀刻制作工艺或更具体而言一道或一道以上蚀刻制作工艺来依序去除剩余的金属栅极52以及金属栅极52下方的鳍状结构14，以于原本金属栅极52的位置形成约略T型的开口66并深入鳍状结构14内。在本实施例中，用来去除剩余金属栅极52的蚀刻气体较佳包含六氟化硫(SF6)，但不局限于此。
需注意的是，由于开口较佳以去除原本金属栅极52的方式所形成，因此所形成的开口66延伸方向较佳比照原本栅极结构22或金属栅极52的延伸方向。换句话说相较于鳍状结构14如图1所示沿着一第一方向(例如X方向)延伸，所形成的开口66较佳沿着与第一方向垂直的第二方向(例如Y方向)延伸。
随后如图9所示，依序形成一衬垫层68以及一介电层70于硬掩模58上并填满开口66。在本实施例中，衬垫层68以及介电层70较佳由不同材料所构成且两者均可选自由氧化硅以及氮化硅所构成的群组。举例来说，本发明一实施利可依序沉积由氮化硅所构成的衬垫层68以及由氧化硅所构成的介电层70于开口66内，或可依序沉积由氧化硅所构成的衬垫层68以及由氮化硅所构成的介电层70于开口66内，这些变化型均属本发明所涵盖的范围。
如图10所示，然后进行一平坦化制作工艺，例如以CMP以及/或回蚀刻制作工艺去除部分介电层70、部分衬垫层68以及部分硬掩模58，使剩余的介电层70以及衬垫层68上表面切齐层间介电层38以及剩余硬掩模58上表面以形成一单扩散隔离结构72。如同前述开口66所延伸的方向，相较于鳍状结构14如图1所示沿着一第一方向(例如X方向)延伸，本阶段所形成的单扩散隔离结构72较佳沿着与第一方向垂直的第二方向(例如Y方向)延伸。
请继续参照图10，图10为本发明一实施利的半导体元件的结构示意图。如图10所示，半导体元件主要包含鳍状结构14设于基底上，栅极结构或金属栅极48、50、54设于鳍状结构14上、层间介电层38环绕金属栅极48、50、54、单扩散隔离结构72设于层间介电层38以及鳍状结构14内、间隙壁30环绕金属栅极48、50、54以及单扩散隔离结构72以及接触洞蚀刻停止层36设于间隙壁30之间。
从细部来看，单扩散隔离结构72又包含一下半部76以及一上半部78设于下半部76上，其中上半部78以及下半部76包含不同宽度，或更具体而言上半部78宽度较佳大于下半部76宽度。另外上半部78以及下半部76又各包含一衬垫层68以及一介电层70设于衬垫层68上且衬垫层68以及介电层70较佳包含不同材料。
需注意的是，在本实施例中分别环绕金属栅极48、50、54以及单扩散隔离结构72的间隙壁30较佳包含不同高度，例如环绕金属栅极50的间隙壁30上表面较佳切齐层间介电层38上表面并高于环绕单扩散隔离结构72的间隙壁30上表面，而环绕单扩散隔离结构72周围的间隙壁30上表面则较佳切齐下半部76以及接触洞蚀刻停止层36上表面。另外接触洞蚀刻停止层36虽较佳包含U型，但从细部来看设于单扩散隔离结构72旁的接触洞蚀刻停止层36上表面较佳低于金属栅极50旁的接触洞蚀刻停止层36上表面。
请继续参照图11，图11为本发明一实施利的半导体元件的结构示意图。如图11所示，本发明可于图10进行平坦化制作工艺，例如以CMP以及/或回蚀刻制作工艺去除部分介电层70、部分衬垫层68以及部分硬掩模58形成单扩散隔离结构72的同时形成一气孔74于单扩散隔离结构72内。此实施例也属本发明所涵盖的范围。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的保护范围。

Claims (20)

1.一种制作半导体元件的方法，其特征在于，包含：
形成一鳍状结构于一基底上；
形成一第一栅极结构以及一第二栅极结构于该鳍状结构上以及一层间介电层环绕该第一栅极结构以及该第二栅极结构；
将该第一栅极结构以及该第二栅极结构转换为一第一金属栅极以及一第二金属栅极；
形成一硬掩模于该第一金属栅极以及该第二金属栅极上；
去除部分该硬掩模、该第二金属栅极以及部分该鳍状结构以形成一开口；以及
形成一介电层于该凹槽内以形成一单扩散隔离结构。
2.如权利要求1所述的方法，另包含：
形成一第一间隙壁环绕该第一栅极结构以及一第二间隙壁环绕该第二栅极结构；
形成一接触洞蚀刻停止层环绕该第一间隙壁以及该第二间隙壁；
形成该层间介电层于该接触洞蚀刻停止层上；
去除部分该第一金属栅极以及部分该第二金属栅极以形成一第一凹槽以及一第二凹槽；以及
形成该硬掩模于该第一凹槽以及该第二凹槽内。
3.如权利要求2所述的方法，另包含于去除该第二金属栅极之前去除部分该硬掩模以及部分该第二间隙壁。
4.如权利要求2所述的方法，另包含于去除该第二金属栅极之前去除部分该硬掩模、部分该接触洞蚀刻停止层以及部分该第二间隙壁。
5.如权利要求1所述的方法，另包含于形成该介电层之前形成一衬垫层于该开口内。
6.如权利要求5所述的方法，其中该衬垫层以及该介电层包含不同材料。
7.如权利要求5所述的方法，另包含平坦化部分该介电层、部分该衬垫层以及部分该硬掩模并使该单扩散隔离结构上表面切齐该硬掩模上表面。
8.如权利要求1所述的方法，另包含于形成该单扩散隔离结构同时形成一气孔于该单扩散隔离结构内。
9.如权利要求1所述的方法，其中该鳍状结构沿着一第一方向延伸且该单扩散隔离结构沿着一第二方向延伸。
10.如权利要求9所述的方法，其中该第一方向垂直该第二方向。
11.一种半导体元件，其特征在于，包含：
鳍状结构，设于一基底上；
栅极结构，设于该鳍状结构上以及一层间介电层环绕该栅极结构；
单扩散隔离结构，设于该层间介电层以及该鳍状结构内，该单扩散隔离结构包含：
下半部；以及
上半部，设于该下半部上，其中该上半部以及该下半部包含不同宽度。
12.如权利要求11所述的半导体元件，另包含：
第一间隙壁，环绕该金属栅极；
第二间隙壁，环绕该单扩散隔离结构；以及
接触洞蚀刻停止层，设于该第一间隙壁以及该第二间隙壁之间。
13.如权利要求12所述的半导体元件，其中该第一间隙壁以及该第二间隙壁包含不同高度。
14.如权利要求12所述的半导体元件，其中该接触洞蚀刻停止层为U型。
15.如权利要求12所述的半导体元件，其中该第二间隙壁旁的接触洞蚀刻停止层上表面低于该第一间隙壁旁的接触洞蚀刻停止层上表面。
16.如权利要求11所述的半导体元件，其中该下半部上表面切齐该金属栅极上表面。
17.如权利要求11所述的半导体元件，其中该单扩散隔离结构包含：
衬垫层；以及
介电层，设于该衬垫层上，其中该衬垫层以及该介电层包含不同材料。
18.如权利要求11所述的半导体元件，另包含气孔，设于该单扩散隔离结构内。
19.如权利要求11所述的半导体元件，其中该鳍状结构沿着一第一方向延伸且该单扩散隔离结构沿着一第二方向延伸。
20.如权利要求19所述的半导体元件，其中该第一方向垂直该第二方向。
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