CN109860276A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN109860276A CN109860276A CN201910113989.XA CN201910113989A CN109860276A CN 109860276 A CN109860276 A CN 109860276A CN 201910113989 A CN201910113989 A CN 201910113989A CN 109860276 A CN109860276 A CN 109860276A
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Abstract
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor devices and forming method thereof.The semiconductor devices includes: substrate；Grid layer is located at the substrate surface；There is the source drift region and drain-drift region that the grid layer opposite sides is distributed in along orientation in the substrate, in the drain-drift region include drain region and be dielectrically separated from area between the drain region and the channel, the depth for being dielectrically separated from area is less than or equal to the depth of the drain region.The present invention optimizes element layout area, so that semiconductor devices is able to maintain original layout size while increasing the OFF state source and drain breakdown voltage of semiconductor devices.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and pursue being produced into for lower unit storage unit
This, a variety of different three-dimensional (3D) flash memories structures are come into being, such as 3D NOR (3D or non-) flash memory and 3D NAND
(3D and non-) flash memory.
Wherein, storage element is used three dimensional pattern layer using its small size, large capacity as starting point by 3D nand memory
Folded highly integrated of layer heap is design concept, produces high unit area storage density, the memory of efficient storage unit performance,
Have become the prevailing technology of emerging memory design and producing.
Higher and higher with integrated level, 3D nand memory develops to 64 layers, 128 layers from 32 layers, even higher
The number of plies.In the peripheral logic circuit of 3D nand memory, high-pressure MOS (Metal Oxide Semiconductor, metal
Oxide semiconductor) device be realize storage unit programming with erasing critical elements.OFF state source and drain breakdown voltage (Drain to
Source Breakdown Voltage, BVDSS) it is an important parameter for measuring MOS device performance.But existing MOS
The breakdown voltage of device is lower, to seriously affect the performance of three-dimensional storage.
Therefore, the OFF state source and drain breakdown voltage for how improving MOS device, improves the performance of three-dimensional storage, be at present urgently
Technical problem to be solved.
Summary of the invention
The present invention provides a kind of semiconductor devices and forming method thereof, and the source and drain for solving existing MOS device punctures
The lower problem of voltage, to improve the electrical property of three-dimensional storage.
To solve the above-mentioned problems, the present invention provides a kind of semiconductor devices, comprising:
Substrate；
Grid layer is located at the substrate surface；
There is source drift region and the leakage that the grid layer opposite sides is distributed in along orientation in the substrate
Pole drift region includes drain region and being dielectrically separated between the drain region and the channel in the drain-drift region
Area, the depth for being dielectrically separated from area are less than or equal to the depth of the drain region.
Preferably, the area that is dielectrically separated from includes:
Isolation channel extends from the surface that the substrate is formed with the grid layer to the substrate interior；
Insulating layer is filled in the isolation channel.
Preferably, further includes:
Gate dielectric layer, between the substrate and the grid layer；
The gate dielectric layer is identical as the material of the insulating layer.
Preferably, on the length direction along the channel, the width of the isolation channel is greater than the width of the drain region.
Preferably, the depth for being dielectrically separated from area is equal to the depth of the drain region.
Preferably, the depth for being dielectrically separated from area is 0.03 μm~0.1 μm.
Preferably, there are the first Doped ions, the source drift region and the drain-drift region have in the substrate
There are the second Doped ions；
First Doped ions are opposite with the conduction type of second Doped ions.
Preferably, further includes:
It is set to the shallow channel isolation area of the substrate interior, it is remote that the shallow channel isolation area is located at the drain-drift region
Side from the channel；
It is set to the draw-out area of the substrate interior, the draw-out area and the drain region are distributed in the shallow trench isolation
The opposite sides in area.
To solve the above-mentioned problems, the present invention also provides a kind of forming method of semiconductor devices, include the following steps:
A substrate is formed, the substrate surface has grid layer, has in the substrate and be distributed in along orientation
The source drift region and drain-drift region of the grid layer opposite sides；
Formation is dielectrically separated from area in the drain-drift region；
Drain region is formed in the drain-drift region, it is described be dielectrically separated from area be located at the drain region and the channel it
Between, and the depth for being dielectrically separated from area is less than or equal to the depth of the drain region.
Preferably, it is formed and is dielectrically separated from specific steps of the area in the drain-drift region and includes:
It is formed with substrate described in the surface etch of the grid layer from the substrate, the drain-drift region Yu Suoshu forms isolation
Slot；
Fill insulant forms insulating layer in the isolation channel.
Preferably, the specific steps for forming insulating layer include:
Deposition of insulative material forms the insulating layer being filled in the isolation channel and is covered in covering for the substrate surface
Cap rock.
Preferably, forming specific steps of the drain region in the drain-drift region includes:
The coating is etched, the opening of the exposure drain-drift region is formed；
Doped ions are injected from the opening, form the drain region.
Preferably, the depth of the drain region is equal to the depth of the isolation channel.
Preferably, on the length direction along the channel, the width of the isolation channel is greater than the width of the opening.
Preferably, the substrate surface further includes the gate dielectric layer between the grid layer and the substrate；
The gate dielectric layer is identical as the material of the insulating layer.
Preferably, the depth of the isolation channel is 0.03 μm~0.1 μm.
Preferably, the specific steps of one substrate of formation include:
A substrate is provided, the substrate surface has grid layer, and has the first Doped ions in the substrate；
The second Doped ions are injected separately into along the two sides of orientation in the grid layer, form the source electrode drift
Area and the drain-drift region, first Doped ions are opposite with the conduction type of second Doped ions.
Semiconductor devices provided by the invention and forming method thereof, by the insulation that a transverse direction is arranged in drain-drift region
Isolated area, and the depth for be dielectrically separated from area is less than or equal to the depth of drain region so that the semiconductor devices have with
Under several aspects advantage: first, be capable of increasing the OFF state source and drain breakdown voltage of semiconductor devices；Second, it can reduce drain electrode
Area optimizes element layout area to the distance of channel, so that semiconductor devices is able to maintain original layout size；Third,
The self-registered technology step for remaining source drift region and drain-drift region, for controlling the fluctuation of high tension apparatus current capability
Have very great help；4th, the formation process for being dielectrically separated from area can be completely compatible with shallow ditch groove separation process, maintains semiconductor
The reliability standard of device is unaffected.
Detailed description of the invention
Attached drawing 1 is the structural schematic diagram of semiconductor devices in the specific embodiment of the invention；
Attached drawing 2 be in the specific embodiment of the invention current-voltage characteristic curve of semiconductor devices in the prior art
Semiconductor devices current-voltage characteristic curve；
Attached drawing 3 is the forming method flow chart of semiconductor devices in the specific embodiment of the invention；
Attached drawing 4A-4E is that main technique section of specific embodiment of the invention during forming semiconductor devices shows
It is intended to.
Specific embodiment
The specific embodiment of semiconductor devices provided by the invention and forming method thereof is done in detail with reference to the accompanying drawing
Explanation.
As 3D nand memory technology further develops to QLC (Quad-Level Cell, four layers of storage unit),
Under the premise of not expanding chip area, how to further increase CMOS high tension apparatus OFF state source and drain breakdown voltage is current high-voltage device
One important directions of part design.
It is current main using in DEMOS (Drain-Extension MOS, drain-extended metal oxide semiconductor) and
Drift is formed in LDMOS (Lateral Double Diffused MOS, lateral double diffusion metal oxide semiconductor) high tension apparatus
The mode in area is moved to improve the OFF state source and drain breakdown voltage of device.
But in current DEMOS high tension apparatus, since carrier moving is relatively close to the lining of source area and drain region
Bottom surface, the peak value of relatively transverse electric field is also close to substrate surface, and drain region and grid layer are shorter on space length, so that
The raising of OFF state source and drain breakdown voltage is restricted (the OFF state source and drain breakdown voltage of DEMOS can only achieve 30V or so at present).
In addition, in current LDMOS high tension apparatus, due to being located at the fleet plough groove isolation structure inside drift region
The depth of (Shallow Trench Isolation, STI) is far longer than the depth of drain region, and the movement needs of carrier bypass
STI in drift region, so that the space length of carrier moving is larger.Although this kind of structure can improve to a certain extent
The OFF state source and drain breakdown voltage of LDMOS high tension apparatus, but can all have bigger loss in device area, conducting resistance,
The design of logic circuit brings difficulty in 3D nand memory for needing strict control device size.Moreover, compared to adopting
The DEMOS high-voltage device of drift region is formed with LDD (Lightly Doped Drain, lightly mixed drain area) autoregistration injection technology
For part, the ion implanting in LDMOS high tension apparatus in drift region is needed using independent light shield, if the grid length of device is smaller,
The minor shifts of contact interface position may result in the larger fluctuation of device performance between drift region and substrate well regions.
In order to avoid the increase of element layout area while improving semiconductor devices OFF state source and drain breakdown voltage, this
Specific embodiment provides a kind of semiconductor devices, and attached drawing 1 is the structure of semiconductor devices in the specific embodiment of the invention
Schematic diagram.Semiconductor devices described in present embodiment can be applied to 3D nand memory peripheral logical circuit
In high-pressure MOS component.
As shown in Figure 1, the semiconductor devices that present embodiment provides, comprising:
Substrate 10；
Grid layer 13 is located at 10 surface of substrate；
There is the source electrode drift that 13 opposite sides of grid layer is distributed in along 20 length direction of channel in the substrate 10
Area 11 and drain-drift region 12 include drain region 14 in the drain-drift region 12 and are located at the drain region 14 and the ditch
It is dielectrically separated from area 16 between road 20, the depth for being dielectrically separated from area 16 is less than or equal to the depth of the drain region 14.
Specifically, Y direction of the grid layer 13 in Fig. 1 is stacked and placed on 10 surface of substrate, the source electrode drift
It moves area 11 and X-direction of the drain-drift region 12 in Fig. 1 is distributed in the opposite sides of the grid layer 13.This is specific real
The mode of applying is therefore can also to form the source drift region using self-registered technology based on DEMOS high-voltage device structure
11 with the drain-drift region 12, thus facilitate control high tension apparatus current capability fluctuation.Wherein, the grid layer 13
Material can be but not limited to polysilicon.
Area 16 is dielectrically separated from described in present embodiment along the y axis (i.e. perpendicular to the direction of the substrate 10)
Depth is less than or equal to the depth of the drain region 14, described to be dielectrically separated from the width of area 16 along the x axis greater than it along Y-axis
The depth in direction, i.e., the described area 16 that is dielectrically separated from laterally (along the x axis) extend, and are on the one hand capable of increasing the semiconductor devices
OFF state source and drain breakdown voltage；On the other hand, area required for semiconductor devices does not increase in holding circuit layout design
While, reduce the path length that carrier moves to the channel 20 from the drain region 14, so that semiconductor devices is connected
The increase of resistance also controls within the acceptable range, to the design rule of 3D nand memory periphery CMOS logic device and
Circuit layout floorplan does not all need special change, the influence very little to original circuit structure design.
Attached drawing 2 be in the specific embodiment of the invention current-voltage characteristic curve of semiconductor devices in the prior art
Semiconductor devices current-voltage characteristic curve, the first curve 21 indicates the electric current-of DEMOS device in the prior art in Fig. 2
Voltage response, the second curve 22 indicate the current-voltage characteristic curve for the semiconductor devices that present embodiment provides.
Table 1 is existing DEMOS device electrical performance and the semiconductor device electrical property energy contrast table that present embodiment provides.In table 1
In, Vtl indicates that linear area's threshold voltage of semiconductor devices, Vts indicate the saturation region threshold voltage of semiconductor devices, Ids table
Show that source-drain current, Ioff indicate off-state current.By table 1 and Fig. 2 it is found that the semiconductor devices that present embodiment provides
2V can be improved in OFF state source and drain breakdown voltage, and Ids only reduces 13%.
The semiconductor device electrical property energy contrast table of the existing DEMOS device of table 1 and present embodiment
Preferably, the area 16 that is dielectrically separated from includes:
Isolation channel is formed with the surface of the grid layer 13 to 10 internal stretch of substrate from the substrate 10；
Insulating layer is filled in the isolation channel.
Specifically, it is described be dielectrically separated from area 16 be by the substrate 10 is formed with the surface of the grid layer 13 into
Row etching, forms isolation channel, and fills what insulating layer was formed in the isolation channel.
Preferably, the semiconductor devices further include:
Gate dielectric layer 17, between the substrate 10 and the grid layer 13；
The gate dielectric layer 17 is identical as the material of the insulating layer.
Preferably, on the length direction along the channel 20, the width of the isolation channel is greater than the drain region 14
Width.
Specifically, it is described be dielectrically separated from area 16 along the x axis on width be greater than the drain region 14 along the x axis on
Width, so that the motion path of carrier is further extended, so that the OFF state source and drain breakdown voltage of the semiconductor devices
It is further enhanced.Those skilled in the art, which can be set according to actual needs, described is dielectrically separated from area 16 and the drain region
Relative width ratio between 14, present embodiment are not construed as limiting this.
Preferably, the depth for being dielectrically separated from area 16 is equal to the depth of the drain region 14.It is furthermore preferred that the insulation
The depth of isolated area 16 is 0.03 μm~0.1 μm.In present embodiment, area 16 is dielectrically separated from along the y axis for described
Depth is set as 0.05 μm.
Preferably, there is the first Doped ions, the source drift region 11 and the drain-drift region in the substrate 10
12 all have the second Doped ions；
First Doped ions are opposite with the conduction type of second Doped ions.
Preferably, the semiconductor devices further include:
It is set to the shallow channel isolation area 18 inside the substrate 10, the shallow channel isolation area 18 is located at drain electrode drift
Move side of the area 12 far from the channel 20；
It is set to the draw-out area 19 inside the substrate 10, the draw-out area 19 is distributed in described shallow with the drain region 14
The opposite sides of channel separating zone 18.
The draw-out area 19 is used to draw the electric signal of the substrate 10.Area is dielectrically separated from described in present embodiment
16 formation process can be compatible with the formation process of shallow channel isolation area 18 in semiconductor devices, to avoid to semiconductor device
The reliability standard of part impacts.
For example, the semiconductor devices is NMOS high tension apparatus, doped with P-type ion in the substrate 10, is formed
P-type trap；The source drift region 11 is the region for gently mixing N-type ion with the drain-drift region 12；The drain region 14
It is the region of heavily doped N-type ion with source area 15；The draw-out area 19 is the region of heavily doped P-type ion.
Moreover, present embodiment additionally provides a kind of forming method of semiconductor devices, and attached drawing 3 is the present invention
The forming method flow chart of semiconductor devices in specific embodiment, attached drawing 4A-4E are that the specific embodiment of the invention is being formed
The structure of main technique schematic cross-section during semiconductor devices, the semiconductor devices that present embodiment is formed can
With as shown in Figure 1.Shown in A- Fig. 4 E as shown in Figure 1, Figure 3 and Figure 4, the formation side for the semiconductor devices that present embodiment provides
Method includes the following steps:
Step S31, forms a substrate 10, and 10 surface of substrate has grid layer 13, has in the substrate 10 along ditch
20 length direction of road is distributed in the source drift region 11 and drain-drift region 12 of 13 opposite sides of grid layer, such as Fig. 4 A institute
Show.
Preferably, the specific steps of one substrate 10 of formation include:
One substrate 10 is provided, 10 surface of substrate has grid layer 13, and have in the substrate 10 first adulterate from
Son；
The second Doped ions are injected separately into along the two sides of 20 length direction of channel in the grid layer 13, form the source electrode
Drift region 11 and the drain-drift region 12, first Doped ions are opposite with the conduction type of second Doped ions.
Specifically, after providing a substrate 10, by carrying out the injection of P-type ion to the substrate 10, in substrate 10
Middle formation P-type trap；Then, 10 surface depositing polysilicon material of Yu Suoshu substrate forms the grid layer 13；Then, using certainly
Alignment Process injects N-type ion in the substrates 10 of 13 two sides of Xiang Suoshu grid layer, forms the source area 11 and described
Drain region 12.
Step S32, formation are dielectrically separated from area 16 in the drain-drift region 12, as shown in Figure 4 C.
Preferably, it is formed and is dielectrically separated from specific steps of the area 16 in the drain-drift region 12 and includes:
Substrate 10 described in the surface etch of the grid layer 13, the drain-drift region Yu Suoshu 12 are formed with from the substrate 10
Isolation channel 30 is formed, as shown in Figure 4 B；
Fill insulant forms insulating layer 31, as shown in Figure 4 C in the isolation channel 30.
Preferably, the specific steps of formation insulating layer 31 include:
Deposition of insulative material forms the insulating layer 31 being filled in the isolation channel 30 and is covered in 10 table of substrate
The coating 32 in face.
Specifically, the material of the substrate 10 can be but be not limited to silicon.After forming the substrate 10, using silicon
Etching technics is formed with the surface etch of the grid layer 13 from the substrate 10, forms the isolation channel 30.In etching process
In, control etching depth is 0.03 μm~0.1 μm, it is furthermore preferred that control etching depth is 0.05 μm.Later, using chemical gas
Phase depositing operation, physical gas-phase deposition or the atom layer deposition process deposition insulating materials such as silica, described in formation
Insulating layer 31 and the coating 32.Wherein, the insulating layer 31 fills the full isolation channel 30, i.e., the thickness of the described insulating layer 31
Degree is more than or equal to the depth of the isolation channel 30.
Step S33 forms drain region 14 in the drain-drift region 12, and the area 16 that is dielectrically separated from is located at the drain region
Between 14 and the channel 20, and the depth for being dielectrically separated from area 16 is less than or equal to the depth of the drain region 14, such as schemes
Shown in 4E.
Preferably, forming specific steps of the drain region 14 in the drain-drift region 12 includes:
The coating 32 is etched, the opening for forming the exposure drain-drift region 12 is as shown in Figure 4 D；
Doped ions are injected from the opening, form the drain region 14.
Specifically, the coating 31 at least covers corresponding with the source drift region 11 and the drain-drift region 12
10 surface of the substrate.By etching the coating 31, it is formed simultaneously the exposure original cost drift region 11 and the drain electrode
Drift region 12；Then, using ion implantation technology, N-type ion is injected to the source drift region 11 and the drain drift
Area is formed simultaneously heavily doped source electrode 15 and drain electrode 14.
Preferably, the depth of the drain region 14 is equal to the depth of the isolation channel 30.
Preferably, on the length direction along the channel 20, the width of the isolation channel 30 is greater than the width of the opening
Degree.
Present embodiment controls the drain region 14 and the relative depth for being dielectrically separated from area 16 and opposite simultaneously
Width, thus further while improving OFF state source and drain breakdown voltage, optimization circuit layout design.
Preferably, 10 surface of substrate further includes the gate dielectric layer between the grid layer 13 and the substrate 10
17；
The gate dielectric layer 17 is identical as the material of the insulating layer 31.
The semiconductor devices and forming method thereof that present embodiment provides, by the way that a cross is arranged in drain-drift region
To the depth for being dielectrically separated from area, and to be dielectrically separated from area be less than or equal to the depth of drain region so that the semiconductor device
Advantage of the part with the following aspects: first, it is capable of increasing the OFF state source and drain breakdown voltage of semiconductor devices；Second, it can be with
Reduce drain region to the distance of channel, element layout area is optimized, so that semiconductor devices is able to maintain original domain ruler
It is very little；Third remains the self-registered technology step of source drift region and drain-drift region, for controlling high tension apparatus current capability
Fluctuation have very great help；4th, the formation process for being dielectrically separated from area can be completely compatible with shallow ditch groove separation process, keeps
The reliability standard of semiconductor devices is unaffected.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (17)
1. a kind of semiconductor devices characterized by comprising
Substrate；
Grid layer is located at the substrate surface；
There is source drift region and the drain electrode drift that the grid layer opposite sides is distributed in along orientation in the substrate
Area is moved, includes drain region in the drain-drift region and is dielectrically separated from area between the drain region and the channel,
The depth for being dielectrically separated from area is less than or equal to the depth of the drain region.
2. semiconductor devices according to claim 1, which is characterized in that the area that is dielectrically separated from includes: isolation channel, from institute
It states substrate and is formed with the surface of the grid layer and extend to the substrate interior；
Insulating layer is filled in the isolation channel.
3. semiconductor devices according to claim 2, which is characterized in that further include:
Gate dielectric layer, between the substrate and the grid layer；
The gate dielectric layer is identical as the material of the insulating layer.
4. semiconductor devices according to claim 2, which is characterized in that described on the length direction along the channel
The width of isolation channel is greater than the width of the drain region.
5. semiconductor devices according to claim 1, which is characterized in that the depth for being dielectrically separated from area is equal to the leakage
The depth of polar region.
6. semiconductor devices according to claim 1, which is characterized in that the depth for being dielectrically separated from area be 0.03 μm~
0.1μm。
7. semiconductor devices according to claim 1, which is characterized in that have the first Doped ions, institute in the substrate
It states source drift region and the drain-drift region and all has the second Doped ions；
First Doped ions are opposite with the conduction type of second Doped ions.
8. semiconductor devices according to claim 1, which is characterized in that further include:
It is set to the shallow channel isolation area of the substrate interior, the shallow channel isolation area is located at the drain-drift region far from institute
State the side of channel；
It is set to the draw-out area of the substrate interior, the draw-out area and the drain region are distributed in the shallow channel isolation area
Opposite sides.
9. a kind of forming method of semiconductor devices, which comprises the steps of:
A substrate is formed, the substrate surface has grid layer, and the substrate is interior described with being distributed in along orientation
The source drift region and drain-drift region of grid layer opposite sides；
Formation is dielectrically separated from area in the drain-drift region；
Formed drain region in the drain-drift region, the area that is dielectrically separated between the drain region and the channel, and
The depth for being dielectrically separated from area is less than or equal to the depth of the drain region.
10. the forming method of semiconductor devices according to claim 9, which is characterized in that formation is dielectrically separated from Qu Yusuo
The specific steps for stating drain-drift region include:
It is formed with substrate described in the surface etch of the grid layer from the substrate, the drain-drift region Yu Suoshu forms isolation channel；
Fill insulant forms insulating layer in the isolation channel.
11. the forming method of semiconductor devices according to claim 10, which is characterized in that form the specific step of insulating layer
Suddenly include:
Deposition of insulative material forms the insulating layer being filled in the isolation channel and the covering for being covered in the substrate surface
Layer.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that form drain region in the leakage
The specific steps of pole drift region include:
The coating is etched, the opening of the exposure drain-drift region is formed；
Doped ions are injected from the opening, form the drain region.
13. the forming method of semiconductor devices according to claim 12, which is characterized in that the depth etc. of the drain region
In the depth of the isolation channel.
14. the forming method of semiconductor devices according to claim 12, which is characterized in that in the length along the channel
On direction, the width of the isolation channel is greater than the width of the opening.
15. the forming method of semiconductor devices according to claim 10, which is characterized in that the substrate surface further includes
Gate dielectric layer between the grid layer and the substrate；
The gate dielectric layer is identical as the material of the insulating layer.
16. the forming method of semiconductor devices according to claim 10, which is characterized in that the depth of the isolation channel is
0.03 μm~0.1 μm.
17. the forming method of semiconductor devices according to claim 10, which is characterized in that form the specific step of a substrate
Suddenly include:
A substrate is provided, the substrate surface has grid layer, and has the first Doped ions in the substrate；
Be injected separately into the second Doped ions along the two sides of orientation in the grid layer, formed the source drift region and
The drain-drift region, first Doped ions are opposite with the conduction type of second Doped ions.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110610941A (en) * | 2019-09-23 | 2019-12-24 | 长江存储科技有限责任公司 | Structure and method for improving peripheral circuit punch-through voltage in three-dimensional memory |
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