CN109859788A - The test method for bit error rate of resistive memory - Google Patents
The test method for bit error rate of resistive memory Download PDFInfo
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- CN109859788A CN109859788A CN201910134609.0A CN201910134609A CN109859788A CN 109859788 A CN109859788 A CN 109859788A CN 201910134609 A CN201910134609 A CN 201910134609A CN 109859788 A CN109859788 A CN 109859788A
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Abstract
The invention discloses a kind of test method for bit error rate of resistive memory.The commercial applications of memory need to guarantee the extremely low bit error rate, this test needs to repeat a large amount of erasable process and analyzed, to need a large amount of time, therefore accelerate to this process meaningful.The present invention is particular value using the length that arbitrary waveform generator adjusts reading waveform, thus that can generate the specific waveforms only comprising reading information after dot product in oscillograph with selection signal.This specific waveforms allows to filter off the waveform read other than information after adjusting oscilloscope sampling rate, the redundancy of information is dropped to theoretical minimum, to increase the flux of error rate test.
Description
Technical field
Present invention pertains generally to memory test fields, more particularly to the reliability test of resistive memory.
Background technique
Resistive memory based on resistance value is a kind of common non-volatility memorizer, is one kind energy under the conditions of passive
The technology of non-volatile recording data.For resistive memory basic operation there are two types of, it is erasable and read.Due to the heating power of device
A degree of bit error rate can all be caused with randomness brought by mechanism itself, erasable operation and read operation by learning.For wiping
Process is write, error code shows as write-in failure, i.e., the state of storage unit does not change in erasable front and back.For reading process,
Error code is shown as being written successfully, i.e. the state of storage unit is changed before and after reading.Commercialized resistive is stored
Device, due to using error code correcting code (Error Correction Code), the bit error rate lower than certain threshold value is can to receive
's.This generally acknowledged bit error rate threshold is 10 in the industry-6, i.e., once error code in every 1,000,000 operations.The test of the bit error rate is
Any commercialized critical reliability data of memory, but this requirement means great data volume and corresponding extremely long test
Time.The time of this key test is substantially reduced therefore is very significant.Traditional error rate analyzer uses fixation
Read access time length, and the timing in this time span and actual circuit is consistent, usually one is deposited much smaller than described
The numerical value of write sequence element length.Therefore, oscillograph must be run with higher sample rate, to capture the reading stage device
On electric current, to obtain the state of device.This high sampling rate increases the higher data volume of script further greatly
Add.
Summary of the invention
In view of the above-mentioned deficiencies in the prior art, it is an object of the present invention to provide a kind of error rate test side of resistive memory
Method.
The purpose of the present invention is what is be achieved through the following technical solutions: a kind of test method for bit error rate of resistive memory,
The described method includes:
In a test system；
The arbitrary waveform generator output of the test macro is two signals, respectively deposits write signal and chooses signal；
The oscillograph input of the test macro is two signals, and the respectively described write signal of depositing is by resistive memory
Excitation current and the selection signal；
The data in the mathematics channel of the oscillograph are the excitation current and the dot product result for choosing signal；
In a computer, dot product is received as a result, and carrying out error rate analyzer and providing the bit error rate.
Further, the test macro is that have based on probe station, wafer and passive probe, and without using independent
Source amplifier or passive amplifier.
Further, it is described deposit write signal deposit write sequence unit be divided into initial phase, write phase, loitering phase with
And read the stage；
The object of the bit error rate is the said write stage, and the voltage magnitude in said write stage can be erasable voltage
Amplitude, or voltage magnitude is read, it is also possible to arbitrary waveform.
Further, the time span in the reading stage deposits the half of write sequence length described in.
Further, the selection sequence units for choosing signal are divided into high level stage and low level stage.
Further, the time location in the high level stage is the subset of the time location in the reading stage.
Further, the calculating operation for obtaining the dot product result is high speed mathematical operation list inside the oscillograph
It is completed in first.
Further, the sample rate of the oscillograph is not more than 50 times of following numerical value, i.e., the described reading for depositing write signal
Take twice of the inverse in stage；And if this sampling is located at the time location in the reading stage, sampling cannot next time
Into the time location in next reading stage for depositing write sequence unit.
Further, the error rate analyzer in the computer uses parallel computation framework.
Further, the error rate analyzer uses classifier algorithm.
The beneficial effects of the present invention are: the method for the present invention can be realized high-throughput error rate test, to greatly contract
It is short carry out error rate test needed for the time, promote the speed of research and development of products.The method of the present invention, which effectively shields, reads rank
Data except section, thus obtain data volume to be processed needed for the error code information of single operation be reduced to it is theoretical minimum, from
And it significantly reduces the preservation of data and handles time and cost.Firstly, present invention uses the selection signal and described depositing
The dot product of write signal simplifies originally complicated waveform in order to which the stage of reading is constant, remaining time location be approximately zero it is similar
The signal of square wave.Since this processing passes through high-speed bus and computing unit completion inside oscillograph, time-consuming is needed not move through
The transmission of equipment room peripheral data, thus more tractable signal is obtained under the premise of not increasing the testing time, thus under being
The processing of one step lays the foundation.
Detailed description of the invention
Fig. 1 is the test method for bit error rate realization principle figure of resistive memory.
Specific embodiment
In the following detailed description, with reference to the attached drawing for forming a part of the invention, wherein passing through graphic side
Formula shows implementable a specific embodiment of the invention.It should be understood that without departing from the scope of the invention, it can be utilized
Its embodiment and the change that structure or logic can be carried out.For example, the feature that an embodiment is shown or described can
For or in conjunction with other embodiment to generate another embodiment.It include these modifications and variations its object is to the present invention.
Use specific language (it is not necessarily to be construed as limitation the scope of the appended claims) description embodiment.Attached drawing do not press than
Example draws and only for purposes of discussion.
We use following symbol table oscillography shape:
1. (time 1, amplitude 1) is defined as maintaining amplitude 1 (unit: V) under the length of time 1 (unit: ns)；
2. it is series connection of two sections of waveforms in timing that [first, second], which schedules,.
Test macro includes arbitrary waveform generator, oscillograph and computer.During the test, resistive to be tested is deposited
Reservoir is spin transfer torque-magnetic random memory (STT-MRAM).
Assuming that the bit error rate for needing the square wave of the 50ns of 0.5V to be written, the specific steps are as follows:
The sample rate that oscillograph is arranged is 5MS/s.Depositing for arbitrary waveform generator is write into Waveform Input device, and by oscillography
The channel 1 of device is connected on device circuit.By the channel 2 of the selection Waveform Input oscillograph of arbitrary waveform generator.In oscillograph
Interior, setting mathematical operation result is the dot product in channel 1 and channel 2, is denoted as mathematics 1.Mathematics 1 is saved to oscillograph.Probe is set
Platform and probe are to complete the acupuncture treatment of microwave probe and magnetic random memory wafer.
After the connection for completing test loop, setting, which is deposited, to be write waveform and is
[(400,-0.7),(100,0),(50,0.5),(100,0),(850,0.2)],
Waveform is chosen in setting
[(700,0),(750,0.5),(50,0)]。
Next step accesses the hard disk of oscillograph using the cable based on gigabit LAN, to read this data.?
On computer, the processing mode of the bit error rate can there are many kinds of, provide two kinds of examples here.First way, preparatory measuring appliance
Resistance-voltage relationship of part, determines the line of demarcation of the resistance under different conditions, then compares the high level of square wave in test data
With scheduled line of demarcation.The second way randomly selects a part of data, determines different conditions resistance using classifier algorithm
Then boundary judges the state of device using trained classifier.The calculating of this step can use parallel computation frame
Structure accelerates.When data save simultaneously, low accuracy floating-point number or integer can be used to reduce data volume.
We can measure the bit error rate with fixed voltage by the above process, can also fix the expected bit error rate and then search for phase
Corresponding voltage.Previous process only needs the voltage by constantly changing write-in can be realized.For latter procedure, newton is used
Method or dichotomy complete this search, referring on the left of Fig. 1.The specific implementation of Newton method is described first.It is arranged one smaller
Write-in voltage, such as 0.1V, a then biggish write-in voltage, such as 0.2V are set.Linear extrapolation is done by Newton method or interpolation obtains
To new write-in voltage, recycle until the difference of the actual measurement bit error rate and the expected bit error rate is less than given error.Next description
The specific implementation of dichotomy.One lesser write-in voltage, such as 0.1V are set, if the actual measurement bit error rate is greater than the expected bit error rate,
It then sets new voltage to twice of primary voltage, until the actual measurement bit error rate is less than the expected bit error rate.Last be used as twice is taken to search
Rope section, carry out binary chop, due to the step for be basic algorithm, do not do specific explanations here.
Claims (10)
1. a kind of test method for bit error rate of resistive memory, which is characterized in that the described method includes:
In a test system；
The arbitrary waveform generator output of the test macro is two signals, respectively deposits write signal and chooses signal；
The oscillograph input of the test macro is two signals, the respectively described excitation deposited write signal and pass through resistive memory
Electric current and the selection signal；
The data in the mathematics channel of the oscillograph are the excitation current and the dot product result for choosing signal；
In a computer, dot product is received as a result, and carrying out error rate analyzer and providing the bit error rate.
2. the method according to claim 1, wherein the test macro is based on probe station, wafer and passive
Probe, and do not use independent activated amplifier or passive amplifier.
3. the method according to claim 1, wherein the write sequence unit of depositing for depositing write signal is divided into initialization
Stage, write phase, loitering phase and reading stage；
The object of the bit error rate is the said write stage, and the voltage magnitude in said write stage can be erasable voltage amplitude
Value, or voltage magnitude is read, it is also possible to arbitrary waveform.
4. according to the method described in claim 3, it is characterized in that, the time span in the reading stage writes sequence close to described deposit
The half of column length.
5. the method according to claim 1, wherein the selection sequence units for choosing signal are divided into high level
Stage and low level stage.
6. according to the method described in claim 5, it is characterized in that, the time location in the high level stage is the reading rank
The subset of the time location of section.
7. the method according to claim 1, wherein the calculating operation for obtaining the dot product result is shown described
It is completed in high speed mathematical arithmetic element inside wave device.
8. the method according to claim 1, wherein no more than 50 times following numbers of the sample rate of the oscillograph
Value, i.e., twice of the inverse in the described reading stage for depositing write signal；And if this sampling is located at the reading stage
Time location then samples not the time location that can enter next reading stage for depositing write sequence unit next time.
9. the method according to claim 1, wherein the error rate analyzer in the computer uses parallel computation
Framework.
10. the method according to claim 1, wherein the error rate analyzer uses classifier algorithm.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113344020A (en) * | 2020-03-02 | 2021-09-03 | 美光科技公司 | Classification of error rates of data retrieved from memory cells |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11257546B2 (en) | 2020-05-07 | 2022-02-22 | Micron Technology, Inc. | Reading of soft bits and hard bits from memory cells |
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