CN109857693A - A kind of adaptive serial clock sequence detecting apparatus and method - Google Patents
A kind of adaptive serial clock sequence detecting apparatus and method Download PDFInfo
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- CN109857693A CN109857693A CN201910150540.0A CN201910150540A CN109857693A CN 109857693 A CN109857693 A CN 109857693A CN 201910150540 A CN201910150540 A CN 201910150540A CN 109857693 A CN109857693 A CN 109857693A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The present invention provides a kind of adaptive serial clock sequence detecting apparatus and detection methods, device includes clock sequence, clock sequence connects COM character machining module, COM detection module connects PCIe clock sequence detecting unit, PCIe clock sequence detecting unit connects RapidIO clock sequence detection unit, RapidIO clock sequence detection unit output test result.The present invention can be realized two kinds of agreement clock compensation sequences of serial sensing RapidIO and PCIe, detection module string is voluntarily selected according to different clock compensation sequences and simultaneously closes off non-present protocol detection module, the input of non-present protocol detection module is blocked, influence caused by the small probability event for occurring another agreement clock compensation sequence in data flow is avoided；The present invention provides the instruction of corresponding agreement while detecting clock compensation sequence, and interfacing module is facilitated to modify to adaptive hardware direction.
Description
Technical field
The invention belongs to clock sequence detection technique fields, fill more particularly, to a kind of adaptive serial clock Sequence Detection
It sets and method.
Background technique
RapidIO technology is mainly directed towards the interconnected communication of high performance embedded system, higher than the efficiency of transmission of Ethernet.
And due to having more perfect consideration in RapidIO routing, exchange, fault-tolerant error correction, ease of use, may be implemented based on hardware
High-performance reliable data transmission.
PCI Express (PCIe) is that one kind can be applied to mobile device, desktop computer, work station, server, insertion
Formula calculates and the bus of all periphery I/O equipment interconnections such as communications platform.
The two can be used serial link and carry out high-speed transfer.Two kinds of protocol physical layers have high similarity, can take out
As for by the PMA that serially unstrings (physical media attachment physical medium attachment layer) layer and PCS (physical
Coding sub-layer Physical Coding Sublayer) layer constitute model.As shown in Figure 1.
To eliminate transmitting terminal and receiving end clock skew in receiving side PCS, two agreements are designed with elastic caching mould
Block.Such as Fig. 2.Elastic caching design can be divided into: clock compensation Sequence Detection, pointer control, synchronization unit, threshold test, storage
Device.Such as Fig. 3.Elastic caching adds or deletes certain particular sequence by pointer control to achieve the purpose that clock compensation.
RapidIO agreement clock compensation sequence is composed according to certain code word in 8b/10b coding schedule.Code word combination sequence is | K |
|R||R||R|.PCIe protocol clock compensation sequence is known as SKIP sequence collection, by a COM character and three SKP character groups below
At.No matter RapidIO | K | | R | | R | | R | combination or PCIe SKIP sequence collection, be all according to 8b/10b coded combination and
At.Such as Fig. 4.
In the design of present clock compensation Sequence Detection, realizing, it is all made of the matching to single-protocol, string does not consider hardware
To the compatibility implementations of agreement.Therefore, when protocol conversion occurs, then clock compensation Sequence Detection is needed to redesign.Hardware
Structure can not be reused, and design time and manpower are wasted.
Summary of the invention
In view of this, the present invention is directed to propose a kind of adaptive serial clock sequence detecting apparatus, to solve above-mentioned background
The problem of being mentioned in technology.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
A kind of adaptive serial clock sequence detecting apparatus, including clock sequence input terminal, the clock sequence input terminal
The input terminal of COM character machining module is connected, the output end connection PCIe clock sequence detecting unit of the COM detection module
Input terminal, the input terminal of the output end connection RapidIO clock sequence detection unit of the PCIe clock sequence detecting unit, institute
State the output end output test result of RapidIO clock sequence detection unit；
The PCIe clock sequence detecting unit includes 3 concatenated SKP character machining modules, the SKP character machining
The output end of module is connected to the input terminal of the first AND gate circuit together with the output end of the COM character machining module, described
The output end output PCIe clock of first AND gate circuit compensates sequence indication signal, and the output end of first AND gate circuit also connects
The first logic circuit is connect, PCIe protocol indication signal is generated by the first logic circuit；First logic circuit also passes through
Three gates connect the RapidIO clock sequence detection unit；
The RapidIO clock sequence detection unit includes 3 concatenated R character machining modules, the R character machining mould
The output end of block is connected to the input terminal of the second AND gate circuit together with the output end of the COM character machining module, and described
The output end of two AND gate circuits exports RapidIO clock compensation sequence indication signal, and the output end of second AND gate circuit is also
The second logic circuit is connected, RapidIO agreement indication signal is generated by the second logic circuit；Second logic circuit is also logical
Cross the 4th gate connection PCIe clock sequence detecting unit.
Further, first logic circuit includes the first gate and the first d type flip flop, first gate
Output end connects the input terminal of the first d type flip flop, and the control signal of first gate connects the defeated of the first AND gate circuit
On the one hand outlet, the output end of first d type flip flop connect the input terminal of the first gate, on the other hand connect third gating
The control signal of device.
Further, second logic circuit includes the second gate and the second d type flip flop, second gate
Output end connects the input terminal of the second d type flip flop, and the control signal of second gate connects the defeated of the second AND gate circuit
On the one hand outlet, the output end of second d type flip flop connect the input terminal of the second gate, on the other hand the 4th gating of connection
The control signal of device.
Further, first gate, the second gate, third gate, the 4th gate are alternative choosing
Logical device.
Compared with the existing technology, a kind of adaptive serial clock sequence detecting apparatus of the present invention has following excellent
Gesture:
(1) present invention can be realized two kinds of agreement clock compensation sequences of serial sensing RapidIO and PCIe, according to different
Clock compensation sequence voluntarily selects detection module string and simultaneously closes off non-present protocol detection module, blocks non-present protocol detection
Module input, avoids influence caused by the small probability event for occurring another agreement clock compensation sequence in data flow；
(2) present invention provides the instruction of corresponding agreement, facilitates interfacing while detecting clock compensation sequence
Module is modified to adaptive hardware direction；
(3) present invention can be compatible with detection RapidIO, PCIe protocol clock compensation sequence, and it is reusable to improve hardware configuration
Property.
Another object of the present invention is to propose a kind of adaptive serial clock sequence detecting method, to realize RapidIO
With the serial clock Sequence Detection of two kinds of agreements of PCIe.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
A kind of adaptive serial clock sequence detecting method, specifically comprises the following steps
(1) data flow flows into PCIe clock sequence detecting unit and RapidIO clock sequence detection unit is detected；
(2) if PCIe clock sequence detecting unit detects continuous SKP character, pass through third gate for RapidIO
The enable signal of clock sequence detection unit is set in vain, exports the data from PCIe clock sequence detecting unit；
(3) if RapidIO clock sequence detection unit detects continuous K character, when by the 4th gate by PCIe
The enable signal of clock sequence detecting unit is set in vain, exports the data from RapidIO clock sequence detection unit.
A kind of adaptive serial clock sequence detecting method of the present invention and a kind of above-mentioned adaptive serial clock sequence
The beneficial effect of column detection device is identical, and details are not described herein.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, string does not constitute an undue limitation on the present invention.In the accompanying drawings:
Fig. 1 is protocol physical layers abstract model schematic diagram described in background of invention；
Fig. 2 provides schematic diagram for asynchronous data communication described in background of invention；
Fig. 3 is elastic caching design drawing described in background of invention；
Fig. 4 is RapidIO described in background of invention and PCIe clock compensates sequence chart；
Fig. 5 is adaptive serial clock compensation detecting device figure described in the embodiment of the present invention.
Description of symbols:
1-PCIe clock sequence detection unit；2-RapidIO clock sequence detection unit；The first AND gate circuit of 3-；4-
One logic circuit；The first gate of 41-；The first d type flip flop of 42-；5- third gate；The second AND gate circuit of 6-；7- second is patrolled
Collect circuit；The second gate of 71-；The second d type flip flop of 72-；The 4th gate of 8-.
Specific embodiment
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", "upper", "lower",
The orientation or positional relationship of the instructions such as "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of description of the present invention and simplification of the description, rather than instruction or dark
Show that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as pair
Limitation of the invention.In addition, term " first ", " second " etc. are used for description purposes only, it is not understood to indicate or imply phase
To importance or implicitly indicate the quantity of indicated technical characteristic.The feature for defining " first ", " second " etc. as a result, can
To explicitly or implicitly include one or more of the features.In the description of the present invention, unless otherwise indicated, " multiple "
It is meant that two or more.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood by concrete condition
Concrete meaning in the present invention.
Go here and there below with reference to the accompanying drawings in conjunction with the embodiments come the present invention will be described in detail.
The present invention provides device and the side of the serial clock Sequence Detection of a kind of adaptive RapidIO and two kinds of agreements of PCIe
Method.As shown in Figure 4, character machining unit module predominantly detects K28.0, tri- kinds of patterns of K28.5, K29.7, i.e., detection K character or
Person's COM character, SKP character, R character, string, which provides to detect, successfully to be indicated.PCIe clock sequence detecting unit and RapidIO in Fig. 5
Two detection modules of clock sequence detection unit are realized according to above-mentioned principle.
As shown in figure 5, a kind of adaptive serial clock sequence detecting apparatus, including clock sequence input terminal, the clock
Sequence inputting end connects the input terminal of COM character machining module, and the output end of the COM detection module connects PCIe clock sequence
The output end connection RapidIO clock sequence detection of the input terminal of detection unit 1, the PCIe clock sequence detecting unit 1 is single
The input terminal of member 2, the output end output test result of the RapidIO clock sequence detection unit 2；
The PCIe clock sequence detecting unit 1 includes 3 concatenated SKP character machining modules, the SKP character machining
The output end of module is connected to the input terminal of the first AND gate circuit 3 together with the output end of the COM character machining module, described
The output end output PCIe clock of first AND gate circuit 3 compensates sequence indication signal, and the output end of first AND gate circuit 3 is also
The first logic circuit 4 is connected, PCIe protocol indication signal is generated by the first logic circuit 4；First logic circuit 4 is also logical
It crosses third gate 5 and connects the RapidIO clock sequence detection unit 2；
The RapidIO clock sequence detection unit 2 includes 3 concatenated R character machining modules, the R character machining
The output end of module is connected to the input terminal of the second AND gate circuit 6 together with the output end of the COM character machining module, described
The output end of second AND gate circuit 6 exports RapidIO clock compensation sequence indication signal, the output of second AND gate circuit 6
End is also connected with the second logic circuit 7, generates RapidIO agreement indication signal by the second logic circuit 7；The second logic electricity
Road 7 also connects PCIe clock sequence detecting unit 1 by the 4th gate 8.
First logic circuit 4 include the first gate 41 and the first d type flip flop 42, first gate 41 it is defeated
Outlet connects the input terminal of the first d type flip flop 42, and the control signal of first gate 41 connects the first AND gate circuit 3
On the one hand output end, the output end of first d type flip flop 42 connect the input terminal of the first gate 41, on the other hand connection the
The control signal of three gates 5.
Second logic circuit 7 include the second gate 71 and the second d type flip flop 72, second gate 71 it is defeated
Outlet connects the input terminal of the second d type flip flop 72, and the control signal of second gate 71 connects the second AND gate circuit 6
On the one hand output end, 72 output end of the second d type flip flop connect the input terminal of the second gate 71, on the other hand connection the 4th
The control signal of gate 8.
First gate 41, the second gate 71, third gate 5, the 4th gate 8 are alternative gating
Device.
The course of work of the invention is as follows: data enter clock sequence compatibility detection module, and serial mode flows into COM word
Detection module is accorded with to detect K28.5 pattern, SKP detection detection K28.0 pattern detects K29.7 pattern in R detection.Each
Pattern provides marking signal after detecting successfully.
As shown in figure 4, the arrangement of PCIe clock sequence is continuous three SKP characters after COM character, RapidIO clock sequence
Arrangement is continuous three R characters after COM character.Before any protocol status is not detected, data flow enters PCIe clock in Fig. 5
Sequence detecting unit 1 can generate PCIe clock compensation sequence indication signal if detecting continuous SKP character, while pass through the
One logic circuit, 4 structure can then generate PCIe protocol indication signal.PCIe protocol indication signal can then be incited somebody to action by third gate 5
The enable signal of RapidIO clock sequence detection unit 2 is set in vain, realizes that RapidIO clock sequence detection unit 2 enters not
Detection pattern, it is ensured that the instruction of RapidIO sequence and the instruction of RapidIO agreement are in invalid state.
Same principle, before any protocol status is not detected, data flow enters RapidIO clock sequence in Fig. 5 and examines
Surveying unit 2 if detecting continuous K character can generate RapidIO clock compensation sequence indication signal, together, when pass through the
Two logic circuits, 7 structure then generates RapidIO agreement indication signal.RapidIO agreement indication signal then passes through the 4th gate 8
The enable signal of PCIe clock sequence detecting unit 1 is set in vain, realizes that PCIe clock sequence detecting unit 1 enters non-detection
Mode, it is ensured that its PCIe sequence exported instruction and PCIe protocol instruction are in invalid state.
The present invention realizes two kinds of agreement clock compensation sequences of serial sensing RapidIO and PCIe, is mended according to different clocks
It repays sequence and voluntarily selects detection module and at the same time closing non-present protocol detection module, avoid occurring another agreement in data flow
It is influenced caused by the small probability event of clock compensation sequence.While detecting clock compensation sequence, corresponding agreement is provided
Instruction facilitates interfacing module to modify to adaptive hardware direction.The present invention can be compatible with detection RapidIO, PCIe association
Clock compensation sequence is discussed, hardware configuration reusability is improved.
The foregoing is merely illustrative of the preferred embodiments of the present invention, goes here and there not to limit the present invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (5)
1. a kind of adaptive serial clock sequence detecting apparatus, it is characterised in that: including clock sequence input terminal, the clock sequence
Column input terminal connects the input terminal of COM character machining module, the output end connection PCIe clock sequence inspection of the COM detection module
The input terminal of unit is surveyed, the output end connection RapidIO clock sequence detection unit of the PCIe clock sequence detecting unit
Input terminal, the output end output test result of the RapidIO clock sequence detection unit；
The PCIe clock sequence detecting unit includes 3 concatenated SKP character machining modules, the SKP character machining module
Output end be connected to the input terminal of the first AND gate circuit together with the output end of the COM character machining module, described first
The output end output PCIe clock of AND gate circuit compensates sequence indication signal, and the output end of first AND gate circuit is also connected with the
One logic circuit generates PCIe protocol indication signal by the first logic circuit；First logic circuit is also selected by third
Logical device connects the RapidIO clock sequence detection unit；
The RapidIO clock sequence detection unit includes 3 concatenated R character machining modules, the R character machining module
Output end is connected to the input terminal of the second AND gate circuit together with the output end of the COM character machining module, described second with
The output end of gate circuit exports RapidIO clock compensation sequence indication signal, and the output end of second AND gate circuit is also connected with
Second logic circuit generates RapidIO agreement indication signal by the second logic circuit；Second logic circuit also passes through
Four gates connect PCIe clock sequence detecting unit.
2. a kind of adaptive serial clock sequence detecting apparatus according to claim 1, it is characterised in that: described first patrols
Collecting circuit includes the first gate and the first d type flip flop, and the output end of first gate connects the input of the first d type flip flop
End, the control signal of first gate connect the output end of the first AND gate circuit, the output end of first d type flip flop
On the one hand the input terminal for connecting the first gate, on the other hand connects the control signal of third gate.
3. a kind of adaptive serial clock sequence detecting apparatus according to claim 1, it is characterised in that: described second patrols
Collecting circuit includes the second gate and the second d type flip flop, and the output end of second gate connects the input of the second d type flip flop
End, the control signal of second gate connect the output end of the second AND gate circuit, the output end of second d type flip flop
On the one hand the input terminal for connecting the second gate, on the other hand connects the control signal of the 4th gate.
4. a kind of adaptive serial clock sequence detecting apparatus according to claim 1, it is characterised in that: first choosing
Logical device, the second gate, third gate, the 4th gate are alternative gate.
5. a kind of detection method using the described in any item adaptive serial clock sequence detecting apparatus of claim 1-4,
It is characterized in that: specifically comprising the following steps
(1) data flow flows into PCIe clock sequence detecting unit and RapidIO clock sequence detection unit is detected；
(2) if PCIe clock sequence detecting unit detects continuous SKP character, pass through third gate for RapidIO clock
The enable signal of sequence detecting unit is set in vain, exports the data from PCIe clock sequence detecting unit；
(3) if RapidIO clock sequence detection unit detects continuous K character, pass through the 4th gate for PCIe clock sequence
The enable signal of column detection unit is set in vain, exports the data from RapidIO clock sequence detection unit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110362278A (en) * | 2019-07-23 | 2019-10-22 | 天津国芯科技有限公司 | A kind of elastic caching device of high-speed transfer |
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