CN109830483B

CN109830483B - 3D NAND memory and forming method thereof

Info

Publication number: CN109830483B
Application number: CN201910114113.7A
Authority: CN
Inventors: 霍宗亮; 薛家倩
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-02-14
Filing date: 2019-02-14
Publication date: 2021-07-02
Anticipated expiration: 2039-02-14
Also published as: CN109830483A

Abstract

A 3D NAND memory and method of forming the same, wherein the method of forming comprises: the stacked structure comprises a plurality of sacrificial layers and isolation layers which are alternately stacked, a first channel hole and a second channel hole are formed in the stacked structure, the second channel hole is communicated with the first channel hole, the second channel hole is aligned and deviated relative to the first channel hole, and a step is formed at the junction of the first channel hole and the second channel hole; forming a charge storage layer on sidewalls and bottoms of the first and second channel holes; forming a channel hole sacrificial layer on the charge storage layer; forming a protective layer on the channel hole sacrificial layer; and sequentially etching the protective layer, the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole to form an opening exposing the surface of the semiconductor epitaxial layer. The method of the invention prevents the charge storage layer at the step from being cut off or damaged, thereby preventing the memory from failing.

Description

3D NAND memory and forming method thereof

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND memory and a forming method thereof.

Background

NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile storage products with low power consumption, light weight and good performance. At present, NAND flash memories with a planar structure are approaching the limit of practical expansion, and in order to further increase the storage capacity and reduce the storage cost per bit, 3D NAND memories with a 3D structure are proposed.

The existing manufacturing process of the 3D NAND memory comprises the following steps: providing a substrate, wherein a stacked structure in which isolation layers and sacrificial layers are alternately stacked is formed on the substrate; etching the stacked structure, and forming a channel hole exposing the surface of the substrate in the stacked structure; forming a storage structure in the channel hole; after the storage structure is formed, etching the stacked structure, and forming a grid separation groove in the stacked structure; removing the sacrificial layer, and forming a control gate at the position where the sacrificial layer is removed; and filling a conductive material in the grid isolation groove to form an array common source.

In order to further increase the storage capacity, in the prior art, when the stacked structure is formed, a multi-layer stacked structure is usually formed, each layer of stacked structure includes a plurality of sacrificial layers and isolation layers which are alternately stacked, and a channel hole is formed in the multi-layer stacked structure; a memory structure is formed in the channel hole, but such a memory structure still has a problem of failure.

Disclosure of Invention

The invention aims to solve the technical problem of how to prevent the failure of a storage structure.

The invention provides a method for forming a 3D NAND memory, which comprises the following steps:

providing a semiconductor substrate, wherein a stacked structure is formed on the semiconductor substrate, the stacked structure comprises a plurality of sacrificial layers and isolation layers which are alternately stacked, a first channel hole and a second channel hole are formed in the stacked structure, the second channel hole is communicated with the first channel hole, the second channel hole is in alignment offset relative to the first channel hole, and a step is formed at the junction of the first channel hole and the second channel hole;

forming a charge storage layer on sidewalls and bottoms of the first and second channel holes;

forming a channel hole sacrificial layer on the charge storage layer;

forming a protective layer on the channel hole sacrificial layer;

and sequentially etching the protective layer, the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole to form an opening.

Optionally, the stacked structure includes a first stacked structure and a second stacked structure located on the first stacked structure, the first stacked structure and the second stacked structure each include a plurality of sacrificial layers and isolation layers stacked alternately, the first stacked structure has a first channel hole penetrating through a thickness of the first stacked structure, a semiconductor substrate at a bottom of the first channel hole has a groove therein, and a semiconductor epitaxial layer is formed in the groove; a second channel hole penetrating through the thickness of the second stacking structure is formed in the second stacking structure; the opening exposes a surface of the semiconductor epitaxial layer.

Optionally, the channel hole sacrificial layer and the protective layer are made of different materials.

Optionally, the channel hole sacrificial layer is made of polysilicon, amorphous silicon or amorphous carbon, and the protective layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or boron nitride.

Optionally, the step of sequentially etching the protective layer, the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole is performed by an anisotropic dry etching process.

Optionally, different etching gases are used for etching the channel hole sacrificial layer and the etching protective layer, and different etching gases are used for etching the charge storage layer and the etching channel hole sacrificial layer.

Optionally, after etching the protective layer on the bottom of the first channel hole, a protective sidewall is formed on the surface of the channel hole sacrificial layer on the sidewalls of the first channel hole and the second channel hole.

Optionally, when the charge storage layer is etched through, the protective sidewall and the channel hole sacrificial layer are synchronously etched and removed, or after the opening is formed, the protective sidewall and the channel hole sacrificial layer are removed.

Optionally, forming a channel layer on a surface of the charge storage layer and in the opening; and forming a filling layer on the channel layer, wherein the filling layer fills the first channel hole and the second channel hole.

Optionally, after forming the channel layer or forming the filling layer, removing the sacrificial layer in the first stacked structure and the second stacked structure; and correspondingly forming a control gate at the position of the sacrificial layer.

Optionally, the charge storage layer includes a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.

The present invention also provides a 3D NAND memory, comprising:

the semiconductor device comprises a semiconductor substrate, wherein a stacked structure is formed on the semiconductor substrate, the stacked structure comprises a plurality of sacrificial layers and isolation layers which are alternately stacked, a first channel hole and a second channel hole are formed in the stacked structure, the second channel hole is communicated with the first channel hole, the second channel hole is aligned and deviated relative to the first channel hole, and a step is formed at the junction of the first channel hole and the second channel hole;

a charge storage layer on sidewalls and a bottom of the first and second channel holes;

a channel hole sacrificial layer on the charge storage layer;

and the protective layer is positioned on the channel hole sacrificial layer and used for protecting the channel hole sacrificial layer from effectively protecting the charge storage layer near the step when the charge storage layer at the bottom of the first channel hole is etched in the subsequent step to form an opening.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the forming method of the 3D NAND memory, when the first channel hole and the second channel hole have alignment offset and a step is formed at the junction of the first channel hole and the second channel hole, after the charge storage layer is formed on the side wall and the bottom of the first channel hole and the second channel hole, the channel hole sacrificial layer is formed on the charge storage layer; forming a protective layer on the channel hole sacrificial layer, wherein when etching and removing part of the protective layer on the bottom of the first channel hole, the etching time is short, and when the protective layer is formed, the thickness of the protective layer at the step is larger than that of the protective layer at the bottom of the first channel hole (the width of the communication part of the first channel hole and the second channel hole is reduced due to the offset of the second channel hole relative to the first channel hole at the step, and the deposition gas entering during the formation of the protective layer is also reduced), so that the protective layer at the step and the side walls of the first channel hole and the second channel hole can be retained or removed by a small amount, and the channel hole sacrificial layer and the storage layer at the bottom of the first channel hole are etched subsequently to form (expose the semiconductor substrate or the semiconductor epitaxial layer) an opening, the protective layer can protect the channel hole sacrificial layer at the bottom, and the channel hole sacrificial layer near the step is etched and removed by a small amount, therefore, in the whole etching process, the charge storage layer at the step is always covered by the channel hole sacrificial layer to protect the charge storage layer at the step, so that the charge storage layer at the step is prevented from being etched through or damaged, and the NAND memory is prevented from failing.

Further, different etching gases are adopted when the channel hole sacrificial layer and the etching protective layer are etched, and different etching gases are adopted when the charge storage layer and the etching channel hole sacrificial layer are etched, so that the etching rate of the protective layer is low, the protective time of the protective layer for the channel hole sacrificial layer at the bottom is prolonged, and the time of the channel hole sacrificial layer for protecting the charge storage layer at the bottom is prolonged.

Drawings

FIGS. 1-2 are cross-sectional views illustrating a process of forming a 3D NAND memory according to an embodiment of the present invention;

3-16 are cross-sectional views illustrating a process of forming a 3D NAND memory according to another embodiment of the present invention;

FIGS. 17-22 are schematic cross-sectional views illustrating a process of forming a 3D NAND memory according to another embodiment of the present invention;

FIGS. 17-27 are schematic cross-sectional views illustrating a process of forming a 3D NAND memory according to yet another embodiment of the present invention;

FIGS. 28-35 are schematic cross-sectional views illustrating a process of forming a 3D NAND memory according to another embodiment of the present invention.

Detailed Description

As described in the background, the conventional multi-layer stack structure 3D NAND memory has a problem of failure.

It is found that the failure problem of the multi-layer stacked 3D NAND memory generally occurs at the boundary of the multi-layer stacked structure, specifically at the 20 positions indicated by the dashed box in fig. 2.

Through further research, the specific reasons for the problems are as follows: fig. 1-2 are schematic cross-sectional views illustrating a cross-sectional structure of a 3D NAND memory according to an embodiment of the invention, first referring to fig. 1, a first stacked structure 211 is formed on a semiconductor substrate 200, the first stacked structure 211 includes a plurality of sacrificial layers 203 and insulating layers 204 stacked alternately, and a buffer oxide layer 201 and a dielectric layer 202 may be further formed between the first stacked structure 211 and the semiconductor substrate 200; etching the first stacked structure 211 to form a first channel hole 205 penetrating the thickness of the first stacked structure 211; after the first channel hole 205 is formed, the buffer oxide layer 201 and the dielectric layer 202 at the bottom and part of the semiconductor substrate 200 are etched continuously, and a groove is formed at the bottom of the first channel hole 205; forming an epitaxial silicon layer 207 in the groove by an epitaxial process; filling the first channel hole 205 with a filling material layer; forming a second stacked structure 212 on the first stacked structure 211, wherein the second stacked structure 212 includes a plurality of sacrificial layers 209 and insulating layers 210 which are alternately stacked; etching the second stacked structure 212 to form a second channel hole 215 penetrating through the thickness of the first stacked structure 211, the second channel hole 215 communicating with the first channel hole 205, the second channel hole 215 being offset with respect to the first channel hole 205, that is, a central axis of the second channel hole 215 is offset from a central axis of the first channel hole 205 (the central axis is a straight line passing through the center of the second channel hole 215 or the first channel hole 205 and perpendicular to the surface of the semiconductor substrate 200), so that a step 23 is formed at an interface position of sidewalls of the second channel hole 215 and the first channel hole 205; a charge storage layer 216 is formed on the sidewalls and bottom surfaces of the second channel hole 215 and the first channel hole 205, the charge storage layer 216 is a stacked structure of a silicon oxide layer-a silicon nitride layer-a silicon oxide layer, and a polysilicon layer 217 is formed on the charge storage layer 216.

Next, referring to fig. 2, the polysilicon layer 217 and the charge storage layer 216 at the bottom of the first channel hole 205 are etched to remove the polysilicon layer 217 and the charge storage layer 216 at the bottom of the first channel hole 205, and an opening 225 exposing the surface of the epitaxial silicon layer 207 is formed, where the polysilicon layer 217 is used to protect the charge storage layer 216 at the sidewalls of the first channel hole 205 and the second channel hole 215 from being damaged when the charge storage layer 216 is etched, but in this embodiment, since the second channel hole 215 has an alignment offset with respect to the first channel hole 205, a step 23 is formed at an interface position of the sidewalls of the second channel hole 215 and the first channel hole 205, a slope of the step 23 is steep, the step 23 may block plasma generated during etching, and when the polysilicon layer 217 and the charge storage layer 216 are etched, an etching rate of the polysilicon layer 217 at the step 23 is greater than an etching rate of the polysilicon layer 217 at the bottom of the first channel hole 205 or substantially the same etching rates of the polysilicon, subsequently, when the etching of the charge storage layer 216 is continued, since the charge storage layer 216 at the step 23 is not covered by the polysilicon layer 217 or is only covered by a little polysilicon layer, the charge storage layer 216 at the step 23 is also etched, so that the charge storage layer 216 at the step 23 is broken or damaged, an etching defect 21 is formed, and since the charge storage layer 216 is used for storing charges, the charge storage layer 216 at the step 23 is broken or damaged and cannot store charges, thereby causing the failure of the 3D NAND memory.

Furthermore, when it is found that the second channel hole 215 has an alignment deviation with respect to the first channel hole 205 or the charge storage layer 216 at the step 23 is cut or damaged, it is a common operation to rework the wafer having problems, but such an operation is very costly, time-consuming and labor-consuming.

Therefore, the invention provides a 3D NAND memory and a forming method thereof, the forming method comprises the steps of forming a protective layer on a channel hole sacrificial layer, when etching and removing part of the protective layer on the bottom of a first channel hole, because the etching time is short, and when the protective layer is formed, the thickness of the protective layer at a step is larger than that of the protective layer at the bottom of the first channel hole (because a second channel hole is offset relative to the first channel hole at the step, the width of the communication part of the first channel hole and the second channel hole is reduced, and the entering deposition gas is also reduced when the protective layer is formed), so that the protective layer at the step and the side walls of the first channel hole and the second channel hole is less reserved or removed, and when the channel hole sacrificial layer and a charge storage layer at the bottom of the first channel hole are etched subsequently, the protective layer can protect the channel hole sacrificial layer at the bottom, the amount of the channel hole sacrificial layer near the step is removed by etching is small, so that the charge storage layer at the step is always covered by the channel hole sacrificial layer in the whole etching process to protect the charge storage layer at the step, and the charge storage layer at the step is prevented from being etched through or damaged to prevent the NAND memory from failing.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

FIGS. 3-16 are cross-sectional views illustrating a process of forming a 3D NAND memory according to another embodiment of the present invention.

Referring to fig. 3, a semiconductor substrate 100 is provided, the semiconductor substrate 100 having a stack structure formed thereon, the stack structure including a first stack structure 111 on the semiconductor substrate 100 and a second stack structure (described later) on the first stack structure 111, the first stack structure 111 including a plurality of sacrificial layers 103 and isolation layers 104 stacked alternately, the first stack structure 111 having a first channel hole 105 formed therein through a thickness of the first stack structure 111.

The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).

The first stacked structure 111 comprises a plurality of sacrificial layers 103 and isolation layers 104 which are alternately stacked, the sacrificial layers 103 are subsequently removed to form a cavity, and then a control gate is formed at the position where the sacrificial layers 103 are removed. The isolation layer 104 serves as electrical isolation between different layers of the control gate, and between the control gate and other devices (conductive contacts, trench holes, etc.).

The sacrificial layer 103 and the isolation layer 104 are alternately stacked, that is: after forming a layer of sacrificial layer 103, a layer of isolation layer 104 is formed on the surface of sacrificial layer 103, and then the steps of forming sacrificial layer 103 and isolation layer 104 on sacrificial layer 103 are sequentially performed cyclically. In this embodiment, the bottom layer of the first stacked structure 111 is a sacrificial layer 103, and the top layer is an isolation layer 104.

The number of layers of the first stacked structure 111 (the number of layers of the dual-layer stacked structure including the sacrificial layer 103 and the isolation layer 104 in the first stacked structure 111) is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the first stacked structure 111 may be 8, 32, 64, or the like, and the greater the number of layers of the first stacked structure 111, the greater the integration level can be. In the present embodiment, only the number of layers of the first stacked structure 111 is 4 as an example.

The sacrificial layer 103 and the isolation layer 104 are made of different materials, and when the sacrificial layer 103 is removed subsequently, the sacrificial layer 103 has a high etching selectivity relative to the isolation layer 104, so that when the sacrificial layer 103 is removed, the etching amount of the isolation layer 104 is small or negligible, and the integrity of the isolation layer 104 is ensured.

The isolation layer 104 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the sacrificial layer 103 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the isolation layer 104 is made of silicon oxide, the sacrificial layer 103 is made of silicon nitride, and the isolation layer 104 and the sacrificial layer 103 are formed by a chemical vapor deposition process.

The first channel hole 105 is formed through an anisotropic dry etching process, the anisotropic dry etching process may be a plasma etching process, before the etching process is performed, a patterned mask layer is formed on the first stacked structure 111, the patterned mask layer has an opening exposing the surface of the first stacked structure 111, and when etching is performed, the first stacked structure 111 is etched by using the patterned mask layer as a mask, and the first channel hole 105 is formed in the first stacked structure 111.

In an embodiment, a buffer oxide layer 101 and a dielectric layer 102 located on the buffer oxide layer 101 are further formed between the first stacked structure 111 and the semiconductor substrate 100, and after the first channel hole 105 is formed, the buffer oxide layer 101 and the dielectric layer 102 at the bottom of the first channel hole 105 and a part of the semiconductor substrate 100 are continuously etched to form a groove 106; an epitaxial semiconductor layer 107 (refer to fig. 4) is formed in the groove 106 through a selective epitaxial process, a surface of the epitaxial semiconductor layer 107 is lower than a surface of the dielectric layer 102 and higher than a surface of the semiconductor substrate 100, the epitaxial semiconductor layer 107 is made of silicon, germanium or silicon germanium, and in this embodiment, the epitaxial semiconductor layer 107 is made of silicon.

In an embodiment, the dielectric layer 102 is a two-layer stacked structure including a silicon nitride layer on the buffer oxide layer 101 and a silicon oxide layer on the silicon nitride layer.

Referring to fig. 5, a second stacked structure 112 is formed on the first stacked structure 111, and the second stacked structure 112 includes a plurality of sacrificial layers 109 and isolation layers 110 alternately stacked.

The sacrificial layer 109 is subsequently removed to form a cavity, and then a control gate is formed where the sacrificial layer 109 is removed. The isolation layer 110 serves as electrical isolation between different layers of the control gate, and between the control gate and other devices (conductive contacts, trench holes, etc.).

The sacrificial layer 109 and the isolation layer 110 are alternately stacked, that is: after forming a sacrificial layer 109, an isolation layer 110 is formed on the surface of the sacrificial layer 109, and then the steps of forming the sacrificial layer 109 and the isolation layer 110 on the sacrificial layer 109 are sequentially performed cyclically. In this embodiment, the bottom layer of the second stacked structure 112 is a sacrificial layer 109, and the top layer is an isolation layer 110.

The number of layers of the second stacked structure 112 (the number of layers of the dual-layer stacked structure of the sacrificial layer 109 and the isolation layer 110 in the second stacked structure 112) is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the second stacked structure 112 may be 8, 32, 64, and the like, and the greater the number of layers of the second stacked structure 112, the higher the integration level is. In the present embodiment, only the number of layers of the second stacked structure 112 is 4 as an example.

The sacrificial layer 109 and the isolation layer 110 are made of different materials, and when the sacrificial layer 109 is removed subsequently, the sacrificial layer 109 has a high etching selectivity relative to the isolation layer 110, so that when the sacrificial layer 109 is removed, the etching amount of the isolation layer 110 is small or negligible, and the integrity of the isolation layer 110 is ensured.

The isolation layer 110 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the sacrificial layer 109 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the isolation layer 110 is made of silicon oxide, the sacrificial layer 109 is made of silicon nitride, and the isolation layer 110 and the sacrificial layer 109 are formed by a chemical vapor deposition process.

In an embodiment, before forming the second stacked structure 112, the first channel hole 105 is filled with a sacrificial material layer 108, and the material of the sacrificial material layer 108 may be polysilicon, amorphous silicon, or amorphous carbon. In this embodiment, the material of the sacrificial material layer 108 is polysilicon.

Referring to fig. 6, the second stacked structure 112 is etched, a second channel hole 115 penetrating the thickness of the second stacked structure 112 is formed in the second stacked structure 112, the second channel hole 115 is communicated with the first channel hole 105, and the second channel hole 115 is aligned and offset with respect to the first channel hole 105, so that a step 10 is formed at the intersection of the first channel hole 105 and the second channel hole 15.

The second stacked structure 112 is etched to form the second channel hole 115 by using an anisotropic dry etching process, which is a plasma etching process in a specific embodiment.

In an embodiment, before the second stacked structure 112 is etched, a buffer oxide layer 113 and a dielectric layer 114 on the buffer oxide layer 113 are formed on the second stacked structure 112, and before the second stacked structure 112 is etched, an opening corresponding to the second channel hole 115 is formed in the dielectric layer 114 and the buffer oxide layer 113.

In one embodiment, the dielectric layer 114 may be a two-layer stacked structure including a silicon nitride layer on the buffer oxide layer 113 and a silicon oxide layer on the surface of the silicon nitride layer.

In the actual manufacturing process of the NAND memory, due to the deviation of the photolithography and/or etching process, when the second stacked structure 112 is etched to form the second channel hole 115, there is an alignment offset of the second channel hole 115 relative to the first channel hole 105, that is, the central axis of the second channel hole 115 is offset from the central axis of the first channel hole 105 (the central axis is a straight line passing through the center of the second channel hole 115 or the first channel hole 105 and perpendicular to the surface of the semiconductor substrate 100), so that the interface position of the second channel hole 115 and the sidewall of the first channel hole 105 forms a step 10, the presence of the step 10 subsequently etches the charge storage layer at the bottom of the first channel hole 105, and when an opening exposing the surface of the epitaxial semiconductor layer 107 is formed, the charge storage layer at the interface between the first channel hole 105 and the second channel hole 115 (or at the interface between the first stacked structure 111 and the second stacked structure 112) is broken or damaged, leading to failure of the NAND memory.

In the present embodiment, only one first stack structure and one second stack structure are taken as an example for explanation, and in other embodiments, the first stack structure and the second stack structure may be plural, and plural first stack structures and plural second stack structures are alternately stacked.

Referring to fig. 7, 8 and 9, a charge storage layer 116 is formed on sidewalls and bottoms of the first and second channel holes 105 and 115.

The charge storage layer 116 is used to store charge. The sacrificial material layer 108 is removed prior to forming the charge storage layer 116. In one embodiment, the sacrificial material layer 108 is removed by a wet etching process.

Referring to fig. 9, fig. 9 is an enlarged schematic structural view of the charge storage layer 116 formed in fig. 8, where the charge storage layer 116 includes a blocking oxide layer 116a, a charge trapping layer 116b on the blocking oxide layer 116a, and a tunneling oxide layer 116c on the charge trapping layer 116 b.

The material of the blocking oxide layer 116a and the tunneling oxide layer 116c is silicon oxide, and the material of the charge trapping layer 116b is silicon nitride. The charge trapping layer 116b, the tunnel oxide layer 116c and the blocking oxide layer 116a are formed by a chemical vapor deposition process.

The first contact hole 105 and the second contact hole 115 form a step 10 at the interface due to the misalignment, and when the charge storage layer 116 is formed, a step may also exist at the surface of the charge storage layer 116 at the step 10.

Referring to fig. 10, a channel hole sacrificial layer 117 is formed on the charge storage layer 116; a protective layer 118 is formed on the channel hole sacrificial layer 117.

The channel hole sacrificial layer 117 is used for protecting the charge storage layer 116 on the sidewalls of the first channel hole 105 and the second channel hole 115 from being intact when the charge storage layer 116 at the bottom of the first channel hole 105 is subsequently etched to form an opening exposing the semiconductor epitaxial layer 107 at the bottom.

The protective layer 118 serves to protect the channel hole sacrificial layer 117 during the entire etching process (when the opening exposing the semiconductor epitaxial layer 107 is formed) so that the channel hole sacrificial layer 117 can effectively protect the charge storage layer 116 near the step 10.

The channel hole sacrificial layer 117 and the protective layer 118 are made of different materials, and subsequently, when the channel hole sacrificial layer 118 is etched, the channel hole sacrificial layer 117 has a high etching selectivity relative to the protective layer 118, so that the protective layer 118 can better protect the channel sacrificial layer 117.

The channel hole sacrificial layer 117 is made of polysilicon, amorphous silicon, or amorphous carbon. The material of the protection layer 118 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or boron nitride. In this embodiment, the channel hole sacrificial layer 117 is made of polysilicon, the protective layer 118 is made of silicon oxide, and the forming process of the sacrificial layer 117 and the protective layer 118 is a chemical vapor deposition process.

Referring to fig. 11, 12, and 13 in combination, the protective layer 118, the channel hole sacrificial layer 117, and the charge storage layer 116 on the bottom of the first channel hole 115 are sequentially etched to form an opening 125 (exposing the surface of the semiconductor epitaxial layer 107).

And sequentially etching the protective layer, the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole by adopting an anisotropic dry etching process, wherein the anisotropic dry etching process can be a plasma etching process.

When etching to remove part of the protection layer 118 on the bottom of the first channel hole 105, because the etching time is shorter, and the protection layer 118 is formed as described above, the thickness of the protection layer 118 at the step 10 is greater than the thickness of the protection layer 118 at the bottom of the first channel hole 105 (the width of the place where the first channel hole 105 communicates with the second channel hole 115 is reduced due to the offset of the second channel hole 115 with respect to the first channel hole 105 at the step 10, so that the entering deposition gas is also reduced), so that the protection layer 118 at the step 10 and at the sidewalls of the first channel hole 105 and the second channel hole 115 is retained or removed by a smaller amount, and thus when the channel hole sacrificial layer 117 and the charge storage layer 116 at the bottom of the first channel hole 105 are etched later, the protection layer 118 can protect the channel hole sacrificial layer 117 at the bottom, so that the channel hole sacrificial layer 117 near the step 10 is etched and removed by a smaller amount, therefore, the charge storage layer 116 at the step 10 is always covered by the channel hole sacrificial layer in the whole etching process to protect the charge storage layer 116 at the step 10, so as to prevent the charge storage layer 116 at the step 10 from being etched through or damaged, and thus prevent the NAND memory from failing.

In one embodiment, different etching gases are used for etching the channel hole sacrificial layer 117 and the etching protection layer 118, and the charge storage layer 116 and the channel hole sacrificial layer 11 are etched7, different etching gases are used, so that the etching rate of the protective layer 118 is lower, the protective layer protects the bottom channel hole sacrificial layer 117 for a longer time, and the channel hole sacrificial layer 117 protects the bottom charge storage layer 116 for a longer time. In one embodiment, the gas used to etch the protective layer 118 is C₄F₈、C₅F₈、 C₄F₆The gas used for etching the channel hole sacrificial layer 117 is HBr or SF₆And NF₃The gas used for etching the charge storage layer 116 is CF₄、C₄F₈、CH₃F、 CH₂F₂One or more of them.

In an embodiment, during the anisotropic dry etching, a portion of the protection layer 118 on the bottom of the first channel hole 105 is removed by etching, a protection sidewall 119 is formed on the surface of the channel hole sacrificial layer on the sidewalls of the first channel hole 105 and the second channel hole 115, then the channel hole sacrificial layer 117 on the bottom of the first channel hole 105 is etched, and then the charge storage layer 116 on the bottom of the first channel hole 105 is etched, so as to form an opening 125 exposing the surface of the semiconductor epitaxial layer 107.

In other embodiments, the same etching gas may be used for etching the channel hole sacrificial layer and the charge storage layer.

In an embodiment, when the charge storage layer 116 is etched through, the protective sidewall 119 and the channel hole sacrificial layer 117 are simultaneously etched and removed, or after the opening 125 is formed, the protective sidewall 119 and the channel hole sacrificial layer 117 are removed.

Referring to fig. 14, a channel layer 120 is formed on a surface of the charge storage layer 116 and in the opening 125.

The channel layer 120 is in contact with the semiconductor epitaxial layer 107. In this embodiment, the material of the channel layer 120 is polysilicon, and the forming process of the channel layer 120 is chemical vapor deposition.

Referring to fig. 15, a filling layer 121 is formed on the channel layer 120, the filling layer 121 filling the first and second channel holes.

The material of the filling layer 121 is silicon oxide or other suitable materials.

Referring to fig. 16, after forming the channel layer 120 or forming the filler layer 121, the sacrificial layers 103 and 109 (refer to fig. 15) in the first and

second stack structures

111 and 112 are removed; control gate 123 and control gate 129 are formed at positions where sacrificial layer 103 and sacrificial layer 109 are removed.

Fill layer 120 and charge storage layer 116 on dielectric layer 114 are planarized away before sacrificial layer 103 and sacrificial layer 109 are removed.

Wet etching may be used to remove the sacrificial layer 103 and the sacrificial layer 109.

The material of control gate 123 and control gate 129 may be metal or other conductive material (e.g., polysilicon, etc.). In this embodiment, the conductive material is a metal, and the metal is one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

In an embodiment, a high-K dielectric layer is further formed between the control gate 123 and the control gate 129 and the corresponding isolation layer 104 and isolation layer 110, and the material HfO of the high-K dielectric layer₂、TiO₂、HfZrO、 HfSiNO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃Or BaSrTiO.

In an embodiment, when the sacrificial layer 103 and the sacrificial layer 109 are removed, the silicon nitride layer in the dielectric layer 102 is simultaneously removed, and the selection gate 132 is correspondingly formed at the position where the silicon nitride layer is removed, and the formation process of the selection gate 132 is the same as the formation steps of the control gate 123 and the control gate 129.

An embodiment of the present invention further provides a 3D NAND memory, referring to fig. 10, including:

a semiconductor substrate 100, wherein a stack structure is formed on the semiconductor substrate 100, the stack structure comprises a first stack structure 111 and a second stack structure 112 located on the first stack structure 111, the first stack structure 111 and the second stack structure 112 each comprise a plurality of sacrificial layers (103, 109) and isolation layers (104, 110) which are alternately stacked, the first stack structure 111 has a first channel hole 105 penetrating through the thickness of the first stack structure, the semiconductor substrate 100 at the bottom of the first channel hole 105 has a groove, and a semiconductor epitaxial layer 107 is formed in the groove; a second channel hole 115 penetrating through the thickness of the second stacked structure is formed in the second stacked structure 112, the second channel hole 115 is communicated with the first channel hole 105, the second channel hole 115 is aligned and offset with respect to the first channel hole 105, and a step 10 is formed at the intersection of the first channel hole 105 and the second channel hole 115;

a charge storage layer 116 on sidewalls and a bottom of the first and second channel holes 105 and 115;

a channel hole sacrificial layer 117 on the charge storage layer 116;

and the protective layer 118 is located on the channel hole sacrificial layer 117, and the protective layer 118 is used for protecting the channel hole sacrificial layer 117 from effectively protecting the charge storage layer 116 near the step 10 when the charge storage layer 116 at the bottom of the first channel hole 105 is etched later to form an opening exposing the semiconductor epitaxial layer 107 at the bottom.

Specifically, the materials of the channel hole sacrificial layer 117 and the protective layer 118 are different.

In one embodiment, the material of the channel hole sacrificial layer 117 is polysilicon, amorphous silicon or amorphous carbon. The material of the protection layer 118 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or boron nitride.

FIGS. 17-22 are schematic cross-sectional views illustrating a process of forming a 3D NAND memory according to another embodiment of the present invention.

Referring to fig. 17, fig. 17 is performed on the basis of fig. 6, and a semiconductor substrate 100 is provided, wherein a stacked structure is formed on the semiconductor substrate 100, the stacked structure includes a first stacked structure 111 located on the semiconductor substrate 100 and a second stacked structure 112 located on the first stacked structure 111, each of the first stacked structure 111 and the second stacked structure 112 includes a plurality of alternately stacked sacrificial layers (103, 109) and isolation layers (104, 110), the first stacked structure 111 has a first channel hole 105 penetrating through a thickness of the first stacked structure, a bottom of the first channel hole 105 has a groove in the semiconductor substrate 100, and a semiconductor epitaxial layer 107 is formed in the groove; the second stacked structure 112 has a second channel hole 115 formed therein and penetrating through the thickness of the second stacked structure, the second channel hole 115 is communicated with the first channel hole 105, and the second channel hole 115 is offset with respect to the first channel hole 105, so that a step 10 is formed at the intersection of the first channel hole 105 and the second channel hole 115.

In an embodiment, the forming process of the first stacked structure 111 and the second stacked structure 112 includes: a first stacked structure 111 is formed on the semiconductor substrate 100; etching the first stacked structure 111 to form a first channel hole 105 penetrating through the thickness of the first stacked structure; forming a groove in the semiconductor substrate 100 at the bottom of the first channel hole 105; a semiconductor epitaxial layer 107 is formed in the groove; filling the first channel hole 105 with a sacrificial material layer 108; forming a second stack structure 112 on the first stack structure 111 and the sacrificial material layer 108; and etching the second stacked structure 112 to form a second channel hole 115 penetrating through the thickness of the second stacked structure, wherein the second channel hole 115 is communicated with the first channel hole 105, the second channel hole 115 is aligned and deviated relative to the first channel hole 105, and a step 10 is formed at the junction of the first channel hole 105 and the second channel hole 105.

The sacrificial material layer 108 is different from the materials of the first stacked structure 111 and the second stacked structure 112, and then a part of the thickness of the sacrificial material layer 108 is etched back, so that the sacrificial material layer 108 has a high etching selectivity relative to the materials of the first stacked structure 111 and the second stacked structure 112.

The material of the sacrificial material layer 108 may be polysilicon, amorphous silicon or amorphous carbon. In this embodiment, the material of the sacrificial material layer 108 is polysilicon.

Referring to fig. 18, the step 10 is etched 201 such that the slope of the step 10 becomes gentle.

In this embodiment, the step 10 is etched to make the gradient of the step 10 gradually decrease, and then when a charge storage layer and a channel hole sacrificial layer on the charge storage layer are formed in the first channel hole 105 and the second channel hole 115, the gradients of the charge storage layer and the channel hole sacrificial layer formed at the step 10 with gradually decreasing gradients gradually decrease, and then the channel hole sacrificial layer and the charge storage layer at the bottom of the first channel hole 105 are etched to form an opening exposing the surface of the semiconductor epitaxial layer 107, the channel hole sacrificial layer at the step 10 with gradually decreasing gradients blocks less plasma, so that the amount of etching removal of the channel hole sacrificial layer at the step 10 with gradually decreasing gradients is less, and the charge storage layer at the step 10 is always covered by the channel hole sacrificial layer in the whole etching process for forming the opening, so as to protect the charge storage layer at the step 10, thereby preventing the charge storage layer at the step 10 from being etched through or damaged during the process of forming the opening, and preventing the NAND memory from failing.

In this embodiment, before the step 10 is etched, the sacrificial material layer 108 with a partial thickness is etched back to remove the partial thickness, and the sidewall of the partial first channel hole 105 below the step 10 is exposed, so that the gradient of the step 10 can be made slower when the step 10 is etched, and when a charge storage layer and a channel hole sacrificial layer located on the charge storage layer are formed in the first channel hole 105 and the second channel hole 115 subsequently, the gradient of the charge storage layer and the surface of the channel hole sacrificial layer formed at the step 10 with the slower gradient is made slower, and when the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole 105 are etched to form an opening exposing the surface of the semiconductor epitaxial layer 107, the amount of the channel hole sacrificial layer of the step 10 removed is less, so that the charge storage layer of the step 10 can be better protected all the time; in addition, the remaining sacrificial material layer 108 may prevent the first stacked structure 111 from being damaged by etching.

In one embodiment, the sacrificial material layer 108 is etched back to a thickness greater than the lateral width of the step 10 to facilitate the gradual slope of the step 10.

The step 201 may be etched by sputtering, dry etching process or Focused Ion beam (FBI) etching process. In one embodiment, the sputtering may use inert gas ions, and the dry etching is a plasma etching process.

Referring to fig. 19, the remaining sacrificial material layer 108 (refer to fig. 18) is removed.

The remaining sacrificial material layer 108 is removed using a wet etching process.

Referring to fig. 20, after the step 10 is etched, a charge storage layer 116 is formed on sidewalls and bottoms of the first and second channel holes 105 and 115; a channel hole sacrificial layer 117 is formed on the charge storage layer 116.

The charge storage layer 116 includes a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.

Referring to fig. 21, the first channel, the channel hole sacrificial layer 117 and the charge storage layer 116 on the bottom of the channel 105 are sequentially etched to form an opening 125 (exposing the surface of the semiconductor epitaxial layer 107).

In one embodiment, the channel hole sacrificial layer 117 is simultaneously etched away when the charge storage layer 116 is etched through, or removed after the opening 125 is formed.

Referring to fig. 20, a channel layer 120 is formed on a surface of the charge storage layer 116 and in the opening 125 (refer to fig. 21); a filling layer 121 is formed on the channel layer 120, and the filling layer 121 fills the first channel hole and the second channel hole.

Further comprising, after forming the channel layer 120 or forming the filling layer 121, removing the sacrificial layers (103, 109) in the first stacked structure 111 and the second stacked structure 112; control gates are formed at locations corresponding to where the sacrificial layer (103/109) is removed.

It should be noted that other definitions or descriptions of the same or similar structures in this embodiment as those in the foregoing embodiment are not repeated in this embodiment, and specific reference is made to the definitions or descriptions of corresponding parts in the foregoing embodiment.

FIGS. 23-27 are cross-sectional views illustrating a process of forming a 3D NAND memory according to another embodiment of the present invention. The difference between this embodiment and the previous embodiment is: after forming the second channel hole, before carrying out the sculpture to the step the lateral wall in second channel hole forms the side wall, therefore is carrying out the sculpture to the step for when the slope of step slows down, the side wall can prevent to bring the sculpture damage to second stacked structure, the sacrificial material layer can prevent to bring the sculpture damage to first stacked structure, makes the characteristic dimension in first channel hole and second channel hole can not change, and, when this kind of mode carried out the sculpture, can reduce the sculpture degree of difficulty that the slope of step slowed down to and can adopt multiple etching process to carry out the sculpture to the step. It should be noted that other definitions or descriptions of the same or similar structures in this embodiment as those in the foregoing embodiment are not repeated in this embodiment, and specific reference is made to the definitions or descriptions of corresponding parts in the foregoing embodiment.

Referring to fig. 23, fig. 23 is performed on the basis of fig. 6, a semiconductor substrate 100 is provided, a stacked structure is formed on the semiconductor substrate 100, the stacked structure includes a first stacked structure 111 located on the semiconductor substrate 100 and a second stacked structure 112 located on the first stacked structure 111, each of the first stacked structure 111 and the second stacked structure 112 includes a plurality of sacrificial layers (103, 109) and isolation layers (104, 110) which are alternately stacked, the first stacked structure 111 has a first channel hole 105 penetrating through the thickness of the first stacked structure, the semiconductor substrate 100 at the bottom of the first channel hole 105 has a groove, a semiconductor epitaxial layer 107 is formed in the groove, and the first channel hole 105 on the semiconductor epitaxial layer 107 is filled with a sacrificial material layer 108; a second channel hole 115 penetrating through the thickness of the second stacked structure is formed in the second stacked structure 112, the second channel hole 115 is communicated with the first channel hole 105, the second channel hole 115 is aligned and offset with respect to the first channel hole 105, and a step 10 is formed at the intersection of the first channel hole 105 and the second channel hole 115; a sidewall 202 is formed on the sidewall of the second channel hole 115.

In an embodiment, the forming process of the sidewall spacers 202 is as follows: forming a side wall material layer on the surface of the second stacked structure 112, the surface of the side wall of the second channel hole 115 and the surface of the sacrificial material layer 108; the second stacked structure 112 and the spacer material layer on the surface of the sacrificial material layer 108 are removed by maskless etching, and a spacer 202 is formed on the sidewall of the second channel hole 115.

In an embodiment, the materials of the sidewall 202 and the first stacked structure 111 and the second stacked structure 112 are different, the materials of the sacrificial material layer 108 and the first stacked structure 111 and the second stacked structure 112 are different, and the materials of the sidewall 202 and the sacrificial material layer 108 are different, so that the sidewall 202 remains intact during the subsequent etching back of the sacrificial material layer 108, and when the step 10 is etched, the sidewall 202 and the sacrificial material layer 108 remain intact, the first stacked structure 111 and the second stacked structure 112 are protected, and when the sidewall 202 and the sacrificial material layer 108 are removed, the etching damage to the first stacked structure 111 and the second stacked structure 112 is small.

The sacrificial material layer 108 or the sidewall spacers 202 may be made of polysilicon, amorphous silicon, or amorphous carbon. In this embodiment, the sacrificial material layer 108 is made of polysilicon, and the sidewall 202 is made of amorphous carbon.

Referring to fig. 24, after forming the spacers 202, the sacrificial material layer 108 is etched back to remove a portion of the thickness.

The sacrificial material layer 108 is etched back to a thickness greater than the lateral width of the step.

The etching back is used to remove a portion of the thickness of the sacrificial material layer 108 by wet etching or anisotropic dry etching.

In one embodiment, when the etch-back is a wet etch, the sacrificial material layer 108 on the upper portion of the first channel hole 105 is completely removed.

In an embodiment, an anisotropic dry etching is used to remove a part of the thickness of the sacrificial material layer 108, and only a part of the sacrificial material layer 108 directly under the second channel hole is removed to expose a part of the sidewall of the first channel hole adjacent to the step 10, and the part of the sidewall of the channel hole opposite to the step 10 is still covered by the sacrificial material layer, so as to further protect the first stacked structure from being damaged by the etching.

Referring to fig. 25, after etching back to remove a part of the thickness of the sacrificial material layer 108, the step 10 is etched so that the slope of the step 10 is reduced.

The step 10 is etched by sputtering, dry etching process or wet etching.

Referring to fig. 26, before forming the charge storage layer, the sidewall spacers 202 and the remaining sacrificial material layer 108 are removed (refer to fig. 25).

Referring to fig. 27, after the step 10 is etched, a charge storage layer 116 is formed on sidewalls and bottoms of the first and second channel holes; forming a channel hole sacrificial layer on the charge storage layer 116; sequentially etching the channel hole sacrificial layer 116 and the charge storage layer on the bottom of the first channel hole to form an opening (exposing the surface of the semiconductor epitaxial layer 107); removing the channel hole sacrificial layer; forming a channel layer 120 on a surface of the charge storage layer 116 and in the opening; a filling layer 121 is formed on the channel layer 1120, and the filling layer 121 fills the first channel hole and the second channel hole.

Further comprising, after forming the channel layer 120 or forming the filler layer 121, removing the sacrificial layer in the first stacked structure 111 and the second stacked structure 112 (103/109); control gates are formed at locations corresponding to where the sacrificial layer (103/109) is removed.

FIGS. 28-35 are schematic cross-sectional views illustrating a process of forming a 3D NAND memory according to another embodiment of the present invention. The difference between this embodiment and the foregoing embodiment is: in this embodiment, after the second channel hole is formed, a side wall is formed on the side wall of the second channel hole, and then the sacrificial material layer is removed to expose the first channel hole; the width of the first channel hole is widened by etching the first channel hole, so that the width of the step is reduced, the gradient of the step is reduced, the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole are etched subsequently, when an opening exposing the surface of the semiconductor epitaxial layer is formed, the channel hole sacrificial layer at the step with the reduced gradient has less barrier to plasma, the channel hole sacrificial layer at the step with the reduced gradient is etched and removed less, and the charge storage layer at the step with the reduced gradient is always covered by the channel hole sacrificial layer in the whole etching process for forming the opening so as to protect the charge storage layer at the step, so that the charge storage layer at the step is prevented from being etched or damaged in the process for forming the opening, and the NAND memory is prevented from failing; and the side wall formed by the side wall of the second channel hole is present, so that the characteristic dimension of the second channel hole is not changed when the first channel hole is etched, and the reduction of the width of the step is facilitated while the characteristic dimension of the second channel hole is kept. It should be noted that other definitions or descriptions of the same or similar structures in this embodiment as those in the foregoing embodiment are not repeated in this embodiment, and specific reference is made to the definitions or descriptions of corresponding parts in the foregoing embodiment.

Referring to fig. 28, fig. 28 is performed on the basis of fig. 6, a semiconductor substrate 100 is provided, a stacked structure is formed on the semiconductor substrate 100, the stacked structure includes a first stacked structure 111 located on the semiconductor substrate 100 and a second stacked structure 112 located on the first stacked structure 111, each of the first stacked structure 111 and the second stacked structure 112 includes a plurality of sacrificial layers (103, 109) and isolation layers (104, 110) which are alternately stacked, the first stacked structure 111 has a first channel hole 105 penetrating through the thickness of the first stacked structure, the semiconductor substrate 100 at the bottom of the first channel hole 105 has a groove, a semiconductor epitaxial layer 107 is formed in the groove, and the first channel hole 105 on the semiconductor epitaxial layer 107 is filled with a sacrificial material layer 108; a second channel hole 115 penetrating through the thickness of the second stacked structure is formed in the second stacked structure 112, the second channel hole 115 is communicated with the first channel hole 105, the second channel hole 115 is aligned and offset with respect to the first channel hole 105, and a step 10 is formed at the intersection of the first channel hole 105 and the second channel hole 115; a sidewall 202 is formed on the sidewall of the second channel hole 115.

Referring to fig. 29, after forming the sidewalls 202, the sacrificial material layer 108 (refer to fig. 28) is removed to expose the first channel holes 105.

In this embodiment, all of the sacrificial material layer 108 is removed, and wet etching is adopted to remove the sacrificial material layer 108.

In other embodiments, referring to fig. 30, after forming the sidewall spacers 202, a portion of the sacrificial material layer 108 is removed to expose the sidewall of the first channel hole 105 under the step 10, and a portion of the sidewall of the first channel hole 105 opposite to the step 10 is still covered by the remaining sacrificial material layer 108, which is advantageous in that: referring to fig. 31, when the first channel hole 105 is etched to widen the width of the first channel hole and reduce the width of the step 10, only the sidewall of the first channel hole under the step 10 is etched, and the portion of the sidewall of the first channel hole 105 opposite to the step 10 is not etched, so that the width of the step 10 is reduced, the gradient of the step is reduced, and the subsequent growth of the charge storage layer and the channel hole sacrificial layer is facilitated.

An anisotropic dry etching process, such as a plasma etching process, is used to remove a portion of the sacrificial material layer 108, such that the portion of the sacrificial material layer 108 directly under the second channel hole 115 is removed, and a portion of the sidewall of the first channel hole 105 opposite to the step 10 is still covered by the remaining sacrificial material layer 108.

Referring to fig. 32, fig. 32 is performed on the basis of fig. 29 or fig. 31, and the first channel hole 105 is etched such that the width of the first channel hole 105 is widened, and the width of the step 10 is narrowed.

The first channel hole 105 is etched such that the width of the first channel hole is widened using wet etching or dry etching.

After etching the first channel hole 105, the removing of the sidewall 202 (refer to fig. 30) or the removing of the sidewall 202 and the remaining sacrificial material layer 108 (refer to fig. 31) is further included.

And removing the side walls 202 and/or the sacrificial material layer 108 by wet etching.

Referring to fig. 33, after the width of the step 10 becomes small, a charge storage layer 116 is formed on sidewalls and bottoms of the first and second channel holes 105 and 115; a channel hole sacrificial layer 117 is formed on the charge storage layer 116.

Referring to fig. 34, the channel hole sacrificial layer 117 and the charge storage layer 116 on the bottom of the first channel hole 105 are sequentially etched to form an opening 125 (exposing the surface of the semiconductor epitaxial layer 107).

Referring to fig. 35, a channel layer 120 is formed on a surface of the charge storage layer 116 and in the opening; a filling layer 121 is formed on the channel layer 120, and the filling layer 121 fills the first channel hole and the second channel hole.

Further comprising: after forming the channel layer 120 or forming the filling layer 121, removing the sacrificial layer in the first stack structure 111 and the second stack structure 112 (103/109); control gates are formed at locations corresponding to where the sacrificial layer (103/109) is removed.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A method for forming a 3D NAND memory, comprising:

forming a channel hole sacrificial layer on the charge storage layer;

forming a protective layer on the channel hole sacrificial layer;

and sequentially etching the protective layer, the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole to form an opening, wherein during the etching of the channel hole sacrificial layer on the bottom of the channel hole, the channel hole sacrificial layer on the step on the bottom of the second channel hole is reserved to protect the charge storage layer on the step during the etching of the charge storage layer.

2. The method of forming a 3D NAND memory as claimed in claim 1, wherein the stack structure includes a first stack structure and a second stack structure on the first stack structure, the first and second stack structures each including a plurality of sacrificial layers and isolation layers stacked alternately, the first stack structure having a first channel hole formed therein through a thickness of the first stack structure, the semiconductor substrate at a bottom of the first channel hole having a recess formed therein, the recess having a semiconductor epitaxial layer formed therein; a second channel hole penetrating through the thickness of the second stacking structure is formed in the second stacking structure; the opening exposes a surface of the semiconductor epitaxial layer.

3. The method of forming a 3D NAND memory of claim 1, wherein the channel hole sacrificial layer and the protective layer are of different materials.

4. The method of claim 2, wherein the channel hole sacrificial layer is made of polysilicon, amorphous silicon, or amorphous carbon, and the protective layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or boron nitride.

5. The method of forming a 3D NAND memory of claim 1 wherein the sequentially etching the protective layer, the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole uses an anisotropic dry etch process.

6. The method of claim 5, wherein different etching gases are used to etch the channel hole sacrificial layer and the protection layer, and different etching gases are used to etch the charge storage layer and the channel hole sacrificial layer.

7. The method for forming a 3D NAND memory as claimed in claim 2 or 5, wherein after etching the protective layer on the bottom of the first trench hole, a protective sidewall is formed on the surface of the trench hole sacrificial layer on the sidewalls of the first trench hole and the second trench hole.

8. The method for forming a 3D NAND memory as claimed in claim 7, wherein the protective sidewall spacer and the channel hole sacrificial layer are removed by simultaneous etching when the charge storage layer is etched through, or the protective sidewall spacer and the channel hole sacrificial layer are removed after the opening is formed.

9. The method of forming a 3D NAND memory as claimed in claim 8, wherein the channel layer is formed on a surface of the charge storage layer and in the opening; and forming a filling layer on the channel layer, wherein the filling layer fills the first channel hole and the second channel hole.

10. The method of forming a 3D NAND memory as claimed in claim 9, wherein after forming the channel layer or forming the filling layer, the sacrificial layer in the first stack structure and the second stack structure is removed; and correspondingly forming a control gate at the position of the sacrificial layer.

11. The method of forming a 3D NAND memory of claim 1 wherein the charge storage layer comprises a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.

12. A3D NAND memory, comprising:

a channel hole sacrificial layer on the charge storage layer;

and the protective layer is used for protecting the channel hole sacrificial layer at the bottom of the second channel hole when an opening is formed in the charge storage layer at the bottom of the first channel hole in the subsequent etching process so as to effectively protect the charge storage layer at the step.

13. The 3D NAND memory of claim 12 wherein the stack structure comprises a first stack structure and a second stack structure on the first stack structure, the first and second stack structures each comprising a plurality of alternately stacked sacrificial layers and isolation layers, the first stack structure having a first channel hole therein through a thickness of the first stack structure, the semiconductor substrate at a bottom of the first channel hole having a recess therein, the recess having a semiconductor epitaxial layer formed therein; a second channel hole penetrating through the thickness of the second stacking structure is formed in the second stacking structure; the opening exposes a surface of the semiconductor epitaxial layer.

14. The 3D NAND memory of claim 12 wherein the channel hole sacrificial layer and the protective layer are of different materials.

15. The 3D NAND memory of claim 14 wherein the channel hole sacrificial layer is polysilicon, amorphous silicon or amorphous carbon and the protective layer is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or boron nitride.