CN109801977A - Memory - Google Patents
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- CN109801977A CN109801977A CN201910088556.3A CN201910088556A CN109801977A CN 109801977 A CN109801977 A CN 109801977A CN 201910088556 A CN201910088556 A CN 201910088556A CN 109801977 A CN109801977 A CN 109801977A
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- 230000015654 memory Effects 0.000 title claims abstract description 118
- 238000003860 storage Methods 0.000 claims abstract description 59
- 230000007547 defect Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000010287 polarization Effects 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 66
- 230000007306 turnover Effects 0.000 claims description 16
- 229910003134 ZrOx Inorganic materials 0.000 claims description 5
- 230000008901 benefit Effects 0.000 abstract description 8
- 230000006870 function Effects 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 155
- 230000004927 fusion Effects 0.000 description 39
- 210000004027 cell Anatomy 0.000 description 32
- 230000005621 ferroelectricity Effects 0.000 description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 238000000034 method Methods 0.000 description 23
- 238000013528 artificial neural network Methods 0.000 description 15
- 229910052681 coesite Inorganic materials 0.000 description 14
- 229910052906 cristobalite Inorganic materials 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 14
- 229910052682 stishovite Inorganic materials 0.000 description 14
- 229910052905 tridymite Inorganic materials 0.000 description 14
- 229910017107 AlOx Inorganic materials 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 230000005611 electricity Effects 0.000 description 8
- 229910004541 SiN Inorganic materials 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 230000014759 maintenance of location Effects 0.000 description 6
- 230000001276 controlling effect Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052688 Gadolinium Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005283 ground state Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 241000894007 species Species 0.000 description 2
- 229910052712 strontium Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052727 yttrium Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 210000005036 nerve Anatomy 0.000 description 1
- 210000004218 nerve net Anatomy 0.000 description 1
- 210000002569 neuron Anatomy 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010977 unit operation Methods 0.000 description 1
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Abstract
The disclosure provides a kind of memory, including multiple memory cells, wherein the memory cell includes: bulk substrate；Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；Deep energy level defect dielectric layer, is located above the channel region；Grid is located on deep energy level defect dielectric layer.The advantages of memory of the disclosure can enable storage unit work in the case where charge capturees mode and polarization overturning mode by the raw energy level defective media layer of offer, and therefore, which has both the function of DRAM and NAND, merge the two.
Description
Technical field
This disclosure relates to memory area, further to a kind of memory comprising deep energy level defect dielectric layer.
Background technique
Traditional DRAM (dynamic random access memory) uses 1 T1C (1Transistor-1Capacitor, 1 crystal
Manage -1 capacitor) memory cell structure, when being connected to the wordline gating of transistor gate, transistor selection can be from position
The position information of storage on the capacitor is read on line；Traditional NAND then uses floating grid (floating gate) or charge
Capture structure；They are one is dynamic random storage is realized, one is non-volatile memories are realized, thus these two types of storages
The preparation process difference of device is huge, can not be inner integrated simultaneously in a on piece chip (SOC), therefore can not merge two kinds of storages
The advantages of device, so that the memory capacity and calculated performance of SOC chip are restricted.
In neural network, traditional cynapse device both ends memristor or three end transistor simulated implementations, cynapse device are general
It is connected with each other using parallel NOR structure, after Weight Training, completes operation by the way of electric current convergence.Such knot
The problems such as that there are operation electric currents is big for structure, and power consumption training power consumption is big, makes and line number is limited.
Summary of the invention
(1) technical problems to be solved
In view of this, the disclosure is designed to provide a kind of memory, the advantages of to merge above two memory.
(2) technical solution
According to the one side of the disclosure, a kind of memory, including multiple memory cells are provided, wherein the memory
Unit includes:
Bulk substrate；
Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；
Deep energy level defect dielectric layer, is located above the channel region；
Grid is located on deep energy level defect dielectric layer.
According to another aspect of the present disclosure, a kind of memory, including multiple memory cells are provided, wherein the storage
Device unit includes:
Bulk substrate；
Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；
First boundary layer is located on channel；
Deep energy level defect dielectric layer is located on the first boundary layer；
Grid is located on deep energy level defect dielectric layer.
According to the another further aspect of the disclosure, a kind of memory, including multiple memory cells are provided, wherein the storage
Device unit includes:
Bulk substrate；
Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；
First boundary layer is located on channel；
Deep energy level defect dielectric layer is located on the first boundary layer；
Second interface layer is located on deep energy level defect dielectric layer；
Grid is located on second interface layer.
In a further embodiment, the material of the deep energy level defect dielectric layer is the HfO of dopingx, ZrOx, PZT,
BFO or BST.
In a further embodiment, deep energy level defect dielectric layer is ferroelectric material layer.
It in a further embodiment, further include grid voltage controller, which is electrically connected to the storage
The grid of unit, for controlling grid voltage work in first voltage, the first voltage is sent out less than deep energy level defect dielectric layer
The turnover voltage of raw polarization overturning.
In a further embodiment, the multiple memory cell forms 3D stacked structure.
(3) beneficial effect
The memory of the disclosure enables storage unit to work in the case where charge capturees mode and polarization overturning mode, therefore,
The advantages of memory has both the function of DRAM and NAND, has merged the two.
The grid voltage controller of the disclosure can control grid voltage work in first voltage and second voltage, so as to deposit
Reservoir work respectively charge prisoner mode and polarization overturning mode, have high efficiency and flexibility.
Detailed description of the invention
Fig. 1 is the schematic cross-section of memory cell in a kind of pattern of fusion memory of the embodiment of the present disclosure.
Fig. 2 is the schematic cross-section of memory cell in another pattern of fusion memory of the embodiment of the present disclosure.
Fig. 3 is the schematic cross-section of memory cell in another pattern of fusion memory of the embodiment of the present disclosure.
Fig. 4 is the schematic illustration for the pattern of fusion memory that the disclosure is implemented.
Fig. 5 is the schematic diagram of the wiring method for pattern of fusion memory of the embodiment of the present disclosure.
Fig. 6 is the schematic diagram of the method for deleting for pattern of fusion memory of the embodiment of the present disclosure.
Fig. 7 A, 7B and 7C are respectively the voltage scanning under the pattern of fusion memory electric charge capture mode of the embodiment of the present disclosure
Curve graph, write-in erasing schematic diagram and reading schematic diagram.
Fig. 8 A, 8B and 8C are respectively the monocycle behaviour under the pattern of fusion memory ferroelectricity inverted pattern of the embodiment of the present disclosure
Make, multicycle operation, and write-in erasing schematic diagram.
Fig. 9 A-9C is respectively the schematic cross-section of the storage unit of three kinds of memories of the embodiment of the present disclosure.
Figure 10 is a kind of schematic illustration of neural network computing device.
Figure 11 is that neuron constitutes schematic diagram.
Figure 12 is the schematic illustration of the neural network arithmetic system of the embodiment of the present disclosure.
Figure 13 is the schematic diagram of the storage unit in the neural network arithmetic system in Figure 12.
Figure 14 is the block diagram of the neural network computing system of the embodiment of the present disclosure.
Specific embodiment
For the purposes, technical schemes and advantages of the disclosure are more clearly understood, below in conjunction with specific embodiment, and join
According to attached drawing, the disclosure is described in further detail.Hereinafter, it will thus provide some embodiments are to be described in detail the disclosure
Embodiment.The advantages of disclosure and effect will be more significant by disclosure following the description.Explanation is appended attached herein
Figure simplified and used as illustrating.Component count, shape and size shown in the drawings can be repaired according to actual conditions
Change, and the configuration of component is likely more complexity.Otherwise practice or application can also be carried out in the disclosure, and without departing from this
Under conditions of spirit and scope defined in open, various change and adjustment can be carried out.
In the disclosure " on ", " top ", " under " etc. terms refer to the half in memory unless stated otherwise
Conductor layer structure is located at the top of the other half conductor layer structure directly contacted, or the lower part directly contacted, that is to say, that adopts
Two semiconductor layers are directly contact when being described with " on " or " under ", for example, " ferroelectric layer, be located at channel region it
On " indicate that ferroelectric layer is located at the top that channel region directly contacts；In the disclosure signified " block ", referring to participate in being formed
The substrate or trap material of one or more storage units.
According to the one side of the embodiment of the present disclosure, a kind of pattern of fusion memory, including multiple storage units are provided, respectively deposited
Include ferroelectric layer in storage unit, storage unit is enable to work in the case where charge capturees mode and polarization overturning mode, therefore,
The advantages of memory has both the function of DRAM and NAND, has merged the two.
Fig. 1 is the schematic cross-section of memory cell in a kind of pattern of fusion memory of the embodiment of the present disclosure.It is mentioned in Fig. 1
For a kind of pattern of fusion memory, including multiple memory cells 10, wherein memory cell 10 includes: bulk substrate；Block
Source electrode and drain electrode above substrate and the channel region extended between source electrode and drain electrode region；Ferroelectric layer, be located at channel region it
On；And grid, it is located on ferroelectric layer.
Memory cell in the embodiment includes ferroelectric layer of the channel region on, and the two directly contacts, by adjusting
It is applied to the voltage swing of grid, ferroelectric layer can be enable to work in the case where charge capturees mode and polarization overturning mode.
Wherein, the ferroelectric layer in Fig. 1 uses ferroelectric layer as gate medium between the gate and channel.The memory can be with work
Make in both of which: on the one hand doing charge storage using lattice defect a large amount of in ferroelectric material, allow to work in charge
Capture mode, by capturing and discharging charge come storing data；On the other hand it can also work in ferroelectricity inverted pattern, pass through
Polarization overturning carrys out storing data.
In some embodiments, the material of the ferroelectric layer can be the HfO of dopingx, ZrOx, PZT, BFO or BST, than
It is more preferably HfOx；Dopant species can be Si, Zr, Hf, Al, Y, Gd, La, Sr, Ti and/or N etc., preferably be doped to
Zr；Doping content is between 10%~75%
In some embodiments, thickness 3nm~10nm of the ferroelectric layer；The length of channel is 5nm~200nm, channel
Width is 5nm~500nm.
In some embodiments, above-mentioned block, source electrode, drain and gate can be according to existing storage unit setting sides
Formula is configured, and corresponding preparation process is also referred to existing process flow and participation is executed.
It in some embodiments, further include control circuit in pattern of fusion memory, and including being connected to each storage unit
Grid control sub-circuit, for individually applying specific first voltage to grid, the ferroelectric layer below grid is made to capture electricity
Son changes threshold voltage during charge or discharge.The control circuit also can integrate the read/write circuit in memory
In, corresponding voltage pulse value is controlled during read-write.Read/write circuit is according to the read write command of CPU, content with the first electricity
The accessed storage unit of pressure write-in；Or information is read from accessed storage unit.The absolute value of the first voltage is answered
The turnover voltage value needed for polarization reversal occurs for the ferroelectric material being less than in ferroelectric layer, with the rising of first voltage, ferroelectricity
The electronics of layer capture is more, and the threshold voltage of storage unit can gradually rise.
In some embodiments, which is also used to individually apply specific second voltage to grid, keeps grid electric
Lotus realizes polarization overturning, changes threshold voltage accordingly, which is gradually reduced with the increase of second voltage.It reads
Read write command of the write circuit according to CPU, the storage unit that content is accessed with second voltage write-in；Or from accessed
Storage unit reads information.Polarization reversal institute occurs for the ferroelectric material that the absolute value of the second voltage should be greater than in ferroelectric layer
The turnover voltage value needed.
In some embodiments, according to the requirement of memory product, source area and drain region can keep floating state, or
Person according to the working condition of memory (write-in, erasing or reading) be adjusted to corresponding state (positive voltage, negative voltage or
Ground connection).Specific adjustment mode is referred to following wiring method embodiments for pattern of fusion memory.
In some embodiments, in a specific program, above-mentioned control circuit can control the voltage for being applied to grid
In first voltage or second voltage, that is, can occur two kinds of voltage modes simultaneously in a process, can send out in this way
Wave the respective advantage of the two of DRAM and tradition flash.
In some embodiments, wordline known in the art, position is can be used in the pattern of fusion memory of the embodiment of the present disclosure
Memory cell array is arranged in line and source electrode line architecture.Wordline is coupled to the grid of corresponding storage unit, and bit line is coupled to phase
The storage unit drain electrode answered, and source electrode line is coupled to corresponding Fe cell source.
In some embodiments, the pattern of fusion memory of the embodiment of the present disclosure further includes reading circuit, for reading each storage
The information of unit storage can be read respectively under polarization overturning or ferroelectric layer trapped electron mode, lesser by applying
Read-out voltage (such as 0.6V), to read the information in storage unit.
Fig. 2 is the schematic cross-section of memory cell in another pattern of fusion memory of the embodiment of the present disclosure.In Fig. 2
There is provided a kind of pattern of fusion memory, including multiple memory cells 20, wherein memory cell 20 includes: bulk substrate；Block
Source electrode and drain electrode above body substrate and the channel region extended between source electrode and drain electrode region；First boundary layer is located at ditch
On road；Ferroelectric layer is located on the first boundary layer；Grid is located on ferroelectric layer.
It is substantially similar in memory unit and Fig. 1 in the embodiment, the difference is that only in ferroelectric layer and
The first boundary layer is provided between channel region.First boundary layer can be used for controlling the growth of ferroelectric material, such as crystal lattice orientation
Control or defect distribution.
In some embodiments, the material of first boundary layer can be SiO2, SiN, SiON, AlOx, TiO2Or
HfOx, preferably, the first interlayer materials can be SiO2；The thickness of first boundary layer can be 0.3nm~3nm；
The material of first boundary layer is adjusted according to the ferroelectricity layer material that need to be grown, such as when ferroelectricity layer material is HfOxWhen, it is right
The first interlayer materials answered can be SiON；Such as when ferroelectricity layer material is SBT, corresponding first interlayer materials can
To be HfOxOr AlOx。
Fig. 3 is the schematic cross-section of memory cell in another pattern of fusion memory of the embodiment of the present disclosure.In Fig. 3
There is provided a kind of pattern of fusion memory, including multiple memory cells 30, wherein memory cell 30 includes: bulk substrate；Block
Source electrode and drain electrode above body substrate and the channel region extended between source electrode and drain electrode region；First boundary layer is located at ditch
On road；Ferroelectric layer is located on the first boundary layer；Second interface layer is located on ferroelectric layer；Grid is located at second contact surface
On layer.
It is substantially similar in memory unit and Fig. 1 in the embodiment, the difference is that only in ferroelectric layer and
It is provided with the first boundary layer between channel region, second interface layer is provided between ferroelectric layer and grid.First boundary layer can be with
For controlling the growth of ferroelectric material, such as crystal lattice orientation control or defect distribution.The second interface layer is for completely cutting off metal gate
Phase counterdiffusion and interface damage between accumulation layer.
In some embodiments, the material of first boundary layer can be SiO2, SiN, SiON, AlOx, TiO2, HfOxOr
Person's a combination thereof, preferably, the first interlayer materials can be SiO2；The thickness of first boundary layer can for 0.3nm~
3nm；The material of first boundary layer is adjusted according to the ferroelectricity layer material that need to be grown, such as when ferroelectricity layer material is HfOx
When, corresponding first interlayer materials can be SiON；Such as when ferroelectricity layer material is SBT or PZT, corresponding first boundary
Surface material can be HfOxOr AOx。
In some embodiments, which can be SiO2, SiN, SiON, AlOx, TiO2Or HfOx。
Preferably, second contact surface layer material can be AlOx；The thickness of the second interface layer can be 1nm~10nm；Second boundary
The material of surface layer is adjusted according to ferroelectric layer and grid material, such as when ferroelectricity layer material is HfOxWhen, corresponding
Second interface layer material can be SiO2/SiN/SiO2Lamination；Such as when ferroelectricity layer material is SBT or PZT, corresponding first
Interlayer materials can be HfOxOr AlOx。
The working principle of storage unit is referred to shown in Fig. 4 in the pattern of fusion memory of above-described embodiment.Fig. 4 is this
The schematic illustration of the open pattern of fusion memory implemented, as shown in figure 4, under charge-trapping mode, as grid voltage VGBy
It is cumulative to add, threshold voltage VTAlso it gradually increases, in A point, scanning voltage is -5V, corresponding threshold voltage VTAbout -1.5V；
When scanning voltage is gradually increasing and is changed into positive value, such as B point, scanning voltage 1V, at this time threshold voltage VTAbout -1.1V,
Compared with when A point, threshold value increases, similar such as C and D point, is in charge-trapping mode；When voltage rises to 4V, the voltage
More than ferroelectricity turnover voltage is generated in ferroelectric layer, ferroelectricity overturning, threshold voltage decreasing, when being further added by scanning voltage occur at this time
When, threshold voltage VTGradually decline, enters ferroelectricity inverted pattern at this time.
According to the another aspect of the embodiment of the present disclosure, a kind of wiring method for pattern of fusion memory is also provided, this melts
Conjunction property memory includes multiple storage units, each storage unit bulk substrate；Source electrode, drain electrode and source drain above substrate
Between the ferroelectric layer and grid that stack on the channel region and channel region that extend.It should be noted that channel region here with
Other semiconductor layers can not included between ferroelectric layer, may include the first above-mentioned boundary layer yet, and ferroelectric layer and channel it
Between may include second interface layer or both directly contact, so storage unit here can be any implementation of Fig. 1-3
The structure of the example description.The present embodiment pattern of fusion storage wiring method include:
Apply first voltage between the grid and block of the storage unit of at least one, first voltage is less than ferroelectric layer
The turnover voltage of polarization overturning occurs；And it will
Source electrode and grid are respectively set to ground connection or are floating state.
Fig. 5 is the schematic diagram of the wiring method for pattern of fusion memory of the embodiment of the present disclosure.In Fig. 5 shown in 51, point
Zero potential (as be grounded) is not kept at the source electrode and drain electrode end of storage unit or being floating state, block keeps zero potential (such as
Ground connection), in addition, applying first voltage in gate terminal, which is less than the turnover voltage that ferroelectricity turns over polarization overturning.It should
Mode of operation can refer to the electric charge capture mode in Fig. 4, complete in low-voltage area (be less than turnover voltage), by applying the
One voltage causes electronics charge and discharge, and so as to cause the variation of threshold voltage, the change procedure is very fast, can reach 20ns grades of volumes
Cheng Sudu is compared than traditional DRAM, and faster, and voltage is relatively low for speed.
With reference to Fig. 7 A-7C, as shown in Figure 7 A, when electric field is applied to storage unit (namely containing the crystalline substance of ferroelectric layer
Body pipe), the central atom in crystalline solid in ferroelectric layer stays in lower state position, after removing electric field, center along electric field
Atom is kept in lower state；When applying first voltage, without overturning, (first voltage is located at the voltage zone of non-toggle to ferroelectric domain
Between).As shown in Figure 7 B, can control positive first voltage is 3V, burst length 20nm, should generate changes of threshold in the process,
Realize the write-in of data；By compared with existing DRAM, such as Fig. 7 B and Fig. 7 C it is found that it passes through 1012Above circulation,
Threshold voltage has at 85 DEG C 1000 seconds or more retention times still less than traditional DRAM, and speed is suitable with DRAM, protects
Hold the DRAM that characteristic is substantially better than the prior art.
In some embodiments, the wiring method of pattern of fusion memory can also include the writing mode as illustrated in Fig. 5
52, apply second voltage between the grid and block of the storage unit of at least one, the second voltage is sent out greater than ferroelectric layer
The turnover voltage of raw polarization overturning；And source electrode is ground state, grid is positive voltage status.The mode of operation can refer in Fig. 4
Ferroelectricity inverted pattern, completed in high voltage region (be greater than turnover voltage), by applying second voltage, ferroelectric domain caused to be turned over
Turn, the program voltage of the process is still less than traditional FLASH, and speed is also very fast, can reach 20ns grades of program speeds.
In some embodiments, for the application of second voltage, with reference to shown in Fig. 8 A-8C, it is single that electric field is applied to storage
First (namely containing the transistor of ferroelectric layer), when a second voltage is applied, (second voltage is greater than overturning electricity to ferroelectricity periodical poling
Pressure).As shown in Figure 8 B, can control positive second voltage is 6V, burst length 20nm, should generate changes of threshold in the process,
It realizes the write-in of data, while generating ferroelectric domain overturning；By compared with existing FLASH, such as Fig. 8 B and Fig. 8 C it is found that
It passes through multiple circulation, and threshold voltage is still less than traditional FLASH, and the retention time, and speed is suitable with FLASH, programs
Voltage is much smaller than tradition FLASH.
In some embodiments, the wiring method of the embodiment further includes being read out to the data of write storage unit,
Such as shown in Fig. 7 C, lesser reading voltage (such as -0.7V) can be applied, realize reading data, threshold voltage is not sent out at this time
Changing.
Fig. 6 is the schematic diagram of the method for deleting for pattern of fusion memory of the embodiment of the present disclosure.In Fig. 6 shown in 61, point
Zero potential (as be grounded) is not kept at the source electrode and drain electrode end of storage unit or being floating state, block keeps zero potential (such as
Ground connection), in addition, applying the tertiary voltage of negative value in gate terminal, the absolute value of the tertiary voltage is less than ferroelectricity and turns over polarization overturning
Turnover voltage.The mode of operation can refer to the electric charge capture mode in Fig. 4, and in low-voltage area, (being less than turnover voltage) is complete
At, by apply tertiary voltage, cause electronics charge and discharge, so as to cause the variation of threshold voltage, the change procedure is very fast, can
Reach 20ns grades of erasing speeds, compared than traditional DRAM, faster, and voltage is relatively low for speed.
With reference to Fig. 7 A-7C, as shown in Figure 7 A, when electric field is applied to storage unit (namely containing the crystalline substance of ferroelectric layer
Body pipe), the central atom in crystalline solid in ferroelectric layer stays in lower state position, after removing electric field, center along electric field
Atom is kept in lower state；When applying tertiary voltage, without reversion, (tertiary voltage is located at the voltage zone of non-toggle to ferroelectric domain
Between).As shown in Figure 7 B, can control positive tertiary voltage is -4V, burst length 20nm, should generate in the process threshold value and become
Change, that is, realizes the erasing of data；By compared with existing DRAM, such as Fig. 7 B and Fig. 7 C it is found that it passes through 1012Above follows
Ring, threshold voltage is still less than traditional DRAM, and 85 degree of 1000 seconds or more retention times, and speed is suitable with DRAM, keeps
Characteristic is substantially better than traditional DRAM.
In some embodiments, the method for deleting of pattern of fusion memory can also include the erasing side such as 62 signals in Fig. 6
Formula, applies the 4th voltage between the grid and block of the storage unit of at least one, and the 4th absolute value of voltage is greater than iron
The turnover voltage of polarization overturning occurs for electric layer；And block is no-voltage (such as ground state), grid is negative voltage status, drain electrode
For ground connection or floating state, source electrode is positive voltage status.The mode of operation can refer to the ferroelectricity inverted pattern in Fig. 4,
High voltage region (being greater than turnover voltage) is completed, and by applying the 4th voltage, causes iron cell farmland to overturn, the erasing electricity of the process
Pressure is still less than traditional FLASH, and speed is also very fast, can reach 20ns grades of erasing speeds.
In some embodiments, for the application of the 4th voltage, with reference to shown in Fig. 8 A-8C, it is single that electric field is applied to storage
First (namely containing the transistor of ferroelectric layer), when applying four voltage, (the 4th absolute value of voltage is greater than to be turned over ferroelectricity periodical poling
Turn voltage).As shown in Figure 8 B, can control the 4th reversed voltage is -6V, burst length 20nm, should generate threshold value in the process
Variation, that is, realize the erasing of data, while generating ferroelectric domain overturning；By compared with existing FLASH, such as Fig. 8 B and Fig. 8 C
It is found that it passes through multiple circulation, threshold voltage is still less than traditional FLASH, and retention time, speed and FLASH phase
When erasing voltage is much smaller than tradition FLASH.
According to the embodiment of the present disclosure in another aspect, providing a kind of memory, which includes multiple storage units,
Include deep energy level defect dielectric layer in each storage unit, storage unit is enable to work under charge prisoner's mode, it therefore, should
Memory has the function of DRAM, while operating voltage much smaller than tradition DRAM, and stores fast with erasing speed.
Fig. 9 A is the schematic cross-section of memory cell in a kind of pattern of fusion memory of the embodiment of the present disclosure.In Fig. 9 A
There is provided a kind of pattern of fusion memory, including multiple memory cells 91, wherein memory cell 10 includes: bulk substrate；Block
Source electrode and drain electrode above body substrate and the channel region extended between source electrode and drain electrode region；Deep energy level defect dielectric layer,
It is located above the channel region；And grid, it is located on deep energy level defect dielectric layer.
Memory cell in the embodiment includes deep energy level defect dielectric layer of the channel region on, and the two directly connects
Touching can enable deep energy level defect dielectric layer capture mode and pole in charge by adjusting the voltage swing for being applied to grid
Change and works under overturning mode.
Wherein, the deep energy level defect dielectric layer in Fig. 9 A use between the gate and channel deep energy level defect dielectric layer as
Gate medium.The memory can use a large amount of lattice defect in deep energy level defect material and do charge storage, allow to work
In electric charge capture mode, by capturing and discharging charge come storing data.
Signified deep energy level defect dielectric layer refers to the dielectric layer of charge trap energy level 1eV or more in the embodiment of the present disclosure
Material, such as SiN, ferroelectric material etc..
In some embodiments, the material of the ferroelectric layer can be the HfO of dopingx, ZrOx, PZT, BFO or BST, than
It is more preferably HfOx；Dopant species can be Si, Zr, Hf, Al, Y, Gd, La, Sr, Ti and/or N etc., preferably be doped to
Zr；Doping content is between 10%~75%.
In some embodiments, thickness 3nm~10nm of the ferroelectric layer；The length of channel is 5nm~200nm, channel
Width is 5nm~500nm.
In some embodiments, above-mentioned block, source electrode, drain and gate can be according to existing storage unit setting sides
Formula is configured, and corresponding preparation process is also referred to existing process flow and participation is executed.
It in some embodiments, further include control circuit in pattern of fusion memory, and including being connected to each storage unit
Grid control sub-circuit for individually applying specific first voltage to grid make the deep energy level defect medium below grid
Layer trapped electron, changes threshold voltage during charge or discharge.The control circuit also can integrate the reading in memory
In write circuit, corresponding voltage pulse value is controlled during read-write.Read/write circuit according to the read write command of CPU, content with
The accessed storage unit of first voltage write-in；Or information is read from accessed storage unit.The first voltage it is exhausted
Turnover voltage value needed for polarization reversal occurs for the deep energy level defect material in deep energy level defect dielectric layer should be less than to value,
With the rising of first voltage, the electronics of deep energy level defect dielectric layer capture is more, the threshold voltage of storage unit can gradually on
It rises.
In some embodiments, according to the requirement of memory product, source area and drain region can keep floating state, or
Person according to the working condition of memory (write-in, erasing or reading) be adjusted to corresponding state (positive voltage, negative voltage or
Ground connection).Specific adjustment mode is referred to the embodiment in the above-mentioned wiring method for pattern of fusion memory.
In some embodiments, wordline known in the art, position is can be used in the pattern of fusion memory of the embodiment of the present disclosure
Memory cell array is arranged in line and source electrode line architecture.Wordline is coupled to the grid of corresponding storage unit, and bit line is coupled to phase
The storage unit drain electrode answered, and source electrode line is coupled to corresponding ferroelectric storage cell source electrode.
In some embodiments, the pattern of fusion memory of the embodiment of the present disclosure further includes reading circuit, for reading each storage
The information of unit storage can be read respectively in deep energy level defect polarization overturning or deep energy level defect dielectric layer trapped electron
Under mode, by applying lesser read-out voltage (such as -0.7V, 0V or 0.7V), to read the information in storage unit.
Fig. 9 B is the schematic cross-section of memory cell in another pattern of fusion memory of the embodiment of the present disclosure.Fig. 9 B
In a kind of pattern of fusion memory, including multiple memory cells 92 are provided, wherein memory cell 92 includes: bulk substrate；
Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；First boundary layer, is located at
On channel；Deep energy level defect dielectric layer is located on the first boundary layer；Grid is located on deep energy level defect dielectric layer.
Memory unit in the embodiment with it is substantially similar in Fig. 9 A, the difference is that only in deep energy level
The first boundary layer is provided between defective media layer and channel region.First boundary layer can be used for controlling deep energy level defect material
The growth of material, such as crystal lattice orientation control or defect distribution.
In some embodiments, the material of first boundary layer can be SiO2, SiN, SiON, AlOx, TiO2, HfOxOr
Person's a combination thereof, preferably, the first interlayer materials can be SiO2；The thickness of first boundary layer can for 0.3nm~
3nm；The material of first boundary layer is adjusted according to the ferroelectricity layer material that need to be grown, such as when ferroelectricity layer material is HfOx
When, corresponding first interlayer materials can be SiON；Such as when ferroelectricity layer material is SBT or PZT, corresponding first boundary
Surface material can be HfOxOr AlOx。
Fig. 9 C is the schematic cross-section of memory cell in another pattern of fusion memory of the embodiment of the present disclosure.Fig. 9 C
In a kind of pattern of fusion memory, including multiple memory cells 93 are provided, wherein memory cell 30 includes: bulk substrate；
Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；First boundary layer, is located at
On channel；Deep energy level defect dielectric layer is located on the first boundary layer；Second interface layer is located at deep energy level defect dielectric layer
On；Grid is located on second interface layer.
Memory unit in the embodiment with it is substantially similar in Fig. 9 A, the difference is that only in deep energy level
It is provided with the first boundary layer between defective media layer and channel region, is provided with second between deep energy level defect dielectric layer and grid
Boundary layer.First boundary layer can be used for controlling the growth of deep energy level defect material, such as crystal lattice orientation control or defect point
Cloth.The second interface layer is used for phase counterdiffusion and the interface damage completely cut off between metal gate and accumulation layer.
In some embodiments, the material of first boundary layer can be SiO2, SiN, SiON, AlOx, TiO2, HfOxOr
Person's a combination thereof, preferably, the first interlayer materials can be SiO2；The thickness of first boundary layer can for 0.3nm~
3nm；The material of first boundary layer is adjusted according to the ferroelectricity layer material that need to be grown, such as when ferroelectricity layer material is HfOx
When, corresponding first interlayer materials can be SiON；Such as when ferroelectricity layer material is SBT or PZT, corresponding first boundary
Surface material can be HfOxOr AlOx。
In some embodiments, which can be SiO2, SiN, SiON, AlOx, TiO2Or HfOx。
Preferably, second contact surface layer material can be AlOx；The thickness of the second interface layer can be 1nm~10nm；Second boundary
The material of surface layer is adjusted according to ferroelectric layer and grid material, such as when ferroelectricity layer material is HfOxWhen, corresponding
Second interface layer material can be SiO2/SiN/SiO2Lamination；Such as when ferroelectricity layer material is SBT or PZT, corresponding first
Interlayer materials can be HfOxOr AlOx。
The working principle of storage unit is referred to charge shown in Fig. 4 and catches in the pattern of fusion memory of above-described embodiment
Catch mode part.Fig. 4 is the schematic illustration for the pattern of fusion memory that the disclosure is implemented, as shown in figure 4, in charge-trapping mould
Under formula, as grid voltage VGIt gradually increases, threshold voltage VTAlso it gradually increases, in A point, scanning voltage is -5V, corresponding threshold
Threshold voltage VTAbout -1.5V；When scanning voltage is gradually increasing and is changed into positive value, such as B point, scanning voltage 1V, threshold at this time
Threshold voltage VTAbout -1.1V, when A point compared with, threshold value increases, similar such as C and D point, is in charge-trapping mode.
According to the content of the another embodiment of the disclosure, a kind of neural network computing system is provided, wherein include:
Operation array, including arithmetic element, each arithmetic element include: under source terminal, drain electrode end and grid and grid
The threshold voltage adjustment layer of side；
The grid of each column arithmetic element of operation array is connected together, and each column according to threshold voltage adjustment layer for adjusting
Threshold voltage to determine weight；
Threshold voltage adjustment layer is ferroelectric layer.
Firstly, as shown in Figure 10, in a kind of neural network computing device, in neural network, traditional cynapse device both ends
Memristor or three end transistor simulated implementations, cynapse device are generally connected with each other using parallel NOR structure, are instructed by weight
After white silk, operation is completed by the way of electric current convergence.In conjunction with shown in Figure 10 and Figure 11, the current value of output end Y is input terminal
Voltage value Y=X × G of X multiplied by the weight (conductance) of respective quadrature fork point cynapse summing value
As shown in Figure 10, electric current caused by each endpoint is in terms of 10uA, and input X is maximum and line number is about hundreds of
Magnitude (summarizes place about several mA of the end Y current maxima), and for electric current caused by each endpoint in terms of 1uA, input X is maximum parallel
The problem of number about thousands of magnitudes, this connection type is that trained power consumption is big, and line number is limited.There is operation electricity in the class formation
The problems such as stream is big, and power consumption training power consumption is big, makes and line number is limited.
Based on above statement, as shown in figure 12, the neural network computing system that the embodiment of the present disclosure proposes, including operation
Array, the arithmetic element that wherein array summarizes includes threshold voltage adjustment layer, which is ferroelectric layer.
As shown in figure 13, operation array includes arithmetic element, and each arithmetic element includes: source terminal, drain electrode end and grid,
And threshold voltage adjustment layer below grid and the channel region extended between source electrode and drain electrode region, the threshold voltage
Adjustment layer is located above channel region；The grid of each column arithmetic element of operation array is connected together, and each column are for according to threshold value electricity
Press the threshold voltage of adjustment layer adjustment to adjust weight；Threshold voltage adjustment layer is ferroelectric layer.It is three end threshold values shown in Figure 13
Regulate and control cynapse device, threshold voltage is regulated and controled by modulating layer, regulates and controls source and drain resistance, in neural network
Cynapse.
In Figure 12, mutually interconnected in series between the arithmetic element and arithmetic element (cynapse and cynapse) of each row.Its
In, X is an input terminal, and the training of weight realizes that electric current when training is mainly the end Gate by applying voltage on the end X
Leakage current (pA magnitude), small power consumption；It optionally, can for the determination of the threshold voltage of the arithmetic element of the line n m column of setting
To apply voltage simultaneously in the line n with array by arranging simultaneously in the m of input terminal X, i.e., with the Joint regulation operation list
The threshold voltage of member realizes the weight input of specific ranks.After training, by applying a fixed electricity on every line
I is flowed, voltage value V is readn, VnSize and the concatenated cynapse resistance value of every row and directly proportional.The current value when structure is read
For a steady state value, and line number is unrestricted, is conducive to construct ultra-large neural network.
In above-mentioned formula, VnIndicate total output voltage of line n, i value is 1 to m, RmIndicate the electricity of line n m column
Stream, β are the mutual conductance of transistor；Xm is the input (input value corresponding to neural network) of the gate terminal of m column, VthmFor m
The threshold voltage of column line n arithmetic element.
In some embodiments, the grid of each column of above-mentioned operation array is for inputting to operation values, the operation array
The arithmetic element of every row be serially connected, for exporting the output valve of the arithmetic element of every row respectively after operation.
In some embodiments, the arithmetic element of every row is also serially connected with summing circuit, for each unit operation result into
Row adduction forms output voltage values.Namely to output i × R of drain electrode end each in above-mentioned formulamIt sums up, finds out Vn.
In some embodiments, the summing circuit rear end of every row further includes analog to digital conversion circuit, for by the output of each row
Voltage value is converted to the output valve of corresponding digital signals.
In some embodiments, the ferroelectricity layer material is HfOx, ZrOx, PZT, BFO or the BST of doping.
In some embodiments, each arithmetic element in the operation array is constituted using 3D stack manner.
In some embodiments, the absolute value of voltage for being applied to each arithmetic element grid is configured to be greater than ferroelectric layer
The turnover voltage of polarization overturning occurs.
Figure 14 is the block diagram of the neural network computing system of the embodiment of the present disclosure.As shown in figure 14, typical nerve net
Network arithmetic system 1400 may include operation array 1401, can also include control circuit 1402 and reading circuit 1403,
Middle control circuit 1402 can control operation array and carry out the input of arithmetic element weight and the training adjustment of weight in array
(can pass through the grid voltage and/or arithmetic element voltage of the row of control arithmetic element column), control carries out nerve
Neural network computing is read in network operations (by inputting the corresponding voltage of input value in neural network at the end X), and control
As a result (read electric current in source terminal input one, finally export total current/voltage in serial each row, then by summing circuit and
Analog to digital conversion circuit determines corresponding numerical value and exports to reading circuit 1403).
Although the disclosure can describe many details, these are not construed as to claimed invention
Or can the range of claimed invention limited, but the description of the specific characteristic as specific embodiment.Independent
Certain features described in the disclosure shelves of the context of embodiment can also combine realization in a single embodiment.On the contrary
Ground, the various features described in the context of single embodiment, can also be in various embodiments individually or with any
Suitable sub-portfolio is realized.Furthermore although effect and even initially can be described feature as in certain combinations above
Scope of the claims described in, but one or more features can be deleted from required combination in some cases,
And claimed combination can be for the variation of sub-portfolio or sub-portfolio.Similarly, although in the accompanying drawings with specific time
Sequence describes to operate, but this is understood not to this and is required the certain order shown in or order in order to execute this
The operation of sample, or not it is understood that this is required to execute all operations shown to realize desired result.
Particular embodiments described above has carried out further in detail the purpose of the disclosure, technical scheme and beneficial effects
Describe in detail bright, it should be understood that the foregoing is merely the specific embodiment of the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the protection of the disclosure
Within the scope of.
Claims (7)
1. a kind of memory, including multiple memory cells, wherein the memory cell includes:
Bulk substrate；
Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；
Deep energy level defect dielectric layer, is located above the channel region；
Grid is located on deep energy level defect dielectric layer.
2. a kind of memory, including multiple memory cells, wherein the memory cell includes:
Bulk substrate；
Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；
First boundary layer is located on channel；
Deep energy level defect dielectric layer is located on the first boundary layer；
Grid is located on deep energy level defect dielectric layer.
3. a kind of memory, including multiple memory cells, wherein the memory cell includes:
Bulk substrate；
Source electrode and drain electrode above bulk substrate and the channel region extended between source electrode and drain electrode region；
First boundary layer is located on channel；
Deep energy level defect dielectric layer is located on the first boundary layer；
Second interface layer is located on deep energy level defect dielectric layer；
Grid is located on second interface layer.
4. memory according to claim 1 to 3, which is characterized in that the material of the deep energy level defect dielectric layer is
The HfO of dopingx, ZrOx, PZT, BFO or BST.
5. memory according to claim 4, which is characterized in that deep energy level defect dielectric layer is ferroelectric material layer.
6. memory according to claim 1 to 3, which is characterized in that it further include grid voltage controller, the control
Device is electrically connected to the grid of the storage unit, and for controlling grid voltage work in first voltage, the first voltage is small
The turnover voltage of polarization overturning occurs in deep energy level defect dielectric layer.
7. memory according to claim 1 to 3, which is characterized in that the multiple memory cell forms 3D and stacks
Structure.
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