CN109801666B

CN109801666B - Testing device for memory chip in hybrid circuit

Info

Publication number: CN109801666B
Application number: CN201910064323.XA
Authority: CN
Inventors: 李俊玲; 沈拉民; 颜伟; 屈博强
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2019-01-23
Filing date: 2019-01-23
Publication date: 2020-12-29
Anticipated expiration: 2039-01-23
Also published as: CN109801666A

Abstract

The testing device for the memory chip in the hybrid circuit can simultaneously realize fault positioning and diagnosis; the circuit comprises a built-in self-test circuit and a bus multiplexing circuit; the built-in self-test circuit and the bus multiplexing circuit are arranged on the master control protocol chip; the built-in self-test circuit is connected with a selection signal port of the bus multiplexing circuit and is connected with the bus multiplexing circuit through a test mode control bus, a test mode address bus and a test mode data bus; the master control protocol chip also comprises a functional memory controller; the control bus of the master control protocol chip is connected with the control port of the memory chip, the data bus of the master control protocol chip is connected with the data port of the memory chip, and the address bus of the master control protocol chip is connected with the address port of the memory chip; the output data bus of the master control protocol chip is connected with the output data port of the memory chip; the built-in self-test circuit and the functional memory controller read data on the memory chip through the output data bus.

Description

Testing device for memory chip in hybrid circuit

Technical Field

The invention belongs to the technical field of memory chip testing; in particular to a testing device of a memory chip in a hybrid circuit.

Background

Due to the characteristics of high assembly density, high reliability, good electrical property and the like, the hybrid integrated circuit technology is widely applied to the fields of computers, automobiles, communication, aerospace and the like. However, how to perform efficient high coverage testing on memory chips in a hybrid circuit configuration to check the manufacturing defects introduced by the assembly process of the hybrid integrated circuit for the memory is a problem in the circuit test verification stage.

MBIST (Memory built in Self Test) is an excellent Test solution for a single-chip embedded Memory recognized in the industry, but cannot be directly applied to a hybrid integrated circuit, and for a hybrid circuit Memory chip, more than all, a conventional functional read-write access mode is adopted to Test the hybrid integrated circuit Memory chip. However, this method has several problems in the following respects: firstly, a function access mode is realized by writing a related control register of a memory, the control time sequence is complex, the test vector generation difficulty is high, and the judgment on the read result of the memory is not intuitive; secondly, the specific structure of the memory determines that the memory has various related failure modes such as fixation, coupling, address decoding and the like, and the functional access is limited by the functional behaviors of the processor or the master controller, so that the test vector with higher test coverage is difficult to generate according to a specific algorithm aiming at the failure type of the memory, and the test coverage is insufficient; thirdly, the development and debugging of the function test vector are difficult, and the test time and the test cost are high. Furthermore, the functional test access approach makes it difficult to locate and diagnose failures in the failed memory.

Disclosure of Invention

The invention provides a self-test device of a hybrid circuit memory chip; the device can realize fault location and diagnosis simultaneously.

The technical scheme of the invention is as follows: a testing device for a memory chip in a hybrid circuit comprises a built-in self-test circuit and a bus multiplexing circuit; the built-in self-test circuit and the bus multiplexing circuit are arranged on the master control protocol chip; the built-in self-test circuit is connected with a selection signal port of the bus multiplexing circuit and is connected with the bus multiplexing circuit through a test mode control bus, a test mode address bus and a test mode data bus; the master control protocol chip also comprises a functional memory controller, and the functional memory controller is connected with the bus multiplexing circuit through a functional mode control bus, a functional mode address bus and a functional mode data bus; the control bus of the master control protocol chip is connected with the control port of the memory chip, the data bus of the master control protocol chip is connected with the data port of the memory chip, and the address bus of the master control protocol chip is connected with the address port of the memory chip; the output data bus of the master control protocol chip is connected with the output data port of the memory chip; the built-in self-test circuit and the functional memory controller read data on the memory chip through the output data bus.

Furthermore, the invention is characterized in that:

the built-in self-test circuit comprises a BIST controller, wherein the BIST controller is connected with a comparator, and the comparator reads data on the memory chip; the BIST controller is interactively connected with the diagnostor, and the diagnostor diagnoses and positions the failed memory chip and outputs diagnosis data; the BIST controller generates test stimuli and sends the test stimuli to the memory chip to be tested.

Wherein the comparator compares the acquired data of the memory chip with expected data and generates a test fail flag that characterizes the memory test result.

Wherein the test stimuli include memory control test stimuli, memory address test stimuli, and memory write data test stimuli.

The BIST kernel also obtains a test start signal and outputs a test end flag.

The bus multiplexing circuit acquires a control signal of the functional mode memory and a control signal of the test mode memory and outputs a memory control signal, acquires an address signal of the functional mode memory and an address signal of the test mode memory and outputs a memory address signal, acquires a data signal of the functional mode memory and a data signal of the test mode memory and outputs a memory data signal.

The memory to be tested acquires a memory control signal, a memory address signal and a memory data signal.

Compared with the prior art, the invention has the beneficial effects that: the testing device provided by the invention has the advantages of simple control operation, easy test generation and high test coverage, and can realize an effective testing approach of fault positioning and diagnosis so as to realize the test of the embedded memory chip in the hybrid integrated circuit. The device generates test excitation by the BIST controller through an external start test mode, realizes high coverage test for the memory through the access interface of the BIST controller and the memory chip to be tested, has small external resource overhead and simple control, and can directly represent the test result of the memory from the outside through the test completion flag signal and the test failure flag signal.

The testing device provided by the invention has simple structure control, and can completely realize built-in self test and fault diagnosis and positioning of the hybrid circuit articulated memory; by adopting an industry mainstream test algorithm for the memory, high coverage test on various faults of the memory can be realized; by adopting a bus interface of the functional memory, the external connection of the memory is simplified, and the test overhead is reduced; the test of the memory chip in the hybrid circuit is realized through a built-in self-test mode, the test generation is easy, and the test vector scale is small. The device is suitable for testing SIP, 3DIC and plug-in memories of board-level circuits.

Drawings

FIG. 1 is a schematic structural diagram of an embodiment of the present invention;

FIG. 2 is a block diagram of the built-in self test circuit of the present invention;

fig. 3 is a block diagram of a bus multiplexer circuit according to the present invention.

Detailed Description

The technical solution of the present invention is further explained with reference to the accompanying drawings and specific embodiments.

The invention provides a testing device of a memory chip in a hybrid circuit, which designs a built-in self-test circuit in a hybrid circuit main control chip by utilizing the characteristic of data interaction between the memory chip in the hybrid circuit and a main control protocol chip, and multiplexes functional data and a control bus to realize test access to the memory chip.

As shown in fig. 1, the device includes a built-in self-test circuit, a functional memory controller and a bus multiplexing circuit, and the built-in self-test circuit, the functional memory controller and the bus multiplexing circuit are arranged on a master control protocol chip; meanwhile, the built-in self-test circuit and the memory chip to be tested are not arranged on the same chip.

The built-in self-test circuit is connected with the bus multiplexing circuit through a test mode control bus, a test mode data bus and a test mode address bus; the function memory control is connected with the bus multiplexing circuit through a function mode control bus, a function mode address bus and a function mode data bus; the bus multiplexing circuit is connected with a control port of the memory chip to be tested through a control bus, the bus multiplexing circuit is connected with an address port of the memory chip to be tested through an address bus, and the bus multiplexing circuit is connected with a data port of the memory chip to be tested through a data bus. The built-in self-test circuit and the functional memory controller are also connected with a data output port of the memory chip to be tested through an output data bus.

As shown in fig. 2, the built-in self-test circuit includes a BIST controller connected to the comparator and the diagnostic, wherein the BIST controller is interfaced with the diagnostic, i.e., data interaction is enabled between the BIST controller and the diagnostic. The BIST controller acquires a test starting signal, and generates a test excitation according to a test algorithm through the control of the control state machine after the test starting signal is triggered; the test algorithm comprises MARCH2 or CHECKERBOARD and the like, and can also be customized according to the read-write time sequence and the fault type of the memory, so that high-coverage test of various fault types of the memory is realized; wherein the test stimuli include memory control test stimuli, memory address test stimuli, and memory write data test stimuli, and the test stimuli are applied to the memory chip under test.

Preferably, a control state machine is arranged in the BIST controller, and a control signal generator, an address generator and a data generator are further arranged, and the three generators are used for generating the test stimulus.

The comparator compares the data read from the memory to be tested with the expected data, and generates a test failure mark which is used for representing whether the test result of the memory is correct or not.

In view of the fact that the object of the built-in self-test structure is a memory hung outside a chip and the memory interface of a main chip has diversity, the device is mapped outside the built-in self-test circuit, a bus multiplexing mechanism is added, and the built-in self-test circuit can directly access an external memory to be tested through the memory interface of the main control protocol chip. The device avoids the additional arrangement of a set of memory interface for testing on the main control protocol chip, and simplifies the external interconnection. As shown in FIG. 3, the purpose of the bus multiplexing circuit is to realize channel switching between the functional access and the test access. Under the normal working mode of the circuit, the signal output of the functional memory controller is selected, and the test signal generated by the BIST controller is selected in the test mode, and the interface connection mode of the original circuit is not changed by multiplexing the memory bus interface of the original control chip with the selected function and the test. Only one-level multi-path selection structure is added on the function access path, the influence on the time sequence performance is very small, and the memory data read back by the memory output port does not need to be controlled and is directly input to a built-in self-test comparator for comparison and simultaneously sent to the function module.

The interconnection between the main control protocol chip and the external memory in the device is not affected, and the high-efficiency test of the memory chip is realized. The bus multiplexing design further reduces the test overhead and reduces the interconnection difficulty brought by external switching logic.

In a certain 0.5um technology hybrid integrated circuit, the testing device provided by the invention is adopted to realize the test of the memory chip in the hybrid circuit.

The hybrid circuit mainly comprises two chips, which are respectively: the device comprises a main control protocol chip and a 16K asynchronous single-port bidirectional data bus memory. The two chips are assembled and interconnected through a thick film process of the hybrid integrated circuit. The memory chip is a standard interface, the main control protocol chip initiates access to the memory through the host interface in a functional mode, and control, address and data buses of the main control protocol chip are all led out from chip pins.

Firstly, modeling is carried out on the read-write time sequence of a 16K asynchronous single-port memory in a master control protocol chip, and the design of an MBIST circuit is carried out by applying MarchC + and Checkboard algorithms which can detect most of memory faults in the mainstream of the industry.

In order to map the standard built-in self-test interface into the standard interface of the memory chip and simplify the external connection of the chip, the bus multiplexing design in the invention is adopted. The MBIST test signal and the functional memory controller signal are switched, so that the test operation of the discrete memory in the hybrid circuit can be normally finished in an MBIST test mode, and the memory work in a normal functional mode is not influenced. The bus multiplexing structure is internally provided with a plurality of multiplexing circuits, test and function data are selected through a multiplexer, and then interactive communication is carried out with a memory through an original function access interface. In this way, the entire controller external interface is unchanged. Mode control and test diagnosis of the MBIST circuit are realized through JTAG, test failure and test completion marks are directly observed outside a chip in a multiplexing mode with functional pins, and here, attention needs to be paid to that a multiplexed controller chip port is required to be a pin at the top layer of the hybrid circuit.

The tested object of the circuit is a memory of a single-port bidirectional data bus, so in the design of the BIST circuit, the read-write control signal generated by the BIST circuit needs to correspondingly control the enabling signal of the bidirectional data bus of the memory. To ensure the data flow of the bidirectional data bus is correct when the memory is read out and written in. In addition, for the structural fault defect of the MBIST circuit, the structural fault defect can be ensured through the testability design technology of internal scanning.

After the structure is applied, the test of the memory chip of the hybrid integrated circuit is greatly simplified, and although some expenses are added on the area of the self-test hardware structure, the direct effects brought by the structure are that the test generation difficulty is reduced, the test vector scale is reduced, more importantly, the high coverage test of the memory can be realized in 100% address traversal, and the test quality of the memory is improved. Based on the structure, the testing of the hybrid integrated circuit memory chip is successfully realized on a V93K testing platform, and the expected good effect is achieved.

Claims

1. The testing device for the memory chip in the hybrid circuit is characterized by comprising a built-in self-test circuit and a bus multiplexing circuit;

the built-in self-test circuit and the bus multiplexing circuit are arranged on the master control protocol chip;

the built-in self-test circuit is connected with the bus multiplexing circuit through a test mode control bus, a test mode address bus and a test mode data bus;

the master control protocol chip also comprises a functional memory controller, and the functional memory controller is connected with the bus multiplexing circuit through a functional mode control bus, a functional mode address bus and a functional mode data bus;

the control bus of the master control protocol chip is connected with the control port of the memory chip, the data bus of the master control protocol chip is connected with the data port of the memory chip, and the address bus of the master control protocol chip is connected with the address port of the memory chip;

the output data bus of the master control protocol chip is connected with the output data port of the memory chip;

the built-in self-test circuit and the functional memory controller read data on the memory chip through an output data bus;

the built-in self-test circuit comprises a BIST controller, wherein the BIST controller is connected with a comparator, and the comparator reads data on the memory chip; the BIST controller is interactively connected with the diagnostor, and the diagnostor diagnoses and positions the failed memory chip and outputs diagnosis data; the BIST controller generates a test stimulus and sends the test stimulus to a memory chip to be tested;

2. The apparatus of claim 1, wherein the comparator compares the acquired data of the memory chip with expected data and generates a test fail flag indicative of the result of the memory test.

3. The apparatus of claim 1, wherein the BIST controller further obtains a test start signal and outputs a test end flag.

4. The apparatus of claim 1, wherein the test stimuli comprise memory control test stimuli, memory address test stimuli, and memory write data test stimuli.

5. The apparatus of claim 1, wherein the memory under test obtains memory control signals, memory address signals, and memory data signals.