CN109792247B

CN109792247B - Apparatus and method for frequency tuning of a rotary traveling wave oscillator

Info

Publication number: CN109792247B
Application number: CN201780061716.4A
Authority: CN
Inventors: H·尚南
Original assignee: Analog Devices Inc
Current assignee: Analog Devices Inc
Priority date: 2016-10-07
Filing date: 2017-09-29
Publication date: 2023-08-22
Anticipated expiration: 2037-09-29
Also published as: DE112017005105T5; CN109792247A; DE112017005105B4; WO2018067406A1

Abstract

Provided herein are apparatus and methods for frequency tuning of a Rotary Traveling Wave Oscillator (RTWO). In some configurations, distributed quantization tuning is used to tune the frequency of the RTWO. The RTWO includes a plurality of segments distributed around the RTWO ring, and the segments include tuning capacitors and other circuitry. Distributed quantized frequency tuning is used to control tuning capacitors in segments of an RTWO using individually controllable code values, thereby enhancing the frequency step or resolution of the RTWO. Furthermore, in a configuration comprising multiple RTWO rings that lock onto each other to reduce phase noise, distributed quantized frequency tuning may be used to place tuning capacitors individually on the multiple RTWO rings that are coupled to each other.

Description

Apparatus and method for frequency tuning of a rotary traveling wave oscillator

Technical Field

Embodiments of the present invention relate to electronic systems, and more particularly to a Rotary Traveling Wave Oscillator (RTWO).

Background

Rotary Traveling Wave Oscillators (RTWO) may be used in a variety of applications including, for example, telecommunication systems, optical networks and/or chip-to-chip communications. For example, RTWO may be used in a frequency synthesizer to generate an output clock signal having a controlled phase and frequency relationship relative to a reference clock signal.

Disclosure of Invention

In one aspect, an RTWO is provided. RTWO includes: an RTWO ring comprising a first transmission line conductor and a second transmission line conductor and configured to carry a travelling wave; and a plurality of fragments located around the RTWO loop. In addition, a first segment of the plurality of segments includes: a pair of metal stubs including a first metal stub electrically connected to the first transmission line conductor and a second metal stub electrically connected to the second transmission line conductor; and one or more capacitor tuning groups electrically connected to the pair of metal stubs and operable to control the oscillation frequency of the RTWO.

In some embodiments, the first segment further comprises a TDC latch electrically connected between the first metal stub and the second metal stub and operable to detect the passage of the traveling wave.

In various embodiments, the lengths of the first metal stub and the second metal stub are substantially equal.

According to various embodiments, the length of each of the first and second metal stubs is at least 0.05 times the traveling wave wavelength.

In some embodiments, the first metal stub and the second metal stub each have a length of at least about 25 μm.

According to various embodiments, the first segment further comprises: a first tap buffer comprising an input electrically connected to the first metal stub; and a second tap buffer including an input electrically connected to the second metal stub.

In various embodiments, the first segment further comprises a regeneration circuit electrically connected between the first metal stub and the second metal stub and configured to provide energy to the traveling wave to compensate for a loss of the differential transmission line.

In various embodiments, each of the plurality of segments includes a plurality of tuning capacitor banks operable to provide an LSB tuning resolution of 50kHz/LSB or less and a tuning range of 4GHz or more.

In some embodiments, the one or more capacitor tuning banks include a fine tuning capacitor bank electrically connected between the first metal stub and the second metal stub, and a coarse tuning capacitor bank electrically connected between the first metal stub and the second metal stub. According to various embodiments, the one or more capacitor tuning banks further comprise a PVT tuning capacitor bank electrically connected between the first metal stub and the second metal stub.

In various embodiments, each segment includes a TDC latch, and the RTWO further includes a clock distribution tree and a reference clock buffer configured to provide a reference clock signal to the TDC latch of each segment via the clock distribution tree.

In other aspects, a PLL is provided. The PLL includes: a PLL core configured to generate one or more frequency tuning codes; and RTWO, including a ring, comprising: comprising a first transmission line conductor and a second transmission line conductor and configured to carry a traveling wave; and a plurality of segments located around the ring. Each segment includes a pair of metal stubs including a first metal stub electrically connected to the first transmission line conductor and a second metal stub electrically connected to the second transmission line conductor, and one or more capacitor tuning groups electrically connected to the pair of metal stubs and operable to control an oscillation frequency of the RTWO based on the one or more frequency tuning codes.

In some embodiments, the length of each of the first and second metal stubs is at least 0.05 times the traveling wave wavelength.

In various embodiments, the RTWO is configured to operate as a digitally controlled oscillator and a time-to-digital converter in a PLL.

In various embodiments, the one or more capacitor tuning groups include a fine tuning capacitor group and a coarse tuning capacitor group, and the one or more frequency tuning codes include a coarse tuning code and a fine integer tuning code.

In other aspects, RTWO is provided. RTWO includes: at least one RTWO loop around which a plurality of fragments are located; and a segment decoder system. Each of the plurality of segments includes one or more configurable circuits, and a segment decoder system is electrically connected to the plurality of segments and configured to control writing of configuration data to the one or more configurable circuits based on the segment address signals.

In some embodiments, each of the plurality of fragments is individually addressable by the fragment address signal.

In various embodiments, the segment decoder system includes a plurality of segment decoders, each segment decoder coupled to a respective one of the plurality of segments.

In various embodiments, the RTWO further includes a serial interface configured to provide the segment decoder system with a segment data signal and a segment address signal. In various embodiments, the segment decoder system is configured to select a segment of the plurality of segments based on the value of the segment address signal and write a plurality of bits of the segment data signal to the selected segment. According to some embodiments, the segment decoder system is configured to write a plurality of bits of the segment data signal to the selected segment over a fewer number of one or more lines than a plurality of bits in a plurality of clock cycles. In various embodiments, the segment decoder system is configured to select a segment of the plurality of segments based on the value of the segment address signal and read one or more bits from the selected segment. In various embodiments, the serial interface includes a local SPI.

In some embodiments, the one or more configurable circuits include at least one of a regeneration circuit, a latch, a tuning capacitor, or a tap buffer.

In various embodiments, the configuration data is operable to control at least one of a bias current, a resistance value, a capacitance value, or a transistor width of the one or more configurable circuits.

In other aspects, RTWO is provided. RTWO includes: a first RTWO ring, a plurality of segments positioned around the first RTWO ring and including a plurality of tuning capacitors selectable to control an oscillation frequency of the RTWO; and a decoder circuit operable to control selection of the plurality of tuning capacitors based on the one or more frequency tuning codes. The selection of the plurality of tuning capacitors is quantized over the plurality of segments.

In some implementations, the decoder circuit includes: a plurality of local decoders, each local decoder configured to control the number of selection capacitors for a respective one of the plurality of segments; and a plurality of tuning decoders configured to control the plurality of local decoders based on the one or more frequency tuning codes.

In various embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the decoder circuit is implemented such that selection of the one or more tuning decoders responsive to a given value of the fine frequency tuning code is dynamically selected. In various embodiments, the decoder circuit is implemented such that the order in which each of the plurality of tuned decoders is selected is different for a first slope of the fine frequency tuning code relative to a second slope of the fine frequency tuning code. In various embodiments, the selection order is rotated through a plurality of different selection orders. According to various embodiments, the selection order is randomly or pseudo-randomly selected.

In various embodiments, the decoder circuit is implemented such that the selection of one or more tuning capacitors responsive to a given value of the one or more frequency tuning codes is dynamically selected.

In some embodiments, the first RTWO ring includes a plurality of sides, and the decoder circuit is further configured to balance a number of selected tuning capacitors for each side of the RTWO ring. According to various embodiments, the decoder circuit is implemented such that the number of tuning capacitors selected per side of the RTWO ring is at most one tuning capacitor, except for each value of the one or more frequency tuning codes.

In various embodiments, the RTWO further includes a second RTWO ring locked to the first RTWO ring, and the decoder circuit individually controls a plurality of selected capacitors of the first RTWO ring and the second RTWO ring. According to various embodiments, the decoder circuit is further configured to balance the number of tuning capacitors selected for the first and second RTWO rings. According to some embodiments, the decoder circuit is implemented such that the number of selected tuning capacitors per RTWO ring is at most one tuning capacitor, except for each value of the one or more frequency tuning codes.

In various embodiments, the plurality of tuning capacitors includes at least one of a plurality of coarse tuning capacitors, a plurality of fine tuning capacitors, or a plurality of PVT tuning capacitors.

In various embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, and the decoder circuit is further configured to receive an offset code operable to provide capacitive tuning for a particular segment of the plurality of segments by tuning a value of the fine frequency tuning code. In various embodiments, the offset code is configured to provide dynamic capacitance adjustment for the plurality of segments when the RTWO is operable to linearize the RTWO.

In other aspects, a PLL with fine frequency tuning resolution is provided. The PLL includes: a PLL core configured to generate one or more frequency tuning codes; and RTWO. RTWO includes: a first RTWO ring; a plurality of segments located around the first RTWO ring and comprising a plurality of tuning capacitors selectable to control the oscillation frequency of the RTWO; and a decoder circuit operable to control selection of the plurality of tuning capacitors based on one or more frequency tuning codes. The selection of the plurality of tuning capacitors is quantized over the plurality of segments.

In various embodiments, the decoder circuit includes: a plurality of local decoders, each local decoder configured to control the number of selection capacitors for a respective one of the plurality of segments; and a plurality of tuning decoders configured to control the plurality of local decoders based on the one or more frequency tuning codes.

In some embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the decoder circuit is implemented such that selection of the one or more tuning decoders responsive to a given value of the fine frequency tuning code is dynamically selected. In various embodiments, the decoder circuit is implemented such that the order in which each of the plurality of tuned decoders is selected is different for a first slope of the fine frequency tuning code relative to a second slope of the fine frequency tuning code.

In various embodiments, the PLL further comprises a second RTWO ring locked to the first RTWO ring, and the decoder circuit individually controls a plurality of selected capacitors of the first RTWO ring and the second RTWO ring. In various embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, and the decoder circuit is further configured to receive an offset code operable to provide capacitive tuning for a particular segment of the plurality of segments by tuning a value of the fine frequency tuning code.

In some implementations, the PLL core is configured to control the value of the offset code to dynamically change the capacitance of the plurality of segments to linearize the RTWO.

In various embodiments, the frequency step of the RTWO corresponds to a selected frequency variation of one tuning capacitor derived from one segment.

In other aspects, RTWO is provided. RTWO includes: a first RTWO ring; a plurality of segments located around the first RTWO ring and comprising a plurality of tuning capacitors selectable to control the oscillation frequency of the RTWO; and a decoder circuit comprising a plurality of local decoders, each decoder configured to control the number of tuning capacitors selected in a respective one of the plurality of segments. In addition, the plurality of input codes of the plurality of local decoders are individually controllable.

In some embodiments, the decoder circuit further comprises a plurality of tuning decoders configured to control the plurality of input codes based on the one or more frequency tuning codes.

In various embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, and the decoder circuit is implemented such that selection of the one or more tuning decoders responsive to a given value of the fine frequency tuning code is dynamically selected.

In various embodiments, the RTWO further includes a second RTWO ring locked to the first RTWO ring, and the decoder circuit individually controls a plurality of selected capacitors of the first RTWO ring and the second RTWO ring.

According to some embodiments, the one or more frequency tuning codes include a fine frequency tuning code, and the decoder circuit is further configured to receive an offset code operable to provide capacitive tuning for a particular one of the plurality of segments by tuning a value of the fine frequency tuning code.

Drawings

Fig. 1 is a schematic diagram of an all-digital phase-locked loop (ADPLL) according to one embodiment.

Fig. 2 is an example of a plot of phase noise versus offset frequency for one implementation of the ADPLL of fig. 1.

Fig. 3 is a schematic diagram of one embodiment of a Rotary Traveling Wave Oscillator (RTWO).

Fig. 4 illustrates one implementation of the segment tuning of the RTWO.

Fig. 5 is a schematic diagram of one implementation of an RTWO with overlapping transmission waveforms of travelling waves.

FIG. 6A is a schematic diagram of one embodiment of an RTWO having segments comprising metal stubs.

Fig. 6B is a schematic diagram of one embodiment of a clock distribution tree for RTWO.

FIG. 7 is a schematic diagram of one embodiment of an RTWO segment with a metal stub.

Figures 8A-8R illustrate an RTWO tuning capacitor sequence for process, voltage and temperature (PVT) tuning, according to one embodiment.

Fig. 9A-9J illustrate an RTWO tuning capacitor sequence for fine integer tuning according to one embodiment.

Fig. 10 shows an embodiment of an RTWO with segment decoding.

Fig. 11 shows an embodiment of a tuned decoder for a multi-ring RTWO.

Fig. 12 shows an embodiment of an RTWO tuning decoder.

FIGS. 13A-1 and 13A-2 illustrate one embodiment of dynamic element matching for segment selection for RTWO.

FIGS. 13B-1 and 13B-2 illustrate another embodiment of dynamic element matching for segment selection of RTWO.

FIGS. 13C-1 and 13C-2 illustrate another embodiment of dynamic element matching for segment selection for RTWO.

Fig. 14 shows an embodiment of an RTWO with segmented digital addressing.

Fig. 15 illustrates various embodiments of a programmable segment circuit.

Fig. 16 shows an embodiment of a PLL system based on RTWO.

Detailed Description

The following detailed description of certain embodiments presents various descriptions of specific embodiments of the invention. The invention may, however, be embodied in a multitude of different ways as defined and covered by the claims. In this specification, reference is made to the drawings, wherein like reference numerals may refer to identical or functionally similar elements. It will be appreciated that the elements illustrated in the figures are not necessarily drawn to scale. Furthermore, it should be understood that certain embodiments may include more elements than shown in the figures and/or subsets of elements shown in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more drawings.

As will be appreciated by one of ordinary skill in the art, a Rotary Traveling Wave Oscillator (RTWO) may include differential transmission lines cross-connected in a ring in an odd number of one or more, and a plurality of regeneration circuits electrically connected along the path of the differential transmission lines. In addition, each crossover may reverse the polarity of the wave propagating along the differential transmission line, and the regeneration circuit may provide energy to the wave to compensate for the loss of the differential transmission line. Additional details of RTWO may be found in U.S. Pat. No.6,556,089 entitled "ELECTRONIC CIRCUITRY" issued 4/29/2003, which is incorporated herein by reference in its entirety.

Provided herein are devices and methods for RTWO.

In a first aspect, an RTWO includes a differential transmission line connected in a loop and a plurality of segments distributed around the loop. These segments comprise metal stubs extending from the RTWO differential transmission line. The metal stubs help to provide additional layout resources for tuning capacitors and other circuits of the RTWO segment while allowing the length of the RTWO ring to be relatively short. Thus, the metal stub does not prevent the RTWO from operating at a relatively high oscillation frequency (e.g., 10GHz or higher) while providing a connection to a tuning capacitor that adjusts the oscillation frequency of the RTWO over a wide tuning range and/or provides fine frequency steps. In some implementations, the RTWO can be tuned by coarse tuning and fine tuning capacitors to provide a wide tuning range, temperature tracking, and a wide frequency ramp, e.g., ramp up to about 1GHz at 10 GHz.

In a second aspect, a distributed quantization scheme is provided to tune the frequency of the RTWO. The RTWO includes a plurality of segments distributed around the RTWO ring, and these segments include tuning capacitors and other circuitry. Distributed quantized frequency tuning is used to control tuning capacitors in RTWO segments using individually controllable code values, thereby enhancing the frequency step or resolution of the RTWO. Furthermore, in a configuration comprising multiple RTWO rings locked to each other to reduce phase noise, distributed quantized frequency tuning may be used to place tuning capacitors on the multiple RTWO rings coupled to each other, respectively, e.g., a 4-coupled ring RTWO configuration. Implementation of RTWO with distributed quantized frequency tuning achieves relatively fine frequency resolution, e.g., a Least Significant Bit (LSB) tuning resolution of 50kHz/LSB or less and a relatively wide tuning range, e.g., 4GHz or more. The distributed quantization scheme may be used for various types of tuning including, but not limited to, coarse tuning, fine tuning, and process, voltage and temperature (PVT) tuning.

In a third aspect, a segmented decoding scheme is provided for RTWO frequency tuning codes to reduce decoding complexity. The segment decoding scheme may use a combination of global and local decoding to operate the frequency tuning code from the Phase Locked Loop (PLL) core to reduce the number of wires or conductors between the PLL core and the RTWO relatively much (e.g., 10 times or more).

In a fourth aspect, a dynamic element matching scheme is provided to linearize the fine tuning gain characteristics of the RTWO. For example, dynamic element matching may be used to reduce or eliminate the periodicity of the fixed segment selection order used in the segment decoding scheme of RTWO. By reducing or eliminating periodicity in the segment order selection, unwanted spurious frequency components can be mitigated. Conversely, selecting a fixed order of RTWO segments may reduce spectral integrity due to parasitic frequency components generated by the nonlinearity of the fine tuning characteristics of the RTWO.

In a fifth aspect, a segmented digital addressing scheme is provided to control parameters of RTWO segments individually. In some implementations, the serial interface communicates with the segments via segment decoders using shared or common line operations to reduce routing congestion. The controllable parameters may include, but are not limited to, bias settings (e.g., bias current levels) of amplifiers used in the RTWO regeneration circuit, bias settings (e.g., time-to-digital converter functions) of sampling latches of the RTWO, and/or providing segment-specific capacitance adjustments to provide linearity correction. Thus, the settings of a particular RTWO segment may be selected to provide tuning or correction of linear or other operating characteristics to improve performance.

The teachings herein may be used to provide a number of advantages. In one example, an RTWO-based all-digital phase-locked loop (ADPLL) operates with a relatively wide frequency tuning range and/or fine frequency tuning resolution. Furthermore, RTWO-based ADPLLs can operate with excellent robustness to remain locked in the presence of process, temperature and/or voltage variations.

The RTWO herein may exhibit relatively low phase noise. In one example, a four-coupled-loop RTWO implements Single Sideband (SSB) phase noise of-121 dBc/Hz at 8.8 GHz.

The RTWO here can also be implemented with a relatively compact area and exhibit relatively low power consumption. In one example, an RTWO with four coupling rings consumes less than about 190mW when operated at about 0.9V and occupies less than about 1.2mm ² Is a part of the area of the substrate.

The RTWO herein may also exhibit a relatively wide tuning range. In one example, for one implementation with four coupling loops, the RTWO is tunable over a frequency range greater than 3GHZ, for example, between about 8.8GHZ and 12 GHZ.

A wide tuning range may provide a number of advantages. For example, RTWO can be used in PLL which can maintain a locked state over a wide range of temperature variations. For example, RTWO can be calibrated at the extremes of the operating temperature range, and the loop of the PLL can remain locked when the temperature changes to the other end of the temperature range. In one example, the RTWO calibrates at the low end of the temperature range (e.g., 40 ℃) and the PLL remains locked as the temperature gradually increases to the high end of the temperature range (e.g., 125 ℃). In another example, the RTWO is calibrated to the high end of the temperature range and the PLL remains locked as the temperature gradually decreases to the low end of the temperature range. For example, in such an example, an RTWO may utilize 40% or less of the fine tuning range of the RTWO in response to changes in operating temperature.

When used in a PLL, RTWO can provide a relatively small amount of output clock jitter. In one example implementation, the ADPLL achieves a closed-loop Root Mean Square (RMS) jitter of about 240fs or less when operating between about 1kHz to 100MHz over a temperature range of about-40 ℃ to about 125 ℃ within the tuning range of the RTWO.

Examples of all-digital phase-locked loops with rotating traveling wave oscillators

In certain configurations herein, an all-digital phase-locked loop (ADPLL) is provided that includes a Rotating Traveling Wave Oscillator (RTWO). ADPLLs may be used in a variety of applications including, but not limited to, telecommunications, chip-to-chip communications, and/or automated test equipment. In one example, the ADPLL generates output clock signals having various frequency ramp profiles and/or rates.

In contrast, an analog PLL with a charge pump may be affected by supply voltage variations, narrow tuning voltage ranges, and/or loop dynamics. These drawbacks are exacerbated in implementations using relatively small geometry processes (e.g., thin line CMOS processes). While ADPLL architecture may provide many advantages, the teachings herein are also applicable to RTWO's used in other electronic systems, such as analog PLLs using RTWO's.

In some implementations, the ADPLL includes an RTWO that operates as both a Digitally Controlled Oscillator (DCO) and a time-to-digital converter (TDC). By using RTWO for a variety of purposes, implementing RTWO to provide a variety of functions may enhance the compactness of the design.

By using RTWO in ADPLL, a low figure of merit (FOM) can be achieved. The excellent FOM is achieved in part by the fine resolution of RTWO TDC.

While the RTWO described herein may be used in an ADPLL, RTWO implemented in accordance with the teachings herein may be used in a wide variety of electronic systems and applications.

Fig. 1 is a schematic diagram of an ADPLL 10 according to one embodiment. ADPLL 10 comprises a fractional accumulator 1, a digital filter 2, a combined Digitally Controlled Oscillator (DCO) and time-to-digital converter (TDC) 4, a counter 5, a counter latch 6, a multiplier 7, a subtracting block 11 and an adding block 12. The combined DCO and TDC 4 includes an RTWO 15 and a TDC latch 16.

As shown in fig. 1, ADPLL 10 includes a fractional accumulator 1 that references a clock signal CLK _REF Rate accumulated digital tuning word or code N _freq . Digital tuning code N _freq May be used to control the output frequency of the ADPLL 10. In the illustrated embodiment, for the reference clock signal CLK _REF The subtracting block 11 generates a difference signal based on the difference between the output of the fractional accumulator 1 and a plurality of DCO clocks num_dco generated in part by the RTWO 15. The number of DCO clocks num_dco corresponds to the digital code expressed in integer and fractional forms.

As shown in fig. 1, RTWO 15 and TDC latch 16 operate to generate a fractional number of DCO clocks frac_dco, wherein the addition block 12 combines with an integer number of DCO clocks int_dco to generate a DCO clock num_dco number. Specifically, RTWO 15 generates K clock phases that are provided to TDC latches 16. The TDC latch 16 is based on a reference clock signal CLK _REF K clock phases from RTWO 15 to determine the fractional number of DCO clock FRAC_DCO. The K clock phases have the same oscillation frequency as each other but have different phases. In one embodiment, the RTWO outputs 64 or more phases to the TDC latch 16. However, other implementations are also possible.

Although the TDC latch 16 is shown as a separate block from the RTWO 15, in some implementations the TDC latch 16 is integrated into the layout of the RTWO 15, for example incorporated into the layout of the RTWO segments.

With continued reference to FIG. 1, RTWO 15 outputs the DCO clock signal CLK _DCO Which may correspond to one of K clock phases in some implementations. In the illustrated embodiment, the DCO clock signal CLK _DCO Is used as an input to a multiplier 7, which multiplier 7 outputs a DCO clock signal CLK _DCO Multiplying by a multiplication factor M to generate an output clock signal CLK _OUT . Comprising multipliers 7 for controlling the output clock by extension Signal CLK _OUT To enhance the flexibility of the ADPLL 10. For example, multiplier 7 may be used to output clock signal CLK _OUT Is controlled to a frequency greater than the maximum oscillation frequency of the RTWO 15 and thus can be used as a frequency multiplier.

In one example, RTWO is multiplied by a multiplication factor M. In another example, the multiplier is omitted.

As shown in fig. 1, the DCO clock signal CLK _DCO Is provided to an integer counter 5. The integer counter 5 works in combination with a counter latch 6 to produce an integer number of DCO periods int_dco. In the illustrated embodiment, the integer counter 5 counts the DCO clock signal CLK _DCO Counting the number of cycles of (a). For example, the integer counter 5 may be loaded with an initial value of 1 and then clocked with the DCO clock signal CLK _DCO Is incremented by 1.

The difference signal generated by the subtracting block 11 is filtered by the digital filter 2. In addition, in this embodiment, the filtered difference signal is used to tune RTWO 15 with an integer digital tuning code INT and a fractional digital tuning code F.

The RTWO 15 of fig. 1 is tuned by an integer digital tuning code INT and a fractional digital tuning code F to change the fundamental oscillation frequency of the RTWO. In some implementations, RTWO 15 may employ additional tuning including, for example, coarse tuning and/or process, voltage and temperature (PVT) tuning.

Thus, in some implementations, the fractional digital tuning code F provides fine fractional tuning of the RTWO 15 and the integer digital tuning code INT provides fine integer tuning.

RTWO 15 may be implemented to include one or more features disclosed herein. In one embodiment, RTWO 15 is implemented using at least one of distributed quantization tuning, segment decoding, dynamic element matching, segment digital addressing, or segments including metal stubs.

ADPLL 10 illustrates one example of an electronic system that may include an RTWO implemented in accordance with the teachings herein. However, the RTWO described herein may be used in a wide variety of electronic systems, including but not limited to a wide variety of data converters and/or frequency synthesizers.

Fig. 2 is an example of a plot 20 of phase noise versus offset frequency for one embodiment of ADPLL 10 of fig. 1.

Graph 20 includes a first curve 21 of the intrinsic DCO phase noise for the combined DCO and TDC 4, a second curve 22 of the TDC phase noise for the combined DCO and TDC 4, and a third curve 23 of the total ADPLL phase noise.

As shown in fig. 2, the RTWO TDC and DCO functions substantially dominate the ADPLL phase noise at low and high frequency offset, respectively.

Although one example plot of phase noise at offset frequency is shown in fig. 2, other phase noise versus offset frequency characteristics are possible.

Fig. 3 is a schematic diagram of one implementation of RTWO 30. The RTWO30 comprises a differential transmission line comprising a first conductor 31 and a second conductor 32. As shown in fig. 3, the differential transmission lines 31, 32 are connected in a closed loop or ring, and the differential transmission lines include a crossover 33 to provide inversion to the traveling wave propagating around the ring. The RTWO30 of fig. 3 further comprises a plurality of segments 35, each segment 35 comprising a regeneration circuit.

The illustrated RTWO30 includes one crossover and thirty-two regeneration circuits, each implemented using back-to-back inverters in this example. However, other configurations are possible, including configurations using different numbers of crossings, more or fewer segments, more or fewer regeneration circuits, and/or regeneration circuits implemented in other ways, for example. Furthermore, RTWO30 may include other circuitry including, but not limited to, tuning capacitors, latches, buffers, and/or other circuitry in segment 35.

As shown in fig. 3, the differential transmission lines of the RTWO are connected in a closed loop manner and folded at each of the four corners. However, the differential transmission line of the RTWO may be implemented in other ways, including for example different implementations of folding and/or routing of the conductors 31, 32. For example, the teachings herein are applicable not only to RTWO implemented using rectangular or square rings, but also to RTWO, which include otherwise shaped transmission lines. Thus, while the RTWO shown includes four sides, the teachings herein apply to RTWOs that include more or fewer sides, as well as RTWOs that have curved loops.

In the illustrated embodiment, the RTWO 30 includes segments 35, each segment including regenerative circuits distributed at substantially regular intervals around the differential transmission line. The uniform distribution of the regeneration circuit helps to maintain a uniform characteristic impedance and a substantially constant wave velocity of the differential transmission line. Although each segment 35 includes a pair of back-to-back inverters, the teachings herein are applicable to segments that include other numbers of regeneration circuits and/or different embodiments of regeneration circuits.

In the illustrated embodiment, RTWO 30 is segmented into 8 segments per side. Since each of conductors 31, 32 provides a clock signal phase, the 32 segments 35 shown operate with 64 total clock signal phases. However, other implementations are also possible.

Oscillation frequency f of RTWO 30 _OSC Based on the velocity of the traveling wave traveling along the transmission line divided by the total length or distance the wave travels in one cycle. In certain embodiments, the oscillation frequency f of RTWO 30 _OSC Given by equation 1 below, where v _p Is the wave phase velocity, L is the length of the transmission line loop or loop, L _TL Is the transmission line inductance, and C _TL Is the transmission line capacitance.

Equation 1

In certain configurations herein, a segment of RTWO (e.g., segment 35 of RTWO 30) includes one or more tuning capacitors having digitally controllable capacitance to set the oscillation frequency of the RTWO.

It may be difficult to meet the RTWO specification in terms of tuning range and frequency tuning step size. In configurations where RTWO is designated to operate at relatively high oscillation frequencies, this challenge may be exacerbated. For example, an RTWO with a relatively high oscillation frequency may have a relatively short transmission line loop and thus may be constrained by available layout resources, such as available transistor active area and/or metal routing channels.

For example, RTWO 30 may be included in ADPLL 10 of fig. 1. However, in some applications, it may be desirable for the ADPLL 10 to oscillate at a relatively high frequency f _OSC (e.g., 10GHz or higher), has a relatively wide tuning range (e.g., 625MHz or higher), and has a relatively fine tuning resolution (e.g., 200kHz or lower).

Fig. 4 illustrates one implementation of the segment tuning of the RTWO. Segment tuning includes PVT tuning (3 bits in this example), coarse tuning (7 bits in this example), fine integer tuning (31 bits in this example) and fine fractional tuning (7 bits in this example).

As shown in fig. 4, PVT tuning is controlled by PVT tuning code with a value ranging from 0 to N _pvt Coarse tuning is controlled by coarse tuning code, which ranges in value from 0 to N _{Roughness of} Fine integer tuning is controlled by a fine integer tuning code having a value in the range of 0 to N _{Fine i} Fine fraction tuning is controlled by a fine fraction tuning code having a value in the range of 0 to N _{Fine f} 。

While one particular implementation of segment tuning is shown, the RTWO herein may be implemented with various segment tuning schemes, including but not limited to using more or fewer bits and/or more or fewer segments of tuning code.

As indicated by block 41 of fig. 4, the RTWO can operate with an oscillation frequency given by equation 2 below, where f _rtwo Is the oscillation frequency of RTWO, all tuning capacitors are deselected, n _pvt Is a selected value for PVT tuning, Δf _pvt,lsb Is PVTLSB frequency resolution (e.g., 16 MHz), n _{Roughness of} Is a selection of coarse tuning, Δf _{Coarse, lsb} Is the coarse LSB frequency resolution (e.g., 9 MHz), n _{Fine i} Is a selected value for fine integer tuning, Δf _{Fine i, lsb} Is a fine integer LSB frequency resolution (e.g., 200 KHz), n _{Fine f} Is a selected value for fine fraction tuning, and Δf _{Fine f, lsb} Is a fine fraction LSB frequency resolution (e.g., 200 KHz).

Equation 2

f _osc ＝f _rtwo +n _pvt *△f _pvt,lsb +n _coarse *△f _coasre,lsb +n _finei *△f _finei,lsb +n _finef *△f _finef,lsb

Implementing RTWO using segmented tuning can reduce the number of tuning capacitors per segment in the RTWO layout. For example, for the 625MHz tuning range and 200kHz tuning resolution specifications, the same size tuning capacitors are used except for the tuning capacitors for PVT variations and there is no tuning capacitor that can have about 12 bits and 2 per segment ¹² A segment of=4096 tuning capacitors to implement RTWO. The routing and control of these tuning capacitors per segment would not be feasible in view of layout resource limitations. In contrast, RTWO using the segment tuning of FIG. 4 can meet these specifications, with about 38 tuning capacitances per segment for coarse and fine integer tuning, 3 tuning capacitances per segment for PVT variation, and 7 tuning capacitances connected to the RTWO ring for fine fractional tuning.

The selection of values for segment tuning may be provided in various ways. In one example, the PVT code is first selected to compensate for PVT variations. Thereafter, a coarse tuning code may be selected. Further, the fine integer and fine fraction tuning codes may be controlled in a loop (e.g., by ADPLL 10 of fig. 1). Thus, the resolution of the fine fraction tuning capacitor bank may control the overall frequency resolution of the RTWO. Thus, providing segmentation may provide two benefits of fine frequency tuning resolution and reduced number of tuning capacitors per segment.

In some implementations, RTWO is tuned to the target frequency by first selecting the value of the PVT tuning code, then selecting the value of the coarse tuning code, and finally selecting the values of the fine integer tuning code and the fine fractional tuning code through the PLL loop. (e.g., ADPLL 10 of fig. 1). For example, an algorithm may be used to select a value for the PVT tuning code that provides a value equal to n _pvt *Δf _pvt,lsb Is used for the frequency step of the frequency step-up circuit. The selected PVT code may be greater than or less than the initial PVT code N _pvt,start . Next, for the selected PVT code, the code N is coarsely tuned from the beginning _{Roughness, start} Start to re-loadRunning the algorithm newly and selecting to provide a value equal to n _{Roughness of} *Δf _{Coarse, lsb} Is used for the coarse tuning code of the frequency step of (a). The coarse tuning code selected may be greater or less than the initial PVT code N _pvt,start . Thereafter, the ADPLL loop is closed and the correct fine integer code and fine fraction code are reached by the loop feedback of the ADPLL to tune the RTWO to the correct frequency.

In certain implementations, the RTWO includes a plurality of fragments distributed around the RTWO loop. Furthermore, each RTWO segment includes a PVT tuning capacitor bank, a coarse tuning capacitor bank, and a fine integer tuning capacitor bank. In certain implementations, the RTWO includes one instance of a fine fraction tuning capacitor bank and multiple instances of a fine integer tuning capacitor bank, a coarse tuning capacitor bank, and a PVT tuning capacitor bank. However, other implementations are also possible.

Fig. 5 is a schematic diagram of one implementation of an RTWO 60 with overlapping traveling wave transmission waveforms. RTWO 60 comprises a differential transmission line comprising a first conductor 31, a second conductor 32 and a crossover 33.RTWO 60 also includes a plurality of segments 65, each segment 65 including a TDC latch.

Although one particular RTWO implementation is shown, the teachings herein are applicable to RTWO implemented in a variety of ways. Although the illustrated segments 65 are each shown as including a TDC latch, for clarity, the segments 65 include additional circuitry that has been omitted from FIG. 5.

The illustrated RTWO 60 is used as a time-to-digital converter (TDC). The time-to-digital conversion function is provided by the delay of the traveling wave traveling around the RTWO ring. For example, the illustrated RTWO 60 is divided into 32 segments 65. In addition, traveling waves traveling along the transmission line of the RTWO traverse each segment 65 twice is an RTWO cycle.

For example, during operation, the traveling wave travels one turn around the transmission line and completes half of the RTWO cycle (180 ° phase) through all segments 65. After inversion, the wave passes through each segment 65 again to complete the second turn around the transmission line and to complete the RTWO cycle (360 ° phase).

As shown in fig. 5, the traveling wave experiences a fixed time delay at each segment 65 of the RTWO. The time delay of the wave at the segment corresponds to the time-to-digital conversion resolution, corresponding to about half of the RTWO period divided by the number of segments 65.

Thus, a plurality of segments 65 may be selected to control the resolution of the RTWO providing time-to-digital conversion functionality.

In one example, RTWO operates at a period of about 1/10GHz and includes 32 segments, and has a corresponding time-to-digital conversion resolution Δt of about 1.56ps _tdc 。

In the illustrated configuration, each segment 65 includes a TDC latch for outputting a reference clock signal CLK _REF The RTWO phase is sampled. In addition, in this example, the reference clock signal references the clock signal CLK _REF The TDC latches of segment 65 are provided via clock conductor 66, which is a ring connection.

Referring to fig. 3-5 and equation 1, the oscillation frequency of the RTWO is based on the ring or the length of the ring of the RTWO. In order to provide an RTWO with a high oscillation frequency, a relatively short transmission line loop is required. However, in order to provide a wide frequency tuning range and fine frequency tuning resolution, a relatively large number of tuning capacitors are required. Moreover, in order to provide a fine resolution time-to-digital conversion function, a large number of fragments are required.

Thus, there is a complex tradeoff between RTWO frequency characteristics (e.g., oscillation frequency, tuning range, and/or frequency step size) and implementation of RTWO segments (e.g., number of segments, layout of segments, and/or circuitry of segments).

Examples of rotary traveling wave oscillators with metallic stubs

Segments of the RTWO may include a variety of circuits including, for example, regeneration circuits (e.g., a sustain amplifier), tuning capacitors, latches, buffers, and/or other circuits. In a first example, to achieve a sufficient tuning range, each RTWO segment may include multiple tuning capacitor banks, for example, three or more tuning capacitor banks as previously discussed with reference to fig. 4. In a second example, a segment of RTWO includes a TDC latch to provide time-to-digital conversion. In a third example, segments of the RTWO each include at least one tap buffer (e.g., a non-inverting or inverting buffer) for obtaining or extracting a clock signal of a particular phase from the RTWO ring.

While it is desirable for a segment of an RTWO to include a large number of relatively large-sized circuits and/or circuits, the RTWO may be constrained by available layout resources, such as available active area and/or routing tracks. Furthermore, providing additional layout resources by increasing the length of the RTWO segments undesirably increases the length of the RTWO ring, thereby reducing the oscillation frequency of the RTWO.

In certain configurations herein, the RTWO includes a segment having a metal stub extending from a differential transmission line of the RTWO. The metal stub provides a connection to other layout resources. For example, the segment layout may be relatively wide (e.g., in a first dimension substantially perpendicular to a local portion of the RTWO transmission line) and may include tuning capacitors and other circuitry connected to the metal stubs. However, the segment layout has a relatively short length (e.g., in a second dimension substantially parallel to a local portion of the RTWO transmission line) such that the transmission line loop of the RTWO is relatively short to provide a high oscillation frequency, e.g., 10GHz or higher.

Thus, a metal stub extends from the differential transmission line of the RTWO to provide a connection to tuning capacitors and/or other circuits that help achieve a wide tuning range, fine frequency steps, high oscillation frequencies, and/or provide additional functionality to the RTWO, such as time-to-digital conversion functionality and/or segment programmability.

FIG. 6A is a schematic diagram of one embodiment of an RTWO 70, wherein the segments comprise metal stubs. The RTWO 70 includes a differential transmission line comprising a first conductor 31, a second conductor 32 and a crossover 33.RTWO 70 also includes a plurality of fragments 75.

In the illustrated embodiment, RTWO 70 includes one intersection and thirty-two segments. However, other configurations are possible, including, for example, configurations using a different number of intersections and/or more or fewer segments. Further, in the illustrated embodiment, the differential transmission lines of the RTWO are connected in a closed loop and folded at each of the four corners. However, the differential transmission line of the RTWO may be implemented in other ways, including for example different implementations of folding and/or routing of the conductors 31, 32. For example, the teachings herein are applicable not only to RTWO implemented using rectangular or square loops, but also to RTWO, which include otherwise shaped transmission lines. Thus, while RTWO 70 is shown to include four sides, the teachings herein apply to RTWOs that include more or fewer sides.

In the illustrated embodiment, RTWO 70 includes segments 75, each segment including a first metal stub 81 and a second metal stub 82 extending from first conductor 31 and second conductor 32, respectively. The first and second metal stubs 81, 82 are used to provide a local clock phase signal from the differential transmission line of the RTWO to the circuitry of segment 75.

In the illustrated embodiment, each segment 75 includes a TDC latch 91, a tuning capacitor 92, and a regeneration circuit 93 that operate using the phase of the clock signal from the first conductor 31 and the phase of the clock signal from the second conductor 32. However, other implementations are possible. Although shown as being connected between the first and second conductors 31, 32 of the RTWO ring, in another example, the regeneration circuit 93 is connected between the first and second metal stubs 81, 82. In the illustrated embodiment, each segment 75 includes a first tap buffer 94 that taps first conductor 31 to obtain a first clock signal phase and a second tap buffer 95 that taps second conductor 32 to obtain a second clock signal phase.

Although one particular implementation of a segmented circuit is shown in fig. 6A, other implementations of segmented circuits are possible, including configurations including more or fewer circuits and/or different circuits. For example, in another embodiment, a first set of tuning capacitors and a second set of tuning capacitors are connected to the first and second conductors 31, 32, respectively. In yet another embodiment, the fragment includes circuitry that provides fragment programmability.

By including first and second metal stubs 81, 82 extending from the differential transmission lines 31, 32 of the RTWO, the segment 75 of the RTWO can be implemented with a wide layout that provides active area and routing resources suitable for the segmented circuit. In addition, the RTWO includes differential transmission lines 31, 32 in a relatively short loop, so that the RTWO 70 has a relatively high oscillation frequency.

In one embodiment, the RTWO has a total loop length of less than 7,500 μm and the stub length of each of the first and second metal stubs 81, 82 is at least 25 μm. For example, with respect to the rectangular ring shown in FIG. 6A, in one embodiment, the RTWO of FIG. 6A has a first length L of less than about 1,875 μm _RING-X And a second length L of less than about 1,875 μm _RING-Y 。

The stub length may be expressed as a fraction of the wavelength of the RTWO traveling wave. In one embodiment, the length of each of the first and second metal stubs 81, 82 is at least about 0.05λ, where λ is the wavelength of the RTWO. As the skilled person will appreciate, the wavelength of an RTWO may be expressed as the wave phase velocity of the RTWO and the oscillation frequency or v of the RTWO _p /f _osc Is a ratio of (2).

In one embodiment, the segments 75 are less than about 25 μm in length and at least about 25 μm in width.

In one embodiment, the RTWO comprises at least 1 fragment per 25 μm loop.

FIG. 6B is a schematic diagram of one embodiment of a clock distribution tree 87 for RTWO 80. RTWO 80 includes a differential transmission line connected in a loop and including a first conductor 31, a second conductor 32 and a crossover 33. RTWO 80 also includes segment 85 and reference clock buffer 86. For clarity, the circuitry of segment 85 is not shown in fig. 6B.

As shown in fig. 6B, a reference clock buffer 86 provides a reference clock signal to each segment 85. The reference clock buffer 86 provides a reference clock signal to the clock distribution tree 87, which clock distribution tree 87 distributes the reference clock signal to each segment 85. The clock distribution tree 87 may be used to provide a reference clock signal to the TDC latches and/or other circuitry of the segment 85 that operates using the reference clock signal.

The illustrated clock distribution tree 87 is implemented using branches such that the length of the clock conductors from the output of the reference clock buffer 86 to each segment 85 is substantially the same. Implementing the clock distribution tree 87 in this manner helps to substantially match the time of arrival of the reference clock signal at the TDC latches and/or other circuitry of the segment 85.

Other details of the RTWO 80 of fig. 6B may be similar to those described previously.

Fig. 7 is a schematic diagram of one embodiment of an RTWO segment 100 having a metal stub. The RTWO segment 100 is connected to a first transmission line conductor 101 and a second transmission line conductor 102 of a ring of the RTWO.

For clarity, only a portion of the first transmission line conductor 101 and the second transmission line conductor 102 are shown in fig. 7. However, the first transmission line conductor 101 and the second transmission line conductor 102 operate as part of a differential transmission line of an RTWO connected in a loop.

The RTWO segment 100 of fig. 7 includes a PVT tuning capacitor bank 111, a coarse tuning capacitor bank 112, a fine tuning capacitor bank 113, a regeneration circuit 115, a TDC latch 117, a first tap buffer 118a, a second tap buffer 118b, a first metal stub 131, and a second metal stub 132.

The PVT tuning capacitor bank 111 includes optional capacitors for compensating for process, temperature, and/or voltage variations. In addition, coarse tuning capacitor bank 112 includes selectable capacitors for providing coarse tuning of the oscillating frequency of the RTWO. Furthermore, the fine tuning capacitor bank 113 comprises selectable capacitors for providing fine tuning of the oscillation frequency of the RTWO. The tuning capacitor bank may be implemented using any suitable tunable capacitor structure, including but not limited to a bank of parallel capacitor elements digitally selectable by a switch.

Although an example of an RTWO segment including three tuning capacitor banks is shown in fig. 7, the teachings herein apply to RTWO tuned using more or fewer capacitor banks.

In the illustrated embodiment, the PVT tuning capacitor bank 111 operates using a three bit PVT tuning code, the coarse tuning capacitor bank 112 operates using a seven bit coarse tuning code, and the fine tuning capacitor bank 113 operates using a thirty-one bit fine integer tuning code. Although one specific example of a bit width is shown, the teachings herein are applicable to tuning with a variety of bit widths. Thus, other implementations are also possible. In some implementations, the fine tuning capacitor bank 113 is controlled by a PLL feedback loop. For example, the fine integer tuning code may be controlled by a digital filter of the PLL.

The illustrated RTWO segment 100 further includes a TDC latch 117 for detecting the passage of traveling waves traveling along the first and second transmission line conductors 101, 102. For example, the output of the TDC latches around the RTWO ring may be processed to generate a digital representation of the time instances of traveling waves through different locations around the ring. For example, the output of the TDC latch may be used to determine the fraction of clock cycles that have passed.

As shown in fig. 7, the TDC latch 117 receives the reference clock signal CLK _REF . In some implementations, the reference clock signal CLK _REF Is provided to the RTWO segment 100 via a clock distribution tree (e.g., clock distribution tree 87 of fig. 6B).

In the illustrated embodiment, the first tap buffer 118a and the second tap buffer 118b are implemented using inverters. The first tap buffer 118a and the second tap buffer 118b are used to generate clock signal phases that are approximately 180 ° apart from each other. By providing tap buffers at different locations along the RTWO ring, a set of clock signals of a desired phase can be obtained. Although fig. 7 shows a configuration in which an inverter is used to provide taps, the RTWO may include tap buffer circuits implemented in various ways.

In the illustrated embodiment, the regeneration circuit 115 includes a first inverter 116a and a second inverter 116b. In addition, the input of the first inverter 116a is electrically connected to the output of the second inverter 116b, and the output of the first inverter 116a is electrically connected to the input of the second inverter 116b. However, the RTWO segment may include regeneration circuitry that is implemented in other ways.

The first and second metal stubs 131, 132 provide a local clock phase from the RTWO loop to the circuitry of the RTWO segment 100. By using the first and second metal stubs 131, 132, the length of the RTWO segment 100 can be relatively short, which in turn results in a relatively short RTWO ring and a correspondingly high RTWO oscillation frequency.

In certain configurations herein, the RTWO segment includes a routing channel 133 for providing routing through the routing track of the RTWO segment.

As shown in fig. 7, the first and second metal stubs 131, 132 provide connection from the first transmission line conductor 101 and the second transmission line conductor 102, respectively, to the circuitry of the RTWO segment 100. For example, first and second metal stubs 131, 132 connect the RTWO ring to tuning capacitors and other circuitry of the RTWO segment 100.

The first and second stub 131, 132 provide a capacitive load that acts as the characteristic impedance Z of the transmission line _o Is a part of the operation of (a). In certain embodiments, the metal stubs may be implemented in approximately equal lengths, and may be distributed at substantially uniform intervals around the RTWO ring. While the spool is shown as being substantially identical for each segment, in other configurations, the spool may be implemented differently for one or more segments. In one example, the design rules of the process limit the layout of the transistor in one direction and the stubs along the top and bottom sides of the RTWO are implemented differently than the stubs on the left and right sides of the RTWO.

As shown in fig. 7, a first metal stub 131 is connected to the first transmission line conductor 101 (e.g., through a via) and extends from the first transmission line conductor 131 to provide a connection to the circuitry of the RTWO segment 100. In the illustrated embodiment, a first metal stub 131 is connected to a first terminal of the PVT tuning capacitor bank 111, a first terminal of the coarse tuning capacitor bank 112, a first terminal of the fine tuning capacitor bank 113, an input of the first tap buffer 118a, a first input of the TDC latch 117. In the illustrated embodiment, the end of the first metal stub 131 is bent before being connected to the first input of the TDC latch 117. However, other implementations are possible.

With continued reference to fig. 7, a second metal stub 132 is connected to the second transmission line conductor 102 (e.g., through a via). After an initial turn or bend, a second metal stub 132 extends from the second transmission line conductor 132 to provide a connection to the circuitry of the RTWO segment 100. In the illustrated embodiment, a second metal stub 132 is connected to the second end of the PVT tuning capacitor bank 111, the second end of the coarse tuning capacitor bank 112, the second end of the fine tuning capacitor bank 113, the input of the second tap buffer 118b, and the second input of the TDC latch 117. However, other implementations are possible.

In one embodiment, the first metal stub 101 and the second metal stub 102 each have a length (including bends) of at least about 25 μm. In one example, the length of the short tubes 101, 102 is about 95 μm, corresponding to about 6% of the wavelength (or 0.06 λ) of an RTWO operating at 10 GHz.

As shown in fig. 7, the transmission line conductors 101, 102 of the RTWO ring have a width W and are spaced apart from each other by a spacing S. The width W and spacing S may be any suitable value, for example w=12 microns, s=8 microns.

In certain embodiments, the transmission line conductors 101, 102 are positioned on different metal layers relative to the metal stubs 131, 132. In one example, the transmission line conductors 101, 102 of the differential transmission line of the RTWO are implemented on two or more adjacent upper metal layers (e.g., a stack of metal-8 and metal-9), and the stub is implemented on a lower metal layer (e.g., metal-7). As will be appreciated by those of ordinary skill in the art, the lower metal layer is closer to the semiconductor substrate than the upper metal layer.

As shown in fig. 7, a planar layout 120 of the RTWO segment 100 has been shown. The plan view layout 120 includes a PVT tuning capacitor bank layout 121, a coarse tuning capacitor bank layout 122, a fine tuning capacitor bank layout 123, a regenerative amplifier layout 125, a TDC latch layout 127, a tap buffer layout 128, and a decoupling capacitor layout 129.

The PVT tuning capacitor bank layout 121 corresponds to the boundaries of the active area (e.g., transistor layout and/or capacitor size) of the PVT tuning capacitor bank 111, the coarse tuning capacitor bank layout 122 corresponds to the boundaries of the active area of the coarse tuning capacitor bank 112, and the fine tuning capacitor bank layout 123 corresponds to the boundaries of the active area of the fine tuning capacitor bank 113. Further, the tap buffer layout 128 corresponds to the boundary of the effective area of the tap buffers 118a, 118b, and the TDC latch layout 127 corresponds to the boundary of the effective area of the TDC latch 117. In addition, the regenerative amplifier layout 125 corresponds to the boundary of the effective area of the inverters 116a, 116b, and the decoupling capacitor layout 129 corresponds to the boundary of the effective area of the decoupling capacitor between the power supply and ground of the regenerative circuit 115.

In one embodiment, RTWO segment 100 has a length S of less than about 25 μm _L And a width S of at least about 25 μm _W . In certain embodiments, the RTWO segments 100 have a width that is greater than the length, such that multiple segments may be distributed around the RTWO ring while maintaining a relatively short RTWO conductor ring length and corresponding high oscillation frequency.

In one embodiment, the RTWO comprises at least 1 fragment per 25 μm loop.

Although specific implementations of RTWO segment circuits and floor plan layouts have been described above, the teachings herein apply to various implementations of RTWO segments.

Example of distributed quantized frequency tuning

The segment of the RTWO includes one or more tuning capacitor banks to provide control of the oscillation frequency of the RTWO. For example, RTWO segments may include, for example, PVT tuning capacitor banks, coarse tuning capacitor banks, and/or fine tuning capacitor banks.

The tuning capacitor bank on the RTWO segment can be controlled using a generic tuning code value. For example, a common PVT tuning code may be used to control the PVT tuning capacitor bank of each segment. Likewise, a common coarse tuning code may be used to control the coarse tuning capacitor bank of each RTWO segment, and a common fine tuning code may be used to control the fine tuning capacitor bank of each RTWO segment.

When the tuning capacitor bank is controlled in this way, the RTWO segments each provide substantially the same amount of tuning capacitance, and the value of the tuning capacitance can be controlled by incrementing or decrementing the tuning capacitance code to achieve the desired RTWO oscillation frequency. In such a configuration, the tuning capacitance value of the segment changes in a lockstep manner.

While implementing RTWO segments in this manner may provide a well-controlled and uniform transmission line characteristic impedance for RTWO, implementing RTWO segments in this manner results in relatively poor step sizes for frequency tuning. For example, in an RTWO implemented with N segments, the LSB capacitance step of the RTWO corresponds to the LSB tuning capacitance of the segment multiplied by the N segments. In one example, the LSB tuning capacitance in each of the 32 segments is 18.5fF, and the LSB capacitance step size of RTWO corresponds to 32 x 18.5fF, as all 32 segments switch together. Furthermore, if the frequency step due to each LSB tuning capacitance is 16MHz, the LSB frequency step of RTWO is 32 x 16MHz, which corresponds to a relatively large value of 512 MHz.

However, relatively large frequency steps may not be suitable for high performance RTWO, such as RTWO providing digitally controlled oscillation and time-to-digital conversion functions in high speed applications.

Although the size of the LSB capacitors in each segment may be reduced by a factor of N to provide finer LSB capacitance steps, reducing the capacitance in this manner may not be feasible. For example, limitations of processing techniques and/or design rules may limit the minimum geometry of the device and/or structure, and thus may not result in a tuning capacitor having a relatively small capacitance value.

In certain configurations herein, a distributed quantization scheme is provided for tuning the frequency of an RTWO. The RTWO includes segments distributed around the RTWO ring, and the segments include tuning capacitors, regeneration circuits, and other circuits. Distributed quantized frequency tuning is used to control tuning capacitors in RTWO segments using individually controllable code values, thereby enhancing the frequency step or resolution of the RTWO. Furthermore, in a configuration comprising multiple RTWO rings that lock onto each other to reduce phase noise, distributed quantized frequency tuning may be used to place tuning capacitors on the multiple RTWO rings, respectively, that are coupled to each other. Thus, distributed quantization tuning may be used not only between segments of an RTWO ring, but also between segments of two or more RTWO rings.

Thus, rather than controlling the tuning capacitor banks of each segment with a common tuning code, at least some of the tuning capacitors in the segments are quantized. Thus, tuning capacitors of RTWO segments may be activated individually and the corresponding tuning capacitors between different segments need not be turned on simultaneously. Thus, RTWO operates with finer frequency steps for frequency tuning.

Figures 8A-8R illustrate an RTWO tuning capacitor sequence for PVT tuning according to one embodiment.

The RTWO tuning sequence depicts an annotated RTWO to show the number of active PVT tuning capacitors in a particular segment, since the value of the tuning code is incremented, starting from the lowest value of the PVT code. For clarity of description, the lowest value of the PVT code is selected to be zero and corresponds to the smallest value of the PVT tuning capacitance. However, the tuning code may be implemented in various ways.

The RTWO tuning sequence is shown in the context of an RTWO with 32 segments, each segment comprising a PVT tuning capacitor bank for compensating temperature, process and/or supply voltage variations. Furthermore, the PVT tuning capacitor bank is 3 bits in this example, resulting in 96 tuning capacitors for PVT compensation. Although one specific example having 32 segments and 96 tuning capacitors is provided, the teachings herein are applicable to a wide variety of RTWO's, including but not limited to RTWO's having more or fewer segments and/or more or fewer tuning capacitors.

Although described in the context of PVT tuning, the distributed quantization tuning scheme of fig. 8A-8R may be used for other types of RTWO tuning capacitor banks, including, for example, coarse tuning and/or fine tuning.

Fig. 8A shows a first PVT tuning configuration 201 with PVT code 0 wherein all PVT tuning capacitors are turned off.

Fig. 8B shows a second PVT tuning configuration 202 in which the PVT code is incremented relative to the first PVT tuning configuration 201 of fig. 8A. As shown in fig. 8B, increasing the tuning capacitor code to a value of 1 results in a segment of the tuning capacitor being activated.

Activating the tuning capacitors one segment at a time results in a relatively small change in the frequency step. For example, the capacitance change Δc along the RTWO ring corresponds to the LSB tuning capacitance CLSB of the tuning capacitor bank of the segment. Thus, the frequency change Δf of RTWO corresponds to the LSB tuning capacitance C _LSB LSB frequency step f of (b) _LSB . In one example, when the LSB tuning capacitor has a value of 18.5fF and the corresponding frequency step is 16MHz, the LSB tuning of RTWO is electricallyThe capacity is about 18.5fF and the frequency step size of RTWO is about 16MHz.

As shown in fig. 8C, a third PVT tuning configuration 203 is shown for increasing the PVT code to 2. In the example shown, eight segments of tuning capacitors separate from the first segment are activated. This in turn results in twice the LSB capacitance change (2×c _LSB ) And twice the frequency step change (e.g., 2*f) _LSB )。

In fig. 8D, a fourth PVT tuning configuration 204 is shown for increasing the PVT code to 3. As shown in fig. 8D, the third segment, which is located at eight segments separated from the second segment, is increased by 1, resulting in LSB capacitance change (3*C _LSB ) About three times the frequency step change (e.g., 3*f) _LSB )。

The algorithm may be repeated as shown in fig. 8E-8Q. Fig. 8E shows a fifth PVT tuning configuration 205 in which the PVT code is 4. Fig. 8F shows a fifth PVT tuning configuration 206 wherein the PVT code is 5. Fig. 8G shows a seventh PVT tuning configuration 207 wherein the PVT code is 6. Fig. 8H shows an eighth PVT tuning configuration 208 in which the PVT code is 7. Fig. 8I shows a ninth PVT tuning configuration 209 wherein the PVT code is 8. Fig. 8J shows a tenth PVT tuning configuration 210 wherein the PVT code is 9. Fig. 8K shows an eleventh PVT tuning configuration 211 in which the PVT code is 10. Fig. 8L shows a twelfth PVT tuning configuration 212 wherein the PVT code is 11. Fig. 8M shows a thirteenth PVT tuning configuration 213 in which the PVT code is 12. Fig. 8N shows a fourteenth PVT tuning configuration 214 in which the PVT code is 13. Fig. 8O shows a fifteenth PVT tuning configuration 215 in which the PVT code is 14. Fig. 8P shows a sixteenth PVT tuning configuration 216 wherein the PVT code is 15. Fig. 8Q shows a seventeenth PVT tuning configuration 217 wherein the PVT code is 16.

As shown in fig. 8Q, half of the segments include activated capacitors. As the PVT code is further incremented, the additional capacitor may be activated in a similar manner as previously described.

In fig. 8R, an eighteenth PVT tuning configuration 218 is shown, wherein the PVT code is 32 and each segment includes an active capacitor.

The order in which tuning capacitors of the RTWO segments are activated around the RTWO loop may be selected to reduce or minimize RTWO imbalance due to the distribution of segment selections around the loop. In one embodiment, the RTWO has a rectangular layout and is one segment on each of the bottom (e.g., south), left (e.g., west), top (e.g., north), and right (e.g., east) sides of the PVT selection ring, which has an order of four consecutive PVT codes, e.g., PVT codes 1 through 4.

In some implementations, the selection order is such that the next selected capacitor in the code order is on a different side of the RTWO than the last selected capacitor.

In the example shown, the selected capacitors are separated from each other by equidistant (e.g., 32/4=8) segments when incrementing from PVT code 1 to 4. In addition, for PVT codes 5 to 8, a segment at the center point of each of the south, west, north, and east sides is selected. In this case, the selected segments are 3 segments equidistant from the segments selected for PVT codes 1 to 4 and 8 segments equidistant from each other.

The tuning sequence for selecting segments around the RTWO ring continues for codes 9 to 16, wherein the segments of PVT codes 9 to 16 are equidistant by 1 segment from the segments selected for PVT codes 5 to 8 and by 8 segments from each other.

The selection algorithm continues for PVT codes 17 to 32, where eventually the capacitor from each segment is selected for code 32.

In some implementations, when the PVT code 32 arrives, the segment selection order repeats and the segment selected for PVT code 1 is selected for PVT code 33. However, for the PVT code 33, the PVT tuning capacitor bank is incremented such that 2 capacitors are activated. Thus, the selection algorithm continues for PVT codes exceeding 32 to the maximum value of PVT codes.

Although described in the context of PVT tuning, the tuning scheme is applicable to other tuning capacitor banks. For example, in another embodiment, quantization techniques are applied to coarse tuning capacitor banks.

Two or more RTWO rings may be coupled to each other to reduce phase noise. For example, when two RTWO rings are coupled, the phase noise of the resulting oscillator may be about 3dB less than the phase noise of each RTWO ring alone. Further reduction of phase noise can be achieved by coupling three or more RTWO rings. For example, coupling four RTWO rings may reduce noise by about 6dB.

Fig. 9A-9J illustrate an RTWO tuning capacitor sequence for fine integer tuning according to one embodiment. The RTWO tuning sequence depicts four coupled RTWO rings annotated to show the number of active fine integer tuning capacitors in a particular segment of a particular RTWO ring, since the value of the fine integer tuning code is incremented starting from the lowest value of the fine integer tuning code. For clarity of description, the lowest value of the fine integer tuning code is selected to be zero and corresponds to the minimum value of the fine integer tuning capacitance. However, the tuning code may be implemented in various ways.

In the illustrated embodiment, the RTWO rings are coupled using phase lock conductors that electrically connect the RTWO rings to each other. Although one example of phase locking is shown, the RTWO loop may be coupled in various ways.

The RTWO tuning sequence is shown in the context of four coupled RTWO rings, each ring having 32 segments. In addition, in this example, the fine integer tuning capacitor bank for each RTWO segment is 31 bits, yielding 3,968 tuning capacitors. Although one specific example is provided having 4 rings, 32 segments, 31 bits, and 3,968 tuning capacitors, the teachings herein are applicable to a wide variety of RTWO including, but not limited to, more or fewer coupled RTWO rings, more or fewer segments, more or fewer bits, and/or more or fewer tuning capacitors.

Although described in the context of fine tuning, the distributed quantization tuning scheme of fig. 9A-9J may be used with other types of RTWO tuning capacitor banks, including, for example, coarse tuning and/or PVT tuning.

Fig. 9A shows a first fine tuning configuration 301 with fine tuning code 0, wherein all fine tuning capacitors are turned off.

Fig. 9B shows a second fine tuning configuration 302 with fine tuning code 1. As shown in fig. 9B, incrementing the fine tuning code results in activating the tuning capacitor (in this example, the lower left loop) of a segment of an RTWO loop).

Activating tuning capacitors of one segment of an RTWO ring at a time achieves relatively fine steps.

For example, if each tuning capacitor of each RTWO segment has a value of 1.5fF, activating the tuning capacitor in this way provides an LSB tuning capacitance C of 1.5 fF/4=0.375 fF for the RTWO _LSB . In some processes, such as a fine line CMOS process, a capacitance of 0.375fF provides finer capacitance resolution relative to the smallest independently tunable LSB capacitor that can be fabricated using the process. In addition, in an implementation where 1.5fF corresponds to a frequency step of 800kHz, when tuned in this manner, RTWO operates with a LSB frequency step f of 200kHz _LSB And (3) operating. Conversely, if the tuning capacitors of each segment of each RTWO are turned on in common, the LSB step size will be about 25.6MHz when all segments of all loops are tuned simultaneously.

Thus, in the illustrated embodiment, fine integer tuning is quantized over multiple RTWO rings.

Fig. 9C shows a third fine tuning configuration 303 with fine tuning code 2. As shown in fig. 9C, incrementing the fine tuning code results in activating the tuning capacitor (in this example, the lower right loop) of a segment of an RTWO loop). In the example shown, the second selected tuning capacitor is located in a line symmetrical (or mirrored) position with respect to the first selected tuning capacitor. Activating the second selected tuning capacitor results in approximately a double change in LSB capacitance and approximately a double frequency step.

Fig. 9D shows a fourth fine tuning configuration 304 with fine tuning code 3. Adding fine tuning code results in the activation of a tuning capacitor of a segment of an RTWO ring (in this example the upper right ring).

Fig. 9E shows a fifth fine tuning configuration 305 with fine tuning code 4. Adding fine tuning code results in the activation of a tuning capacitor of a segment of an RTWO ring (in this example the upper left ring).

As shown in fig. 9A-9E, incrementing the fine tuning code to a value range of 0 to 4 results in the capacitor being activated in one segment of each RTWO. Thus, for continuous fine frequency tuning codes, a particular one of the RTWO rings has at most one additional active capacitor relative to the other RTWO rings.

Activating the tunable capacitor in this way keeps the free oscillation frequency of each RTWO ring substantially the same as each other. Thus, the fine integer code may be incremented or decremented while maintaining the lock between the RTWO rings.

As shown in fig. 9F-9I, the algorithm continues. Fig. 9F shows a sixth fine tuning configuration 306, wherein the fine tuning code is 5. Fig. 9G shows a seventh fine tuning configuration 307, wherein the fine tuning code is 6. Fig. 9H shows an eighth fine tuning configuration 308, wherein the fine tuning code is 7. Fig. 9I shows a ninth fine tuning configuration 309, wherein the fine tuning code is 8.

In fig. 9J, a tenth fine tuning configuration 310 is shown, wherein the fine code is 128 and each segment of each RTWO includes an active capacitor. The selection algorithm continues for fine codes exceeding 128 up to a maximum of fine codes. Thus, the tuning capacitor selection is distributed over four RTWO rings up to the total number of fine integer tuning capacitors, in this particular example 31 capacitors per segment x 32 segments x 4 rings = 3968 tuning capacitors. Although the illustrated example uses 3968 to tune the capacitor operation, other implementations are possible.

Although various examples of distributed quantization tuning have been described, distributed quantization tuning may be applied to RTWO implemented in various ways. For example, an RTWO may include one or more loops of various shapes and sizes, and an RTWO may include fragments that are implemented in a variety of ways. Thus, the teachings herein are applicable to RTWO implemented in a variety of ways.

Example of decoding of a slice for a rotary traveling wave oscillator

In some configurations herein, a segmented decoding scheme is provided for RTWO frequency tuning codes to reduce decoding complexity. The segment decoding scheme may operate using a combination of global decoding and local decoding to process the frequency tuning code. By using segment decoding, multiple signal paths associated with a frequency tuning code may be reduced.

RTWO can operate with a large number of tuning capacitors, including tuning capacitors for PVT tuning, coarse tuning, and fine tuning (including, for example, fine integer and fine fraction tuning). In embodiments using multiple loops coupled to each other to reduce phase noise, the number of tuning capacitors may be further increased. A large number of tuning capacitors may result in a large number of signal paths or wires.

In one example, a 4-ring RTWO includes 32 segments per ring, each segment including a PVT tuning capacitor bank having 2 bits, a coarse tuning capacitor bank having 3 bits, and a fine integer tuning capacitor bank having 5 bits. In addition, each loop includes one example of a fine fraction tuning capacitor bank having 5 bits. In this example, without segment decoding, the PVT tuning capacitor bank operates with 256 lines (2 bits by 32 segments by 4 rings), the coarse tuning capacitor bank operates with 384 lines (3 bits by 32 segments by 4 rings), the fine integer tuning capacitor bank operates with 640 lines (5 bits by 32 segments by 4 rings), and the fine fractional tuning capacitor bank operates with 20 lines (5 bits by 4 rings). Thus, the number of buses in this example may be 256+384+640+20=1300 lines.

Routing a large number of wires, however, can lead to routing congestion. Furthermore, these routes may lead to the electrical environment being potentially coupled with the RTWO by digital spurious components. For example, a large number of wires may act as a large antenna on a semiconductor chip. Furthermore, the flexibility and/or scalability of RTWO designs may be limited. For example, such routing congestion may limit the maximum number of RTWO rings that can be coupled to each other to improve phase noise.

In some configurations herein, tuning capacitors on RTWO segments are quantized such that the tuning capacitor of each RTWO segment can be controlled separately from the tuning capacitors of the other segments. In addition, the global decoder processes the frequency tuning codes (e.g., PVT tuning codes, coarse tuning codes, and/or fine integer tuning codes) to generate input codes for the local decoder of the RTWO. In some implementations, thermometer decoding is performed locally for each segment by a local decoder. In a multi-ring implementation, the frequency tuning code may be routed to a global decoder associated with each RTWO ring.

By using a segmented decoding scheme, many metal routes or wires can be reduced.

For example, in the specific example above, 1300 lines are used for a 4-ring RTWO, which operates without segment decoding. In contrast, segment decoding in this particular example can be used to provide 7-bit PVT tuning (e.g., 3 thermometer bits per segment 32 segments = 96 LSBs<27 8-bit coarse tuning (e.g., 7 thermometer bits per segment x 32 segments = 224 LSB)<2 ⁸ ) And 12-bit fine integer tuning (e.g., 31 thermometer bits per segment 32 segments 4 rings = 3968 LSB)<2 ¹² ). Thus, PVT tuning operates with 28 lines (7-bit 4-ring), coarse tuning with 32 lines (8-bit 4-ring), and fine integer tuning with 48 lines (12-bit 4-ring). Thus, the number of buses in this example may be 28+32+48+20=128 lines, which is about an order of magnitude smaller than an implementation without segment decoding.

Fig. 10 illustrates one embodiment of an RTWO 400 with segment decoding. In some configurations herein, segment decoding is provided to reduce multiple lines routed to the RTWO, such as multiple digital signal routes from the ADPLL core to the RTWO.

RTWO 400 includes differential transmission lines connected in a closed loop or ring. The differential transmission line comprises a first conductor 31, a second conductor 32 and a crossover 33.REDWO400 also includes fragment 100, which may be as previously described with respect to FIG. 7. In the illustrated embodiment, thirty-two instances of segment 100 are located around a ring, with eight segments on each side of the ring. As shown in fig. 10, 32 fragments are marked with an index between 0 and 31.

RTWO 400 also includes a global decoder system 401, a local decoder system 402, a digital routing bus 405, a serial interface 406, and a fine fraction tuning capacitor bank 410.

Although one particular RTWO implementation is shown, the teachings herein are applicable to RTWO implemented in a variety of ways, including, but not limited to, RTWO with different ring implementations, different segment implementations, and/or different decoder implementations.

Global decoder system 401 includes a segment decoder system 403 and a tuning decoder system 404. Global decoder system 401 may be implemented using digital logic circuits, such as digital logic generated by digital synthesis. For example, the segment decoder system 403 and/or the tuning decoder system 404 may be described using a hardware description language such as Verilog, which may be synthesized to generate digital logic circuits. However, other implementations are also possible. Although shown distributed for each segment, one or more decoders may be configured to provide decoding to multiple segments. For example, one decoder may be used per RTWO side, as shown in fig. 11.

The tuned decoder system 404 is used to decode frequency tuning codes (e.g., PVT, coarse tuning, and/or fine integer tuning codes) to generate input codes to the local decoder system 402. The input code is processed by the local decoder system 402 to activate the appropriate tuning capacitance of the RTWO segment.

In the illustrated embodiment, the tuning decoder system 404 includes a Tuning Decoder (TD) for each segment 100. In addition, the local decoder system 402 includes a Local Decoder (LD) for each segment 100. In some implementations, the LD is used to convert binary input codes from the corresponding TDs to thermometer coded output codes for selecting a plurality of active tuning capacitors 100 for a particular RTWO segment.

As shown in fig. 10, the digital routing bus 405 surrounds the perimeter of the RTWO 400. Digital routing bus 405 may be used to route various input signals to global decoder system 401.

For example, the global decoder system 4101 of RTWO 400 has been annotated to show input signals 411-412 for frequency tuning, including PVT tuning codes (pvt_code <6:0 >), coarse tuning codes (coarse_code <7:0 >), fine integer tuning codes (fine int_code <7:0 >) and fine fraction tuning codes (fine frac_code <2:0 >). Although not shown in fig. 10 for clarity, RTWO 400 may receive one or more clock signals that indicate the timing of the tuning code.

In the illustrated embodiment, digital routing bus 405 provides tuning decoder system 404 with PVT tuning codes, coarse tuning codes, and fine integer tuning codes, which tuning decoder system 404 processes to generate input codes to control local decoder system 402. The local decoder system 402 processes the input code to control the PVT tuning library, coarse tuning library, and fine integer tuning library of the RTWO segment 100.

As shown in fig. 10, one example of a fine fraction tuning library 410 is included in the RTWO400 shown, and a fine fraction tuning code (fine frac_code <2:0 >) is provided to the fine fraction tuning library 410 to control fine fraction tuning. Thus, in this example, the fine fraction tuning code bypasses the tuning decoder system 404. In some implementations, an LD is included to decode the fine fraction tuning code to generate a thermometer to control the fine fraction tuning library 410.

While one particular implementation of frequency tuning code and decoding is shown, the teachings herein are applicable to a wide variety of implementations.

The segment decoder system 403 includes a Segment Decoder (SD) for each segment 100. The segment decoder system 403 is used to decode data received via the serial interface 406 to the segment 100 of the RTWO.

As shown in FIG. 10, serial interface 406 receives input signals 413, input signals 413 including segment data signals (rtwo_seg_data <7:0 >), segment address signals (rtwo_seg_addr <4:0 >), write enable signals (rtwo_wr_en), serial interface clock signals (rtwo_sclk), and read data signals (rtwo_rd_data <7:0 >). In some implementations, serial interface 406 is implemented as a local Serial Peripheral Interface (SPI).

In the illustrated embodiment, digital routing bus 405 routes input signal 413 to each SD of segment decoding system 403 for decoding.

It may be desirable that a fragment of an RTWO (e.g., RTWO fragment 100) be configurable. To provide configurability, the RTWO segments 100 can be written or read via the serial interface 406.

The illustrated RTWO 400 includes a segment decoder system 401 that reduces the multiple routes associated with the communication with the RTWO segments 100. In some implementations, the segment decoder system 403 operates using a local register map. The local register map is used to provide a bit address for each segment and to determine when the serial interface 406 is in communication with a particular one of the RTWO segments 100.

By including the segment decoder system 401, the plurality of data and address bus bits associated with routing from the serial interface 406 to the RTWO segment 100 may be reduced.

For example, in one particular implementation, a 4-ring RTWO with 32 segments per ring includes a data bus that uses 8 bit operations common to the 4 rings, and an address bus that uses 5 bit operations common to the 4 rings. In such an example, the 4-ring RTWO operates with 13 bits and wires.

In contrast, a similar 4-ring RTWO implemented with a segment decoder system may include 2048 bits and lines (16 bits per segment x 32 segments x 4 rings). Thus, by including a segment decoder system in this particular example, a one hundred fold reduction may be achieved.

Additional details of the segment decoder system 403 may be discussed below with reference to fig. 14-15.

Fig. 11 shows an embodiment of a tuned decoder for a multi-ring RTWO 600. Polycyclic RTWO 600 includes southwest RTWO ring 601 (R0), southeast RTWO ring 602 (R1), northeast RTWO ring 603 (R2), and northwest RTWO ring 604 (R3). Although a configuration using four rectangular RTWO rings is shown, the teachings herein are applicable to embodiments using more or fewer rings and/or rings implemented with other shapes.

Although terms related to basic directions (north, south, east, west, northeast, northwest, southeast, southwest) are used to describe a multi-ring RTWO, one of ordinary skill in the art will understand that these terms are used herein to understand relative directions and not to refer to true directions. For example, the multi-ring RTWO 600 is typically implemented at least in part on an Integrated Circuit (IC) or semiconductor die, and the orientation of the multi-ring RTWO 600 changes as the IC changes position or angle. Similarly, terms associated with the top, bottom, left and right sides are used to describe relative directions.

As shown in fig. 11, PVT tuned decoders, coarse tuned decoders, and fine integer tuned decoders are provided around the sides of each RTWO ring 601-604.

With respect to northwest RTWO ring 604, northwest PVT decoder 614a, northwest coarse decoder 624a, and northwest fine integer decoder 634a are located on a first or top side. In addition, the south PVT decoder 614b, the south coarse tuning decoder 624b, and the south fine integer decoder 634b are located on a second or bottom side. Further, the west PVT decoder 614c, the west coarse decoder 624c, and the west fine integer decoder 634c are located on the third side or left side. In addition, the east PVT decoder 614d, the east coarse decoder 624d, and the east fine integer decoder 634d are located on the fourth side or right side.

In addition, the orientation of the corresponding tuning decoder of northeast RTWO ring 603 is line symmetric with respect to northwest RTWO ring 604. For example, relative to northeast RTWO ring 603, north PVT decoder 613a, north coarse decoder 623a, and north fine integer decoder 633a are located on the top side. In addition, the south PVT decoder 613b, the south coarse decoder 623b, and the south fine integer decoder 633b are located at the bottom side. Further, the west PVT decoder 613c, the west coarse decoder 623c, and the west fine integer decoder 633c are located on the right side. In addition, the east PVT decoder 613d, the east coarse decoder 623d, and the east fine integer decoder 633d are located on the left side.

Furthermore, the orientation of the corresponding tuning decoder of southwest RTWO ring 601 is line symmetric with respect to northwest RTWO ring 604. For example, relative to southwest RTWO ring 601, north PVT decoder 611a, north coarse decoder 621a, and north fine integer decoder 631a are located on the bottom side. In addition, the south PVT decoder 611b, the south coarse decoder 621b, and the south fine integer decoder 631b are located on the top side. Further, the west PVT decoder 611c, the west coarse decoder 621c, and the west fine integer decoder 631c are located on the left side. In addition, the east PVT decoder 611d, the east coarse decoder 621d, and the east fine integer decoder 631d are located on the right side.

In addition, the directions of the respective tuning decoders of the southeast RTWO ring 602 are line symmetric with respect to the southwest RTWO ring 601 and the northeast RTWO ring 603. For example, relative to southeast RTWO ring 602, north PVT decoder 612a, north coarse tuning decoder 622a, and north fine integer decoder 632a are located on the bottom side. In addition, the south PVT decoder 612b, the south coarse tuning decoder 622b, and the south fine integer decoder 632b are located on the top side. Further, the west PVT decoder 612c, the west coarse decoder 622c, and the west fine integer decoder 632c are located on the right side. In addition, the east PVT decoder 612d, the east coarse decoder 622d, and the east fine integer decoder 632d are located on the left side.

Implementing a tuned decoder of one RTWO ring with line symmetry provides symmetry that reduces mismatch between rings relative to a tuned decoder of another RTWO ring.

In the embodiment shown, a tuning decoder is placed on each side of the RTWO ring. In addition, the tuning decoder controls the tuning capacitor of adjacent RTWO segments, which reduces the connection between the output of the tuning decoder and the RTWO segments. For example, in an implementation where each RTWO ring has 32 segments, the north-tuning decoder provides decoding to 8 corresponding segments of the RTWO ring. Thus, the route length is reduced. Thus, the shown tuning decoder may show a set of TD blocks as shown in fig. 10. However, other implementations are also possible. For example, separate TD blocks may be provided for each RTWO segment.

As shown in fig. 11, PVT tuning decoders of RTWO rings 601-604 are represented by text labels pvt_decoder_north, pvt_decoder_west, pvt_decoder_south, and pvt_decoder_east. In addition, the coarse tuning decoder is represented by the text labels coarse_decoder_north, coarse_decoder_west, coarse_decoder_south, and coarse_decoder_east. In some implementations, the PVT tuning decoder is substantially the same for each of the RTWO rings and segments, and the PVT tuning decoder operates with common PVT tuning codes. In addition, in some implementations, the coarse tuning decoder is substantially the same for each of the RTWO rings and segments, and the coarse tuning decoder operates with a common coarse tuning code.

In one embodiment, the PVT and/or coarse tuning decoder utilizes a distributed quantization tuning operation, as previously discussed with respect to FIGS. 8A-8R.

As shown in fig. 11, the fine integer tuning decoders of RTWO rings 601-604 label text labels fine int_decoder_r0_north, fine int_decoder_r0_west, fine int_decoder_r0_south, fine int_decoder_r0_east, fine int_decoder_r1_north, fine int_decoder_r1_west, fine int_decoder_r1_south, fine int_decoder_r1_east, fine int_decoder_r2_north, fine int_decoder_r2_west, fine int_decoder_r2_south, fine int_decoder_r2_east, fine int_decoder_r3_north, fine int_decoder_r3_west, fine int_decoder_r3_south, and fine int_decoder_r3_east.

In some implementations, the fine integer tuning decoder is implemented using substantially the same hardware (e.g., substantially the same Verilog), but with a different rtwo_position <3: a 0> value operates and thus has a different output value. Implementing the decoder in this manner enhances scalability and flexibility.

In one embodiment, the fine integer tuning decoder operates with distributed quantized tuning of the tuning code across segments and loops, as previously discussed with respect to fig. 9A-9J. A separate fine integer tuning decoder is provided that can be fine tuned on each RTWO segment as well as on each RTWO ring. This in turn facilitates the individual control of each tuning element of each segment of each RTWO ring. Thus, in some implementations, fine integer tuning is performed across each RTWO segment and across each RTWO ring.

Although fig. 11 illustrates one embodiment of a tuned decoder for a multi-ring RTWO, the tuned decoder may be implemented in a variety of ways.

Fig. 12 shows an embodiment of an RTWO tuning decoder 700. Multiple instances of the RTWO tuning decoder 700 may be located along the RTWO side. For example, RTWO tuning decoder 700 illustrates one implementation of the tuning decoder of FIG. 11 located on one side of an RTWO ring.

In the depicted embodiment, RTWO tuning decoder 700 includes PVT tuning decoder 701, coarse tuning decoder 702, and fine integer tuning decoder 703.

As shown in fig. 12, PVT tuning decoder 701 receives PVT tuning code (pvt_code <6:0 >) and location code (rtwo_location <3:0 >) and generates segment PVT tuning code (pvt_tuning 0<1:0>,... The segment PVT tuning codes are used by a Local Decoder (LD) of the respective segment to control the selection of PVT tuning capacitors.

The coarse tuning decoder 702 of fig. 12 receives the coarse tuning code (coarse_code <7:0 >) and the location code (rtwo_location <3:0 >) and generates a segment coarse tuning code (coarse_tuning 0<2:0>,... The segment coarse tuning code is used by the LD of the corresponding segment to control the selection of coarse tuning capacitors.

As shown in fig. 12, the fine integer tuning decoder 703 receives a fine integer tuning code (fine int_code <11:0 >), a position code (rtwo_position <3:0 >), an LSB offset code (offset_lsb <1:0 >), an offset position code (offset_position <2:0 >) and a test mode code (test_mode <1:0 >), and generates a segment fine integer tuning code (fine int_tuning 0<4:0>,... The segment fine integer tuning code is used by the LD of the corresponding segment to control the selection of the fine integer tuning capacitor.

Multiple instances of the RTWO tuning decoder 700 may be located along the sides of the RTWO rings 601-604 of fig. 11, and a position code (rtwo_position <3:0 >) may be used to control the response of the tuning decoder to a particular tuning code value. In one embodiment, the selected tuned decoder positions for the different values of the position code (rtwo_positions <3:0 >) are given in table 1 below.

TABLE 1

In some implementations, when a tuning decoder is instantiated at a particular location around the RTWO ring, the address of the particular tuning decoder is hardwired.

The tuning decoder located around the RTWO ring decodes PVT tuning codes (pvt_code <6:0 >), coarse tuning codes (coarse_code <7:0 >) and fine integer tuning codes (fine int_code <11:0 >). The tuning code represents the total number of tuning capacitors in the RTWO to be activated or selected.

In the illustrated embodiment, each tuning decoder generates segment tuning codes for a plurality of RTWO segments. For example, PVT tuning decoder 701 outputs segment PVT tuning codes for 8 RTWO segments (pvt_tuning 0<1:0>,... In addition, the coarse tuning decoder 702 outputs segment coarse tuning codes (coarse_tuning 0<2:0>,) for 8 RTWO segments, coarse_tuning 7<2:0 >). Further, the fine integer tuning decoder 703 outputs segment fine integer tuning codes (fine int_tuning 0<4:0>,... Although the tuning decoder shown outputs segment tuning codes for eight segments, other implementations are possible.

In the illustrated embodiment, the output of the tuning decoder is represented as a binary representation of the tuning capacitors selected for each tuning capacitor bank. The respective Local Decoder (LD) is for processing the output of the tuning decoder to control the selection of tuning capacitors for the respective segments. In some implementations, the LD generates a thermometer code for each tuning capacitor bank based on the binary output of the tuning decoder.

In one example, the PVT tuning capacitor bank for each segment includes 3 PVT capacitors represented by 2 binary bits, and the LD processes the 2 binary bits to generate a thermometer code for controlling the selection of the 3 PVT capacitors. In another example, the coarse tuning harmonic library for each segment includes 7 coarse tuning capacitors represented by 3 binary bits, and the LD processes the 3 binary bits to generate a thermometer code for controlling the selection of the 7 coarse tuning capacitors. In yet another example, the fine integer tuning memory bank has 31 capacitors represented by 5 binary bits, and the LD processes the 5 binary bits to generate a thermometer code for controlling the selection of the 31 capacitors.

In the illustrated embodiment, the fine integer tuning decoder 703 also receives LSB offset codes (offset_lsb <1:0 >), offset position codes (offset_position <2:0 >) and test mode codes (test_mode <1:0 >).

In one embodiment, the test pattern code controls whether fine fraction tuning is quantized across segments and across multiple loops (e.g., as shown in fig. 9 a-9J), or quantized across segments rather than multiple loops. Quantization across segments and across multiple loops provides enhanced tuning resolution.

The LSB offset code (offset_lsb <1:0 >) and offset position code (offset_position <2:0 >) may be used to add multiple offset LSBs to the fine integer tuning code (fine int_code <11:0 >). Advantageously, the offset LSB may be added by tuning the value of the fine integer tuning code, rather than by selecting a tuning capacitor for a particular tuning group. Providing an offset allows compensating for non-linearities on the RTWO ring, wherein capacitive mismatch is particularly likely to occur at segments near corners and/or intersections. Thus, the capacitance mismatch can be compensated by adding an offset digital code to any particular segment taken from any segment of any ring of the RTWO (e.g., for any of the 128 segments of the 4-ring RTWO, each ring has 32 segments). An offset number code is added to the fragment identified by the offset position code (offset_position <2:0 >).

One embodiment of an additional number of LSBs for different values of the LSB offset code (offset_lsb <1:0 >) is given in Table 2 below. However, other implementations are also possible.

TABLE 2

Offset_lsb<1>	Offset_lsb<0>	Additive amount of LSB
			0	0	2
0	1	4
			1	0	6
1	1	10

The LSB offset code (offset_lsb <1:0 >) can also be used to evaluate the sensitivity of the multi-ring RTWO to mismatches in any segment. Thus, the LSB offset code (offset_lsb <1:0 >) can be used as a powerful investigation tool to evaluate the quality of RTWO physical layout. For example, by programming a digital code, 2, 4, 6, or 10 LSBs can be added to any of the 128 segments in an RTWO without the use of an additional fixed tuning capacitor in each RTWO segment.

One embodiment of selected fragments for different values of the offset position code (offset_position <2:0 >) is given in table 3 below. However, other implementations are also possible.

TABLE 3 Table 3

The LSB offset code (offset_lsb <1:0 >) and offset position code (offset_position <2:0 >) may be used to write the desired number of LSBs to any segment of RTWO. In some embodiments, the offset is provided via a segment decoder system (e.g., the segmented digital addressing system of fig. 14) rather than via a decoder. For example, with respect to the embodiment of fig. 10, SPI interface 406 may be used to write a desired number of LSBs to a particular fragment.

In one embodiment, the offset LSB of the random or pseudo-random number is written periodically when the RTWO is operational. The process of writing a random number of offset LSBs can be done at any speed, while RTWO oscillates at its fundamental frequency. By implementing RTWO in this way, the linearity of RTWO is improved by randomizing mismatch in the fine integer tuning capacitor. For example, the LSB offset code (offset_lsb <1:0 >) and offset position code (offset_position <2:0 >) may be used to provide dynamic tuning of the capacitance value of the segment, thereby providing a linearized fine tuning gain characteristic.

Although fig. 12 illustrates one embodiment of an RTWO tuned decoder, the RTWO tuned decoder may be implemented in a variety of ways.

Examples of algorithms for tuning the decoder system are provided below. When implementing a tuned decoder using the embodiment shown in fig. 12, a tuned decoding algorithm may be used to implement the tuned decoder of the multi-loop RTWO700 of fig. 11. In some configurations, a hardware description language describing the algorithm may be synthesized to generate digital logic. However, other implementations are also possible.

Although a particular tuned decoder algorithm is described, the teachings herein apply to a variety of tuned decoding algorithms.

The tuning decoder may be implemented to map binary tuning codes (e.g., pvt_code <6:0>, coarse_code <7:0> and fine int_code <11:0 >) to segments of the RTWO.

In one example, the PVT tuning and coarse tuning algorithms are implemented with different maximum code values (e.g., 96 codes for PVT and 224 codes for coarse tuning), but otherwise are substantially the same.

Thus, while the following examples focus on quantized PVT tuning, coarse tuning algorithms may be implemented in a similar manner.

As the PVT code increases, the calculation described by the following hardware description language (hereinafter referred to as "hardware description 1") determines which of the four sides (west, south, east, and north) of the RTWO ring is selected. Once a side is selected, the algorithm sets the segment on that side. When the PVT code is incremented by 1, the offset numbers 1, 2, 3, and 4 select one of the west, south, east, or north sides of the RTWO.

pvt_seg_counter_west=mod (pvt_code, 32) -1

pvt_seg_counter_nan=mod (pvt_code, 32) -2

pvt_seg_counter_east=mod (pvt_code, 32) -3

pvt_seg_counter_north=mod (pvt_code, 32) -4

Modulus 32 represents the cycle through 32 segments in an RTWO ring before these calculations are reset back to zero. This corresponds, for example, to when all 32 fragments within an RTWO ring transmit 1LSB (see, e.g., fig. 8R). Thus, when pvt_code=32, all PVT tuning capacitors in each segment will have a capacitance of 1LSB, when pvt_code=2×32, all PVT tuning capacitors in each segment will have a capacitance of 2LSB, and pvt_code=3×32, all PVT tuning capacitors in each segment will have a capacitance of 3 LSB.

The above calculation is used as an input of the block counter calculation described in the following hardware description language (hereinafter referred to as "hardware description 2"). As described in hardware description 2, the block counter is incremented by 1 for every 4 codes of the pvt_seg_counter. This indicates that each side of the RTWO ring activates the same number of LSB capacitors, or that the complete cycle of the west, south, east and north sides of the RTWO is complete (in this example, in order). At count 5, the block counter indicates that it is time to go back to the west side of the RTWO and add LSBs at a different piece of that side.

pvt_seg_block_counter_west_decoder=floor (pvt_seg_counter_west/4) +1

pvt_seg_block_counter_south_decoder=floor (pvt_seg_counter_south/4) +1

pvt_seg_block_counter_east_decoder=floor (pvt_seg_counter_east/4) +1

pvt_seg_block_counter_north_decoder=floor (pvt_seg_counter_north/4) +1

The PVT code assigned to each of the 32 segments is calculated by the following hardware description language (hereinafter referred to as "hardware description 3"). In addition, for the first 32 PVT codes, the PVT code assigned to any one of the 32 segments is 1, meaning that 1LSB is added to the tuning capacitor bank in any segment. For the next 32 PVT codes (and so on), the PVT code assigned to any one of the 32 segments is 2, meaning that a 2LSB is added to the tuning capacitor bank in any segment. In this example, the value of pvt_code_assignment is between 1 and 3.

pvt_code_assignment=floor (pvt_code/32) +1

Based on the values of the block counters specified in the hardware description 2, the respective tuning capacitor groups on the west side, the south side, the east side, and the north side of the RTWO ring are set according to the following hardware description language (hereinafter referred to as "hardware description"). Although hardware description 4 only shows the computation of the west tuned decoder, similar computations may be used by the south, east and north decoders. For example, if pvt_seg_block_counter_west_decoder=0 and pvt_code_assignment=1, the PVT codes of the tuning capacitor bank on the RTWO ring west side are all zero and the tuning capacitors are switched. In addition, if pvt_seg_block_counter_west_decoder=1, all PVT except PVT of segment 0 on the west side of RTWO are set to tuning capacitance of 1 or 1 LSB. Furthermore, if pvt_seg_block_counter_west_decoder=2, the PVT codes of segment 0 and segment 4 of the tuning capacitor bank on the west side of the RTWO ring are set to 1. When pvt_seg_block_counter_west_decoder equals 2, the input pvt_code is 5, indicating that after adding LSB on each RTWO 4 side, the block counter returns to the west side of RTWO.

ifpvt_seg_block_counter_west_decoder= 0

pvt_tuning 0=pvt_code_assignment-1

pvt_tuning 1 = pvt_code_assignment-1

pvt_tuning 2=pvt_code_assignment-1

pvt_tuning 3 = pvt_code_assignment-1

pvt_tuning 4 = pvt_code_assignment-1

pvt_tuning 5 = pvt_code_assignment-1

pvt_tuning 6 = pvt_code_assignment-1

pvt_tuning 7 = pvt_code_assignment-1

elseifpvt_seg_block_counter_west_decoder= 1

pvt_tuning 0=pvt_code_assignment

pvt_tuning 1 = pvt_code_assignment-1

pvt_tuning 2=pvt_code_assignment-1

pvt_tuning 3 = pvt_code_assignment-1

pvt_tuning 4 = pvt_code_assignment-1

pvt_tuning 5 = pvt_code_assignment-1

pvt_tuning 6 = pvt_code_assignment-1

pvt_tuning 7 = pvt_code_assignment-1

elseifpvt_seg_block_counter_west_decoder= 2

pvt_tuning 0=pvt_code_assignment

pvt_tuning 1 = pvt_code_assignment-1

pvt_tuning 2=pvt_code_assignment-1

pvt_tuning 3 = pvt_code_assignment-1

pvt_tuning 4 = pvt_code_assignment

pvt_tuning 5 = pvt_code_assignment-1

pvt_tuning 6 = pvt_code_assignment-1

pvt_tuning 7 = pvt_code_assignment-1

elseifpvt_seg_block_counter_west_decoder= 3

pvt_tuning 0=pvt_code_assignment

pvt_tuning 1 = pvt_code_assignment-1

pvt_tuning 2 = pvt_code_assignment

pvt_tuning 3 = pvt_code_assignment-1

pvt_tuning 4 = pvt_code_assignment

pvt_tuning 5 = pvt_code_assignment-1

pvt_tuning 6 = pvt_code_assignment-1

pvt_tuning 7 = pvt_code_assignment-1

elseifpvt_seg_block_counter_west_decoder= 4

pvt_tuning 0=pvt_code_assignment

pvt_tuning 1 = pvt_code_assignment-1

pvt_tuning 2 = pvt_code_assignment

pvt_tuning 3 = pvt_code_assignment-1

pvt_tuning 4 = pvt_code_assignment

pvt_tuning 5 = pvt_code_assignment-1

pvt_tuning 6 = pvt_code_assignment

pvt_tuning 7 = pvt_code_assignment-1

elseifpvt_seg_block_counter_west_decoder= 5

pvt_tuning 0=pvt_code_assignment

pvt_tuning 1 = pvt_code_assignment-1

pvt_tuning 2 = pvt_code_assignment

pvt_tuning 3 = pvt_code_assignment

pvt_tuning 4 = pvt_code_assignment

pvt_tuning 5 = pvt_code_assignment-1

pvt_tuning 6 = pvt_code_assignment

pvt_tuning 7 = pvt_code_assignment-1

elseifpvt_seg_block_counter_west_decoder= 6

pvt_tuning 0=pvt_code_assignment

pvt_tuning 1 = pvt_code_assignment

pvt_tuning 2 = pvt_code_assignment

pvt_tuning 3 = pvt_code_assignment

pvt_tuning 4 = pvt_code_assignment

pvt_tuning 5 = pvt_code_assignment-1

pvt_tuning 6 = pvt_code_assignment

pvt_tuning 7 = pvt_code_assignment-1

elseifpvt_seg_block_counter_west_decoder= 7

pvt_tuning 0=pvt_code_assignment

pvt_tuning 1 = pvt_code_assignment

pvt_tuning 2 = pvt_code_assignment

pvt_tuning 3 = pvt_code_assignment

pvt_tuning 4 = pvt_code_assignment

pvt_tuning 5 = pvt_code_assignment

pvt_tuning 6 = pvt_code_assignment

pvt_tuning 7 = pvt_code_assignment-1

elseifpvt_seg_block_counter_west_decoder= 8

pvt_tuning 0=pvt_code_assignment

pvt_tuning 1 = pvt_code_assignment

pvt_tuning 2 = pvt_code_assignment

pvt_tuning 3 = pvt_code_assignment

pvt_tuning 4 = pvt_code_assignment

pvt_tuning 5 = pvt_code_assignment

pvt_tuning 6 = pvt_code_assignment

pvt_tuning 7 = pvt_code_assignment

endif

Using the PVT tuning algorithm described above, the block counter increments every 4 PVT codes at the input of the decoder. At the end of these 4 PVT codes, 1 LSB is set at fragments 0, 8, 16 and 24. At PVT code 32, the block counter is reset and each of the 32 segments has a tuning capacitance of 1 LSB (all segments are assigned code 1 starting from 0 to 31). At code 33, the block counter starts to increment, while segment 0 has 2LSB. When all 32 fragments have 2 LSBs and the algorithm repeats until the PVT code reaches 96, the algorithm continues until the PVT code 64 is reached.

A fine integer quantization tuning algorithm is provided in the following example. The fine integer quantization tuning algorithm follows a similar approach to the quantized PVT tuning algorithm described above. However, the fine integer quantization tuning algorithm also provides quantization of the tuning code across multiple RTWO rings (4 in this example) and across segments (32 per ring in this example). In contrast, the PVT tuning algorithm described above quantifies across RTWO segments, but not across RTWO loops.

The position of the segment to be selected at one of the west, south, east or north sides of the four RTWO rings when the fine int_code is increased is determined by the computation of the following hardware description language description (hereinafter "hardware description 5").

Fine int_seg_counter_west_r0=mod (fine int_code, 32×4) -1

Fine int_seg_counter_west_r1=mod (fine int_code, 32×4) -2

Fine int_seg_counter_west_r2=mod (fine int_code, 32×4) -3

Fine int_seg_counter_west_r3=mod (fine int_code, 32×4) -4

Fine int_seg_counter_south_r0=mod (fine int_code, 32×4) -5

Fine int_seg_counter_south_r1=mod (fine int_code, 32×4) -6

Fine int_seg_counter_south_r2=mod (fine int_code, 32×4) -7

Fine int_seg_counter_south_r3=mod (fine int_code, 32×4) -8

Fine int_seg_counter_east_r0=mod (fine int_code, 32×4) -9

Fine int_seg_counter_east_r1=mod (fine int_code, 32×4) -10

Fine int_seg_counter_east_r2=mod (fine int_code, 32×4) -11

Fine int_seg_counter_east_r3=mod (fine int_code, 32×4) -12

Fine int_seg_counter_north_r0=mod (fine int_code, 32×4) -13

Fine int_seg_counter_north_r1=mod (fine int_code, 32×4) -14

Fine int_seg_counter_north_r2=mod (fine int_code, 32×4) -15

Fine int_seg_counter_north_r3=mod (fine int_code, 32×4) -16

Offset numbers 1 through 16 in hardware description 5 above select one of the 16 fragments of the 4-ring RTWO because the code is incremented by 1. Modulus 32×4=128 means 128 segments are cycled before the calculation of the reset zero. This corresponds to when all 128 fragments in the 4-ring RTWO transmit 1 LSB. Thus, when fine int_code=128, all fine integer tuning capacitors in each of the 128 segments have a capacitance of 1 LSB. When fine int_code=2×128, all fine integer tuning capacitors in each of the 128 segments have a capacitance of 2LSB, and so on. R0, R1, R2 and R3 represent ring numbers in a 4-ring coupled RTWO, as shown in FIG. 11.

As the fine code (fine int_code) increases, the selected decoder order is shown in table 4 below. This sequence repeats every 16 codes of the fine int_code.

TABLE 4 Table 4

Fine int_code	Decoder
		0	Western, R0
1	Western, R1
		2	Western, R2
3	Western, R3
		4	South, R0
5	South, R1
		6	South, R2
7	South, R3
		8	East, R0
9	East, R1
		10	East, R2
11	East, R3
		12	North, R0
13	North, R1
		14	North, R2
15	North, R3

The computation in the above hardware description 5 is used as an input to the block counter computation set forth in the following hardware description language (hereinafter referred to as "hardware description 6"). As described below, for every 4×4=16 codes of the fine int_seg_counter, the block counter is incremented by 1. This shows that all 16 sides of the 4-ring RTWO have the same number of LSB capacitances and surround a complete cycle on the west, south, east and north sides of each of the 4 RTWO rings. At count 17, the block counter indicates that it is time to go back to the west side of ring number 0 of the RTWO and add LSBs at a different segment of that side.

Fine int_seg_block_counter_west_decoder_r0=floor (fine int_seg_counter_west_r0/(4*4)) +1

Fine int_seg_block_counter_west_decoder_r1=floor (fine int_seg_counter_west_r1/(4*4)) +1

Fine int_seg_block_counter_west_decoder_r2=floor (fine int_seg_counter_west_r2/(4*4)) +1

Fine int_seg_block_counter_west_decoder_r3=floor (fine int_seg_counter_west_r3/(4*4)) +1

Fine int_seg_block_counter_south_decoder_r0=floor (fine int_seg_counter_south_r0/(4*4)) +1

Fine int_seg_block_counter_south_decoder_r1=floor (fine int_seg_counter_south_r1/(4*4)) +1

Fine int_seg_block_counter_south_decoder_r2=floor (fine int_seg_counter_south_r2/(4*4)) +1

Fine int_seg_block_counter_south_decoder_r3=floor (fine int_seg_counter_south_r3/(4*4)) +1

Fine int_seg_block_counter_east_decoder_r0=floor (fine int_seg_counter_east_r0/(4*4)) +1

Fine int_seg_block_counter_east_decoder_r1=floor (fine int_seg_counter_east_r1/(4*4)) +1

Fine int_seg_block_counter_east_decoder_r2=floor (fine int_seg_counter_east_r2/(4*4)) +1

Fine int_seg_block_counter_east_decoder_r3=floor (fine int_seg_counter_east_r3/(4*4)) +1

Fine int_seg_block_counter_north_decoder_r0=floor (fine int_seg_counter_north_r0/(4*4)) +1

Fine int_seg_block_counter_north_decoder_r1=floor (fine int_seg_counter_north_r1/(4*4)) +1

Fine int_seg_block_counter_north_decoder_r2=floor (fine int_seg_counter_north_r2/(4*4)) +1

Fine int_seg_block_counter_north_decoder_r3=floor (fine int_seg_counter_north_r3/(4*4)) +1

The fine integer code assigned to each of the 128 fragments is determined by the calculation described in the following hardware description language (hereinafter referred to as "hardware description 7"). In addition, for the first 128 fine integer codes, the code assigned to any one of the 128 segments is 1, meaning that 1LSB is added to the tuning capacitor bank in any segment. For the next 128 fine integer codes, the fine integer code assigned to any one of the 128 segments is 2, indicating that 2 LSBs are added to the tuning capacitor bank in any segment, and so on. The value of fine int_code_assignment is between 1 and 8.

Fine int_code_assignment=floor (fine int_code/(32×4)) +1

Based on the values of the block counters described in the hardware description 6, the respective tuning capacitor groups in the west side, the south side, the east side, and the north side of the RTWO ring are set according to calculations specified in the following hardware description language (hereinafter referred to as "hardware description 8"). Although hardware description 8 only shows the computation of the west tuning decoder for ring number 0 and the fine int_seg_block_counter_west_decoder_r0 for some values, other values of the remaining decoders and fine int_seg_block_counter_west_decoder_r0 may use similar computation. For example, if fine int_seg_block_counter_west_decoder_r0=0 and fine int_code_assignment=1, then the fine integer code of the tuning capacitor bank on the west side of RTWO ring number 0 is all zero and the tuning capacitors are switched. In addition, if fine int_seg_block_counter_west_decoder_r0=1, all codes except the fine integer code of segment 0 on the west side of RTWO ring 0 are set to 1 (1 LSB of tuning capacitance). Further, if fine int_seg_block_counter_west_decoder_r0=2, the fine integer codes of segment 0 and segment 4 of the tuning capacitor bank on the west side of RTWO ring 0 are set to 1. When the fine int_seg_block_counter_west_decoder_r0 is equal to 2, the input fine int_code is 17, which means that after each RTWO 16 side adds LSB, the block counter is flipped to the west side of RTWO ring 0.

if fine int_seg_block_counter_west_decoder_r0= 0

Fine int_tuning 0r0=fine int_code_assignment-1

Fine int_tuning 1 r0=fine int_code_assignment-1

Fine int_tuning 2r0=fine int_code_assignment-1

Fine int_tuning 3r0=fine int_code_assignment-1

Fine int_tuning 4r0=fine int_code_assignment-1

Fine int_tuning 5r0=fine int_code_assignment-1

Fine int_tuning 6r0=fine int_code_assignment-1

Fine int_tuning 7r0=fine int_code_assignment-1

elseif fine int_seg_block_counter_west_decoder_r0= 1

Fine int_tuning 0r0=fine int_code_assignment

Fine int_tuning 1 r0=fine int_code_assignment-1

Fine int_tuning 2r0=fine int_code_assignment-1

Fine int_tuning 3r0=fine int_code_assignment-1

Fine int_tuning 4r0=fine int_code_assignment-1

Fine int_tuning 5r0=fine int_code_assignment-1

Fine int_tuning 6r0=fine int_code_assignment-1

Fine int_tuning 7r0=fine int_code_assignment-1

elseif fine int_seg_block_counter_west_decoder_r0= 2

Fine int_tuning 0r0=fine int_code_assignment

Fine int_tuning 1 r0=fine int_code_assignment-1

Fine int_tuning 2r0=fine int_code_assignment-1

Fine int_tuning 3r0=fine int_code_assignment-1

Fine int_tuning 4r0=fine int_code_assignment

Fine int_tuning 5r0=fine int_code_assignment-1

Fine int_tuning 6r0=fine int_code_assignment-1

Fine int_tuning 7r0=fine int_code_assignment-1

Using the tuning algorithm described above, the block counter is incremented every 16 fine integer codes at the input of the decoder. At the end of these 16 fine integer codes, 1LSB is set at segments 0, 8, 16 and 24 for each of the rings R0 (SW), R1 (SE), R2 (NE) and R3 (NW). At the fine integer 128, the block counter is reset and each of the 128 segments has a tuning capacitance of 1LSB (all segments from 0 to 31 have a code of 1 assigned to them). At code 129, the block counter begins incrementing again, while segment 0 has 2LSB. When all 128 segments have 2 LSBs and the algorithm repeats until the fine integer code reaches 3968, the algorithm continues until the fine integer code 256 is reached.

Although specific examples of algorithms for tuning a decoder system are provided above, tuning a decoding algorithm may be implemented in various ways.

Dynamic element matching examples for linearizing RTWO fine-tuning gain

In certain configurations herein, a dynamic element matching scheme is provided to linearize the fine-tuning gain characteristics of the RTWO. For example, dynamic element matching may be used to break the periodicity of the fixed segment selection order used in the segment decoding scheme of RTWO. By reducing or eliminating periodicity in the segment order selection, unwanted spurious frequency components can be mitigated. Conversely, selecting a fixed order of RTWO segments may reduce spectral integrity by generating spurious frequency components.

For example, a wide frequency ramp may span the full range of fine-tuned codes. When using a fixed sequence of segment selection, spurious components occur at frequencies that deviate from the fundamental frequency. The frequency of the spurious component is based on the period of the fixed segment selection order.

Table 5 below shows one example of a fixed order selection for one implementation of the multiple ring RTWO 600 of fig. 11. In table 5, W0, W1, W2, and W3 indicate the west tuned decoders of RTWO rings R0, R1, R2, and R3, respectively. Similarly, S0, S1, S2 and S3 represent the south tuned decoders of RTWO rings R0, R1, R2 and R3, respectively. Likewise, E0, E1, E2, and E3 represent the east-tuned decoders of RTWO rings R0, R1, R2, and R3, respectively. In addition, N0, N1, N2, and N3 represent north-tuned decoders of RTWO rings R0, R1, R2, and R3, respectively.

TABLE 5

As shown in the example listed in table 5, as the fine int_code increases, the decoder activates or triggers in a particular order. The periodicity of the segment selection may result in a reduction in the spectral purity of the output clock phase of the RTWO.

In certain implementations herein, the RTWO decoding system is implemented with a dynamic element matching scheme to linearize a fixed order. Additionally, the dynamic element matching scheme may increase the periodicity of the fixed order and/or remove the periodicity entirely.

FIGS. 13A-1 and 13A-2 illustrate one embodiment of dynamic element matching for segment selection for RTWO. The dynamic element matching schemes of FIGS. 13A-1 and 13A-2 illustrate one embodiment of dynamic element matching for the multi-ring RTWO 600 of FIG. 11. Thus, the illustrated embodiment of dynamic element matching is used in the context of 16 tuned decoders, labeled decoder 0 through decoder 15, respectively.

However, the dynamic element matching scheme may be used for a wide variety of RTWO s, including but not limited to RTWO including more or fewer rings, different implementations of rings, more or fewer fragments, different implementations of fragments, more or fewer tuned decoders, and/or different implementations of tuned decoders.

As shown in fig. 13A-1 and 13A-2, an order of 16 decoder cycles (in this example) is shown, with the order of the selected decoders labeled first through sixteenth decoder selections 1001-1016, respectively. The decoder period indicates a decoder selected in response to a ramp up in the fine integer code received by the RTWO. As described above, in some applications, a wide frequency ramp may span the entire range of fine-tuned codes.

Pointer 1000 is used to indicate the last tuned decoder that has been selected. In addition, the next period pointer 1020 indicates the tuned decoder (16 decoder periods in this example) to be used at the beginning of the next decoder period. As shown in the first decoder selection 1001, the next cycle pointer 1020 is located at a different decoder location than the pointer 1000 is located in the first decoder selection 1001. Achieving dynamic element matching in this way reduces the periodicity of decoder selection by preventing two consecutive 16 decoder periods from starting at the same decoder position.

In the illustrated embodiment, pointer 1000 begins at decoder 0 at first decoder selection 1001. In some implementations, if pointer 1000 is never set, for example, at chip power up or reset, pointer 1000 may be set to a particular starting value (e.g., decoder 0) or to a random or pseudo-random decoder location.

As shown in fig. 13A-1 and 13A-2, when switching from one decoder selection to the next, the selected decoder changes. For example, in the illustrated embodiment, the selected decoder in the next decoder selection begins after the decoder of the current decoder selection ends. Thus, in this embodiment, all previously selected decoders are turned off when transitioning to the next decoder selection.

For example, when transitioning from the first decoder selection 1001 to the second decoder selection 1002, decoder 0 is turned off and decoders 1-2 are turned on. In addition, when switching from the second decoder selection 1002 to the third decoder selection 1003, the decoder 1-2 is turned off and the decoder 3-5 is turned on. Further, when switching from the third decoder selection 1003 to the fourth decoder selection 1004, the decoder 3-5 is turned off and the decoder 6-9 is turned on. In addition, when switching from the fourth decoder selection 1004 to the fifth decoder selection 1005, the decoders 6-9 are turned off and the decoders 10-14 are turned on.

In the embodiment shown, the selected decoders are marked in numerical order, starting with a start index 0 and ending with an end index 15. In addition, when the end index is exceeded during decoder selection, the selected decoder wraps to include decoders starting from the start index. For example, when transitioning from fifth decoder selection 1005 to sixth decoder selection 1006, decoders 10-14 are turned off and decoders 15 and 0-4 are turned on.

As shown in the sixth through sixteenth decoder selections 1006-1016, the algorithm repeats until the sixteenth decoder selection 1016, where all sixteen decoders are selected.

The number of selected decoders may be selected based on the fine integer code. For example, in this embodiment mod (fine int_code, 16) +1 can be calculated with distributed quantization across four rings. Furthermore, in this example, fine int_code0 does not select any decoder. Thus, the result will be a value between 1 and 16.

Depending on the current position of pointer 1000, the result will be a certain number of decoders selected from the current pointer position. In one example, pointer 1000 is located at decoder 5 and fine int_code=200, and mod (200,16) +1=9, the 9 decoders selected corresponding to decoders 6 through 14. Thereafter, the position of pointer 1000 is at decoder 14.

Dynamic element matching may operate with quantization tuning. In one example, the embodiment of dynamic element matching of FIGS. 13A-1 and 13A-2 is used in conjunction with the embodiment of quantization tuning previously discussed with respect to FIGS. 9A-9J. Implementing RTWO in this manner results in at most 1LSB between a given RTWO ring and other RTWO rings, thereby improving performance. Thus, the benefits of dynamic element matching and quantization tuning can be realized. However, other implementations are also possible.

FIGS. 13B-1 and 13B-2 illustrate another embodiment of dynamic element matching for segment selection of RTWO. The dynamic element matching schemes of FIGS. 13B-1 and 13B-2 illustrate one embodiment of dynamic element matching for the multi-ring RTWO 600 of FIG. 11. Thus, the illustrated embodiment of dynamic element matching is used in the context of 16 tuned decoders, labeled decoder 0 through decoder 15, respectively.

As shown in fig. 13B-1 and 13B-2, an order of 16 decoder cycles (in this example) is shown, with the order of the selected decoders labeled first through sixteenth decoder selections 1101-1116, respectively. The decoder period indicates a decoder selected in response to a ramp up in the fine integer code received by the RTWO.

The embodiment of dynamic element matching of fig. 13B-1 and 13B-2 is similar to the embodiment of dynamic element matching of fig. 13A-1 and 13A-2 except that the dynamic element matching of fig. 13B-1 and 13B-2 is implemented to turn off only one decoder when transitioning from one decoder selection to the next.

For example, when transitioning from the first decoder selection 1101 to the second decoder selection 1102, decoder 0 is turned off and decoders 1-2 are turned on. In addition, when switching from the second decoder selection 1102 to the third decoder selection 1103, decoder 1 is turned off, decoder 2 remains on, and decoders 3-4 are turned on. Further, when transitioning from the third decoder selection 1103 to the fourth decoder selection 1104, decoder 2 is turned off, decoders 3-4 remain on, and decoders 5-6 are turned on. In addition, when switching from the fourth decoder selection 1104 to the fifth decoder selection 1105, the demodulator 3 is turned off, the decoders 4-6 remain on, and the decoders 7-8 are turned on.

As shown in the sixth through sixteenth decoder selections 1106-1116, the algorithm repeats until the sixteenth decoder selection 1116, where all sixteen decoders are selected.

Additional details of dynamic element matching of fig. 13B-1 and 13B-2 may be similar to those described previously.

The dynamic element matching scheme of fig. 13A-1 and 13A-2 and the dynamic element matching scheme of fig. 13B-1 and 13B-2 are rotational dynamic element matching schemes. In the example with 16 decoder choices, there are 256 start-up possibilities (16 x 16) for the rotation period. Although the rotational dynamic element matching scheme reduces periodicity by increasing the length of the period of the fixed order, the degree of periodicity can still be maintained.

In some embodiments, the segment decoder system is implemented to operate with random or pseudo-random dynamic element matching.

For example, in some embodiments, a Pseudo Random Binary Sequence (PRBS) is used to change the selection order of the decoders. The PRBS may be generated in any suitable manner, for example using digital logic.

In one example, the PRBS changes the selection pointer every certain number of codes, e.g., every 16 fine integer codes, every 128 fine integer codes, etc. Thus, an even longer rotation sequence can be achieved to break the periodicity of decoder selection.

In another example, dynamic element matching is used to randomize the order in which the segments are selected by a particular tuned decoder. Thus, rather than activating tuning capacitors associated with a particular tuning decoder in a given sequence, the sequence of tuning capacitors controlled by a particular tuning decoder is dynamically selected. Thus, dynamic element matching can be used to break the periodicity in the selection of the tuning decoder (tuning decoder order) and/or in the tuning capacitors selected by the tuning decoder (segment selection order).

FIGS. 13C-1 and 13C-2 illustrate another embodiment of dynamic element matching for segment selection for RTWO. The dynamic element matching of fig. 13C-1 and 13C-2 shows the order of the 16-decoder cycles (in this example), with the order of the selected decoders labeled as first through sixteenth decoder selections 1201-1216, respectively. The decoder period indicates a decoder selected in response to a ramp up in the fine integer code received by the RTWO.

The dynamic element matching embodiment of FIGS. 13C-1 and 13C-2 is similar to the embodiment of FIGS. 13B-1 and 13B-2, except that the PRBS is used to select the next cycle pointer 1020 (location 5 has been pseudo-randomly selected, in this example). Thus, the next cycle pointer 1020 has been selected by a pseudo-random process to start the next decoder cycle at decoder 5.

Thus, RTWO can be implemented to operate with dynamic element matching in a variety of ways. In one example, a tuning decoder system (e.g., tuning decoder system 404 of fig. 10) includes digital logic implemented to provide dynamic element matching.

Although specific examples of algorithms for dynamic element matching are provided above, dynamic element matching algorithms may be implemented in various ways. In a first example, a random set of decoders is selected for a given fine tuning code. For example, when three tuning decoders are activated in response to a particular fine tuning code, the selected tuning decoder may be randomly or pseudo-randomly selected. In another example, the PRBS is used to select between two or more fixed selection orders. Thus, dynamic element matching may be implemented in various ways.

Examples of digital addressing schemes for the sheeting of RTWO segments

In some configurations herein, a segmented digital addressing scheme is provided to control parameters of RTWO segments individually. In some implementations, the serial interface communicates with the segments via segment decoders using shared or common line operations to reduce routing congestion. The controllable parameters may include, but are not limited to, bias settings (e.g., bias current levels) of amplifiers used in the RTWO regeneration circuit, bias settings of sampling latches of the RTWO (e.g., for time-to-digital converter functions), and/or providing segment-specific capacitance adjustments to provide linearity correction. Thus, the settings of a particular RTWO segment may be selected to provide tuning or correction of linear or other operating characteristics to improve performance.

Referring back to fig. 10, rtwo 400 includes a segment decoder system 403 that includes a Segment Decoder (SD) for each segment 100. The segment decoder system 403 is used to decode data received via the serial interface 406 to the segment 100 of the RTWO.

For example, serial interface 406 of FIG. 10 receives input signals 413 including a segment data signal (rtwo_seg_data <7:0 >), a segment address signal (rtwo_seg_addr <4:0 >), a write enable signal (rtwo_wr_en), a serial interface clock signal (rtwo_sclk), and a read data signal (rtwo_rd_data <7:0 >). In some implementations, serial interface 406 is implemented as a local Serial Peripheral Interface (SPI).

For example, in one particular implementation, a 4-ring RTWO with 32 segments per ring includes a data bus that uses 8-bit operations common to the 4 rings, and an address bus that uses 8-bit operations common to the 4 rings. In such an example, the 4-ring RTWO operates with 16 bits and wires.

In contrast, a similar 4-ring RTWO implemented with a segment decoder system may include 2048 bits and lines (16 bits per segment x 32 segments x 4 rings). Routing 2048 lines from the serial interface to each segment of the RTWO is a difficult task and may limit the flexibility and/or scalability of the RTWO design. In addition, a large number of wires may act as a large antenna on a semiconductor chip.

Fig. 14 shows one embodiment of an RTWO1500 with segmented digital addressing. RTWO1500 includes a loop including a first conductor 31, a conductor 32, and a crossover 33.RTWO 1500 also includes a plurality of fragments distributed around the loop. RTWO1500 also includes a segment decoder system comprising segment decoders 1501, 1502, 1503 and 1508. For clarity, only a portion of the ring, segment, and segment decoder system is shown in fig. 14. For example. Fig. 14 shows the circuit on the left side of the RTWO ring.

Although one particular RTWO implementation is shown, the teachings herein are applicable to RTWO implemented in a variety of ways, including, but not limited to, RTWO with different ring implementations (including, for example, more rings and/or differently shaped rings), different segment implementations, and/or different decoder implementations.

As shown in fig. 14, the left hand segment of the RTWO ring is labeled segment 0, segment 1, segment 2. Thus, in this example, there are 8 segments to the left of the loop. In addition, the segment decoder system includes a respective segment decoder for each segment. For example, segment decoder 1501 is coupled to segment 0, segment decoder 1502 is coupled to segment 1, segment decoder 1503 is coupled to segment 2, and segment decoder 1508 is coupled to segment 7. Thus, in this example, there are 8 segment decoders on the left side of the ring.

In the illustrated embodiment, the segment decoder system receives data and address signals 1510. As shown in fig. 14, the data and address signals 1510 include 8-bit segment data signals rtwo_seg_data <7:0> and a 5-bit fragment address signal rtwo_seg_addr <4:0>. Although an example with 8 data bits and 5 address bits is shown, other implementations are possible.

In some implementations, the segment decoder system 401 is implemented to provide addressing of segments associated with multiple rings. In one example, the segment address signal is implemented as an 8-bit signal rtwo_seg_addr <7:0>, wherein the first part of bits is used to identify the segment location and the second part of bits is used to identify the particular ring.

It may be desirable that fragments of RTWO are configurable. To provide configurability, RTWO segments can be written by data and address signals 1510. In some implementations, the segment decoder system is also implemented to read from the segment, for example, by using the read data signal rtwo_rd_data <7 shown in fig. 10: 0>.

As shown in fig. 14, each segment decoder communicates with a respective segment. For example, as shown in block 1511, segment decoder 1501 provides segment write signal seg_data_wr <15 to segment 0: 0>. In addition, as shown in block 1512, segment decoder 1502 provides segment write signals seg_data_wr <15:0> to segment 1. Further, as shown in block 1513, segment decoder 1503 provides segment write signal seg_data_wr <15 to segment 2: 0>. In addition, as shown in block 1518, segment decoder 1508 provides segment write signal seg_data_wr <15:0> to segment 7.

Thus, each segment includes one or more configurable circuits that are programmed or configured using configuration bits provided via a segment write signal. In one embodiment, the one or more configurable circuits include at least one of a regeneration circuit, a latch, a tuning capacitor, or a tap buffer.

In the illustrated embodiment, the segment write signal seg_data_wr <15:0> has a ratio of fragment data signal rtwo_seg_data <7:0> larger bit width. Thus, in this example, fragments may be written in two cycles. By implementing fragment writing over multiple cycles, many global fragment data bits and corresponding lines can be reduced.

The illustrated segment decoders 1501, 1502, 1503, and 1508 each receive a segment address setting signal seg_addr_set <4:0>, which have different values for different segment decoders (e.g., 00000, 00001, 00010, 00011, etc.). The segment address setting signal seg_addr_set <4:0> is used to program the segment decoder with a code indicating the location of the segment decoder. In some implementations, the segment address set signal seg_addr_set <4:0> is hardwired and has a value selected based on its position around the ring.

The segment decoder sets the segment address setting signal seg_addr_set <4:0> and fragment address signal rtwo_seg_addr <4:0> to determine when to access the fragment.

In one embodiment, when the segment address signal rtwo_seg_addr <4:0> and the fragment address setting signal seg_addr_set <4: when 0> matches, the fragment decoder writes the data to the corresponding fragment. When there is an address match, the fragment decoder uses the fragment write signal seg_data_wr <15:0> to write the segment, wherein the written data corresponds to segment data signal rtwo_seg_data <7:0> bits.

The data written may include, but is not limited to, settings of amplifiers of the segments, settings of latches of the segments, and/or capacitance settings of the segments (e.g., adding capacitance to provide linearity correction for a particular segment). Thus, the settings of a particular RTWO segment may be selected to provide tuning or correction of linear or other operating characteristics to improve performance. The written data may be stored in fragments in any suitable manner. In one example, the fragments include state elements, such as memory elements and/or memory (including but not limited to registers), that store data for configuring the fragments.

Although one example of data and address signals 1510 is shown, other implementations are possible. In another example, one or more input signals 413 shown in fig. 10 are provided to each segment decoder.

Although one embodiment of segmented digital addressing is shown in fig. 14, the teachings herein are applicable to segmented digital addressing implemented in a variety of ways.

Fig. 15 illustrates various embodiments of a programmable segment circuit.

As shown in fig. 15, one embodiment of a regeneration circuit 1600 with programmable bias current is shown. The regeneration circuit 1600 includes a first n-type field effect transistor (NFET) 1601 and a first p-type field effect transistor (PFET) 1603 operating as a first inverter, and a second NFET1602 and a second PFET1604 operating as a second inverter. The first and second inverters are connected back-to-back, with the input of the first inverter connected to the output of the second inverter and vice versa. An instantiation of the regeneration circuit 1600 may be included in a segment wherein a first terminal a is connected to a first conductor of the RTWO ring and a second terminal B is connected to a second conductor of the RTWO ring.

In this example, regeneration circuit 1600 includes the use of a set of parallel NFET transistors M [3:0] a configurable bias current source implemented. In addition, in this embodiment, four program bits D [3 ] from the configuration register 1609 of the segment: 0] is used to control the selection of the plurality of active transistors and the corresponding amount of bias current of the inverter.

With continued reference to fig. 15, one embodiment of a regeneration circuit 1620 having programmable degeneration resistors 161, 162 is shown. Each programmable degeneration resistor 161, 162 may comprise a plurality of parallel resistor elements selected by a control bit to control the amount of resistance to degradation. Other details of the regeneration circuit 1620 may be similar to those of the regeneration circuit 1600.

As shown in fig. 15, one embodiment of a regeneration circuit 1630 with programmable noise filter capacitors 1621, 1622, and 1623 is shown. Each noise filtering capacitor 1621-1623 may include a plurality of parallel capacitor elements selected by a control bit to control capacitance. Other details of the regeneration circuit 1640 may be similar to those of the regeneration circuit 1620.

Although fig. 15 shows three examples of programmable segment circuits, various segment circuits may be programmable. Examples of segment programmability include, but are not limited to, setting of an amplifier (e.g., bias current), setting of a TDC latch (e.g., sample point) and/or tuning capacitance tuning setting (e.g., fine code offset LSB).

PLL system example based on RTWO

Fig. 16 shows one embodiment of an RTWO-based PLL system 1700. The PLL system 1700 includes an RTWO 1710. As shown in fig. 16, the RTWO 1710 includes a metal stub 1711, a distributed quantization tuning system 1712, a segment decoding system 1713, a Dynamic Element Matching (DEM) system 174, and a segment digital addressing system 1715.

Metal stub 1711 is included in a segment of the RTWO and helps to provide access to additional layout resources for tuning capacitors and other circuits while allowing the length of the RTWO ring to be relatively short. Thus, the metal stub 1711 does not prevent the RTWO 1710 from operating at a relatively high oscillation frequency (e.g., 10GHz or higher) while providing a connection to a tuning capacitor that adjusts the RTWO oscillation frequency over a wide tuning range and/or provides fine frequency steps.

The distributed quantization tuning system 1712 is used to control tuning capacitors in the RTWO segments using individually controllable code values to enhance the frequency step or resolution of the RTWO. In some implementations, the RTWO 1710 includes multiple rings, and the distributed quantization tuning system 1712 places tuning capacitors on the multiple RTWO rings, respectively. Implementation of RTWO with distributed quantization frequency tuning can achieve relatively fine frequency resolution, e.g., LSB tuning resolution of 50kHz/LSB or less.

A segment decoding system 1713 is provided for the RTWO frequency tuning code to reduce decoding complexity. Segment decoding system 1713 may include global and local decoders for processing frequency tuning codes to reduce routing congestion.

The dynamic element matching system 1714 linearizes the fine-tuning gain characteristics of the RTWO 1710. For example, dynamic element matching system 1714 may be used to reduce or eliminate the periodicity of fixed order segment selection used in segment decoding system 1713. By reducing or eliminating periodicity in the segment order selection, unwanted spurious frequency components may be mitigated, thereby improving performance of PLL system 1700.

The segmented digital addressing system 1715 may be used to control parameters of RTWO segments individually and include segment decoders that operate with shared or common lines to reduce routing congestion. The controllable parameters may include, but are not limited to, bias settings (e.g., bias current levels) of amplifiers used in the RTWO regeneration circuit, bias settings of sampling latches of the RTWO (e.g., for time-to-digital converter functions), and/or providing segment-specific capacitance adjustments to provide linearity correction to the RTWO 1710.

PLL system 1700 illustrates one example of an electronic system that may include an RTWO implemented in accordance with the teachings herein. However, the RTWO described herein may be used in a wide variety of electronic systems, including but not limited to a wide variety of data converters and/or frequency synthesizers.

Application of

Devices employing RTWO including one or more of the above features may be implemented as a variety of electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics, electronic test devices, radar systems, and the like. Examples of electronic devices may also include circuitry for an optical network or other communication network. Consumer electronics may include, but are not limited to, automobiles, camcorders, cameras, digital cameras, portable memory chips, washing machines, dryers, washer/dryers, copiers, facsimile machines, scanners, multi-function peripherals, and the like. Furthermore, the electronic device may include unfinished products, including products for industrial, medical, and automotive applications.

The foregoing description and claims may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematic diagrams depicted in the figures depict an example arrangement of elements and components, in actual embodiments, additional intermediate elements, devices, features, or components may be present (assuming that the functionality of the depicted circuits is not adversely affected).

Although the present invention has been described in terms of certain embodiments, other embodiments apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages described herein, are also within the scope of the invention. Furthermore, the various embodiments described above may be combined to provide further embodiments. In addition, certain features shown in the context of one embodiment may also be incorporated into other embodiments. Accordingly, the scope of the invention is to be limited solely by reference to the appended claims.

Claims

1. A Rotary Traveling Wave Oscillator (RTWO), comprising:

a first RTWO ring;

a plurality of fragments positioned around the first RTWO ring and comprising a first fragment and a second fragment;

a plurality of tuning capacitors selectable to control an oscillation frequency of the RTWO and including a first plurality of capacitors in the first segment and a second plurality of capacitors in the second segment; and

a segment decoder circuit located around the first RTWO ring, the segment decoder circuit operable to control selection of the plurality of tuning capacitors based on one or more frequency tuning codes, wherein the segment decoder circuit comprises a first decoder of the first segment configured to control selection of the first plurality of capacitors based on decoding a first input code, and a second decoder of the second segment configured to control selection of the second plurality of capacitors based on decoding a second input code that is independently controllable from the first input code.

2. The RTWO of claim 1, wherein the segment decoder circuit comprises: a plurality of local decoders, each local decoder configured to control a plurality of selected capacitors for a respective one of the plurality of segments; and a plurality of tuning decoders configured to control the plurality of local decoders based on the one or more frequency tuning codes.

3. The RTWO of claim 2, wherein the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the segment decoder circuit is implemented such that selection of one or more tuning decoders responsive to a given value of the fine frequency tuning code is dynamically selected.

4. The RTWO of claim 3, wherein the segment decoder circuit is implemented such that an order of selecting each of the plurality of tuning decoders is different for a first ramp of the fine frequency tuning code relative to a second ramp of the fine frequency tuning code.

5. The RTWO of claim 4, wherein the selection order is rotated by a plurality of different selection orders.

6. The RTWO of claim 4, wherein the selection order is randomly or pseudo-randomly selected.

7. The RTWO of claim 1, wherein the segment decoder circuit is implemented such that selection of one or more tuning capacitors responsive to a given value of the one or more frequency tuning codes is dynamically selected.

8. The RTWO of claim 1, wherein the first RTWO ring includes a plurality of sides, wherein the segment decoder circuit is further configured to balance a number of selected tuning capacitors for each side of the RTWO ring.

9. The RTWO of claim 8, wherein the decoder circuit is implemented such that the number of tuning capacitors selected per side of the RTWO ring is at most one tuning capacitor, except for each value of the one or more frequency tuning codes.

10. The RTWO of claim 1, further comprising a second RTWO loop phase locked to the first RTWO loop, wherein the segment decoder circuit individually controls a plurality of selected capacitors of the first RTWO loop and the second RTWO loop.

11. The RTWO of claim 10, wherein the segment decoder circuit is further configured to balance a plurality of selected tuning capacitors for the first RTWO ring and the second RTWO ring.

12. The RTWO of claim 11, wherein the segment decoder circuit is implemented such that the number of selected tuning capacitors per RTWO ring is at most one tuning capacitor, except for each value of the one or more frequency tuning codes.

13. The RTWO of claim 1, wherein the plurality of tuning capacitors comprises a plurality of coarse tuning capacitors, or at least one of a plurality of process, voltage, and temperature (PVT) tuning capacitors, and a plurality of fine tuning capacitors, wherein the first plurality of capacitors controlled by the first decoder are fine tuning capacitors, and wherein the second plurality of capacitors controlled by the second decoder are fine tuning capacitors.

14. The RTWO of claim 1, wherein the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the segment decoder circuit is further configured to receive an offset code operable to provide capacitive adjustment for a particular segment of the plurality of segments by adjusting a value of the fine frequency tuning code.

15. The RTWO of claim 14, wherein the offset code is configured to provide dynamic capacitance adjustment for the plurality of segments when the RTWO is operable to linearize the RTWO.

16. A Phase Locked Loop (PLL) with fine frequency tuning resolution, the PLL comprising:

a PLL core configured to generate one or more frequency tuning codes; and

a Rotary Traveling Wave Oscillator (RTWO) comprising:

A first RTWO ring;

a plurality of segments located around the first RTWO ring and comprising a plurality of tuning capacitors selectable to control the oscillation frequency of the RTWO; and

a segment decoder circuit located around the first RTWO ring, the segment decoder circuit operable to control selection of the plurality of tuning capacitors based on one or more frequency tuning codes, wherein the segment decoder circuit comprises a respective decoder segment for each segment of the plurality of segments.

17. The PLL of claim 16, wherein the segment decoder circuit comprises: a plurality of local decoders, each local decoder configured to control a plurality of selected capacitors for a respective one of the plurality of segments; and a plurality of tuning decoders configured to control the plurality of local decoders based on the one or more frequency tuning codes.

18. The PLL of claim 17, wherein the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the segment decoder circuit is implemented such that selection of one or more tuning decoders responsive to a given value of the fine frequency tuning code is dynamically selected.

19. The PLL of claim 18, wherein the segment decoder circuit is implemented such that an order of selecting each of the plurality of tuning decoders is different for a first slope of the fine frequency tuning code relative to a second slope of the fine frequency tuning code.

20. The PLL of claim 19, further comprising a second RTWO loop phase locked to the first RTWO loop, wherein the segment decoder circuit individually controls a plurality of selected capacitors of the first RTWO loop and the second RTWO loop.

21. The PLL of claim 16, wherein the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the segment decoder circuit is further configured to receive an offset code operable to provide capacitance adjustment for a particular segment of the plurality of segments by adjusting a value of the fine frequency tuning code.

22. The PLL of claim 21, wherein the PLL core is configured to control a value of an offset code to dynamically change a capacitance of the plurality of segments to linearize the RTWO.

23. The PLL of claim 16, wherein the frequency step of the RTWO corresponds to a selected frequency variation of a tuning capacitor derived from a segment.

24. A Rotary Traveling Wave Oscillator (RTWO), comprising:

a first RTWO ring;

decoder circuitry comprising a plurality of local decoders, each decoder configured to control a plurality of selected tuning capacitors in a respective one of the plurality of segments, wherein a plurality of input codes of the plurality of local decoders are individually controllable.

25. The RTWO of claim 24, wherein the decoder circuit further comprises a plurality of tuning decoders configured to control the plurality of input codes based on one or more frequency tuning codes.

26. The RTWO of claim 24, wherein the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the decoder circuit is implemented such that selection of one or more tuning decoders responsive to a given value of the fine frequency tuning code is dynamically selected.

27. The RTWO of claim 24, further comprising a second RTWO ring locked to the first RTWO ring, wherein the decoder circuit individually controls a plurality of selected capacitors of the first RTWO ring and the second RTWO ring.

28. The RTWO of claim 24, wherein the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the decoder circuit is further configured to receive an offset code operable to provide capacitance adjustment for a particular segment of the plurality of segments by adjusting a value of the fine frequency tuning code.

29. A Rotary Traveling Wave Oscillator (RTWO), comprising:

an RTWO ring comprising a first transmission line conductor and a second transmission line conductor and configured to carry a travelling wave; and

a plurality of fragments positioned around an RTWO ring, wherein a first fragment of the plurality of fragments comprises:

a pair of metal stubs including a first metal stub electrically connected to the first transmission line conductor and a second metal stub electrically connected to the second transmission line conductor; and

one or more capacitor tuning groups electrically connected to the pair of metal stubs and operable to control the oscillation frequency of the RTWO.

30. The RTWO of claim 29, wherein the first segment further comprises a time-to-digital converter (TDC) latch electrically connected between the first metal stub and the second metal stub and operable to detect the passage of the traveling wave.

31. The RTWO of claim 29, wherein the first metal stub and the second metal stub are substantially equal in length.

32. The RTWO of claim 29, wherein the first metal stub and the second metal stub each have a length of at least 0.05 times the traveling wave wavelength.

33. The RTWO of claim 29, wherein the first metal stub and the second metal stub each have a length of at least 25 μιη.

34. The RTWO of claim 29, wherein the first fragment further comprises: a first tap buffer comprising an input electrically connected to the first metal stub; and a second tap buffer including an input electrically connected to the second metal stub.

35. The RTWO of claim 29, wherein the first segment further comprises a regeneration circuit electrically connected between the first metal stub and the second metal stub and configured to provide energy to the traveling wave to compensate for losses of a differential transmission line.

36. The RTWO of claim 29, wherein each of the plurality of segments comprises a plurality of tuning capacitor banks operable to provide a Least Significant Bit (LSB) tuning resolution of 50kHz/LSB or less than 50kHz/LSB and a tuning range of 4GHz or higher.

37. The RTWO of claim 29, wherein the one or more capacitor tuning banks comprise a fine tuning capacitor bank electrically connected between the first metal stub and the second metal stub, and a coarse tuning capacitor bank electrically connected between the first metal stub and the second metal stub.

38. The RTWO of claim 37, wherein the one or more capacitor tuning groups further comprise a process, voltage and temperature (PVT) tuning capacitor group electrically connected between the first metal stub and the second metal stub.

39. The RTWO of claim 29, wherein each segment includes a TDC latch, wherein the RTWO further includes a clock distribution tree and a reference clock buffer configured to provide a reference clock signal to the TDC latch of each segment via the clock distribution tree.

40. A Phase Locked Loop (PLL) comprising:

a PLL core configured to generate one or more frequency tuning codes; and

a Rotary Traveling Wave Oscillator (RTWO) comprising:

a loop comprising a first transmission line conductor and a second transmission line conductor and configured to carry a traveling wave; and

a plurality of segments located around the circumference and each comprising a pair of metal stubs including a first metal stub electrically connected to the first transmission line conductor and a second metal stub electrically connected to the second transmission line conductor, and one or more capacitor tuning groups electrically connected to the pair of metal stubs and operable to control an oscillation frequency of the RTWO based on the one or more frequency tuning codes.

41. The PLL of claim 40, wherein the first metal stub and the second metal stub each have a length of at least 0.05 times the traveling wave wavelength.

42. The PLL of claim 40, wherein the RTWO is configured to operate as a digitally controlled oscillator and a time-to-digital converter in the PLL.

43. The PLL of claim 40, wherein the one or more capacitor tuning groups comprise a fine tuning capacitor group and a coarse tuning capacitor group, and wherein the one or more frequency tuning codes comprise a coarse tuning code and a fine integer tuning code.

44. The PLL of claim 40, wherein the first metal stub and the second metal stub are substantially equal in length.

45. The PLL of claim 40, wherein the first metal stub and the second metal stub each have a length of at least 25 μm.

46. The PLL of claim 40, wherein each of the plurality of segments located around the loop further comprises a regeneration circuit electrically connected between the first metal stub and the second metal stub and configured to provide energy to the traveling wave to compensate for losses of the first transmission line conductor and the second transmission line conductor.

47. The PLL of claim 40, wherein each of the plurality of segments comprises a plurality of tuning capacitor banks operable to provide a Least Significant Bit (LSB) tuning resolution of 50kHz/LSB or less than 50kHz/LSB and a tuning range of 4GHz or higher than 4 GHz.

48. A method for frequency tuning, comprising:

propagating a traveling wave over a Rotating Traveling Wave Oscillator (RTWO) ring, the RTWO ring comprising a first transmission line conductor and a second transmission line conductor; and

controlling an oscillation frequency of an RTWO ring using one or more capacitor tuning groups of a pair of metal stubs electrically connected to a first segment, the pair of metal stubs including a first metal stub electrically connected to the first transmission line conductor and a second metal stub electrically connected to the second transmission line conductor, wherein the pair of metal stubs extend substantially perpendicular to the RTWO ring such that the pair of metal stubs does not dampen high frequency oscillations of the RTWO.

49. The method of claim 48, further comprising detecting passage of the traveling wave using a time-to-digital converter (TDC) latch in the first segment, the TDC being electrically connected between the first metal stub and the second metal stub.

50. The method of claim 48, further comprising providing signal buffering using a first tap buffer coupled to the first metal stub and a second tap buffer coupled to the second metal stub.

51. The method of claim 48, further comprising providing energy to the traveling wave using a regeneration circuit in the first segment to compensate for losses of the first transmission line conductor and the second transmission line conductor, wherein the regeneration circuit is electrically connected between the first metal stub and the second metal stub.

52. The method of claim 48, wherein controlling said oscillation frequency comprises:

switching a fine tuning capacitor bank in the one or more capacitance tuning banks, the fine tuning capacitor bank electrically connected between the first metal stub and the second metal stub; and

a coarse tuning capacitor bank electrically connected between the first metal stub and the second metal stub is switched.

53. The method of claim 52, wherein the one or more capacitor tuning groups further comprise a process, voltage and temperature (PVT) tuning capacitor group electrically connected between the first metal stub and the second metal stub.