CN109787653A - A kind of simple adaptive control improved method of timing error discriminator - Google Patents
A kind of simple adaptive control improved method of timing error discriminator Download PDFInfo
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- CN109787653A CN109787653A CN201910044981.2A CN201910044981A CN109787653A CN 109787653 A CN109787653 A CN 109787653A CN 201910044981 A CN201910044981 A CN 201910044981A CN 109787653 A CN109787653 A CN 109787653A
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Abstract
The present invention provides a kind of simple adaptive control improved methods of timing error discriminator, which comprises the following steps: step (1): loop convergence stage；Step (2): loop stability tracking phase, the present invention not only increases loop for the robustness of change in signal strength using simple normalized, while also obtaining the direct estimation of true error；Processing simply makes this method in engineering practice and has very strong feasibility.
Description
Technical field
The present invention relates to digital communicating fields, and in particular to a kind of pair of Gardner bit timing error discriminator it is simple from
Adapt to improved method.
Background technique
In digital communication systems, the clock at signal propagation delay time and transmitting-receiving both ends is asynchronous, results in the need for receiving
End recovers bit timing information just and can guarantee the good error performance of communication system.Bit synchronization technology is then the pass for realizing the demand
Key technology, wherein Gardner bit-synchronization algorithm is classical digital timing synchronization control method.This method utilizes similar phaselocked loop
Technology, using loop fashion real-time tracking and locking bit timing instant, bit timing estimation error is wherein important link.
Typical Gardner the timing-error estimation is to obtain bit timing deviation in the way of symbol waveform detection to believe
Breath, this, which makes estimated value will receive symbol waveform shape and signal strength, influences, it is excessive or it is too small can cause bit timing with
Track loop it is unstable, even result in losing lock diverging, thus the typical algorithm is more sensitive to signal strength or weakness.
Summary of the invention
In order to solve above-mentioned insufficient defect, the present invention provides a kind of improvement of the simple adaptive control of timing error discriminator
Method, the algorithm can be adaptive to signal strength or weakness, keep tenacious tracking performance.
The present invention provides the simple adaptive control improved methods of a kind of pair of Gardner bit timing error discriminator, including with
Lower step:
Step (1): loop convergence stage；
Step (2): loop stability tracking phase.
Above-mentioned method, wherein in the step (1), symbol waveform is sampled and obtained with higher sample rate
Sample sequence { x (k) }K=1,2,3..., and the sample sequence is separately input into window withdrawal device and interpolation device.
Above-mentioned method, wherein the window withdrawal device goes out adopting for maximum absolute value to the data pick-up in window width N
Sample value is sent into alpha filter, and N is not less than the sampled value number in a symbol width；Interpolation filter is with every half code element
The rate of one sampled point exports sampled value, output to Timing error estimator.
Above-mentioned method, wherein the peak value of extraction is filtered by the alpha filter.
Above-mentioned method, wherein front and back sampled value x (k-1), x (k+ are obtained by interpolation filter in the step (2)
1) be symbol waveform peak value, using the output valve of interpolation filter as peak estimation, output to alpha filter.
The present invention provides the simple adaptive control improved methods of a kind of pair of Gardner bit timing error discriminator with following
The utility model has the advantages that the present invention not only increases loop for the robustness of change in signal strength, together using simple normalized
When also obtain the direct estimation of true error；Processing simply makes this method in engineering practice and has very strong feasibility.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical label indicates identical part in all the attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is show the gist of the present invention.
Fig. 1 is typical Gardner bit timing error estimation schematic illustration；
Fig. 2 is the improved bit timing error estimation schematic illustration of the present invention；
Fig. 3 is that schematic diagram is embodied in the improved bit timing error estimation of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Referring to Fig.1 shown in-Fig. 3, the simple adaptive control of a kind of couple of Gardner bit timing error discriminator provided by the invention
Improved method, comprising: the symbol peak value estimation method of two different phases and improved Timing error estimator, wherein in place fixed
When synchronization loop converged state, approximate peak value sampling sequence is formed after filtering as dynamic by the maximum value in each period
The symbol peak value of state is estimated.Timing Synchronization loop stability tracking phase in place is sampled by the peak value moment that interpolation filter obtains
Value sequence is estimated after filtering as dynamic symbol peak value, is estimated using the dynamic symbol peak value mentioned among the above to original
Gardner bit timing estimation error be normalized, with a little estimation error accuracy loss exchanged whole loop for
Enhancing to the robustness of signal strength or weakness variation, the present invention not only increase loop for signal using simple normalized
The robustness of Strength Changes, while also obtaining the direct estimation of true error.Processing simply makes this method in engineering reality
There is very strong feasibility in trampling.
Shown in referring to Fig.1, the mode that original algorithm carries out one point sampling point of every half chip to symbol waveform is sampled,
Error calculation is timed using these sampled values.Symbol waveform and sampled point schematic diagram are as shown in Figure 1.It is adopted using three waveforms
Sampling point x (k-1), x (k), x (k+1) carry out following formula such as and calculate, and can get the estimated value of bit timing error:
uτ=x [k] (xd[k-1]-xd[k+1]) (1)
Wherein subscript d indicates the hard-decision values (± 1) to the sampled value.As previously mentioned, the estimated value is true bit timing
The result of product of error and estimation gain, and gain will be influenced by error size, symbol waveform shape and signal strength.
And in the present invention, adaptive impovement is carried out to the estimation using a kind of simple method for normalizing.Usual base band
Signal is the band-limited signal for alerting overmolding filtering, and similar sinusoidal shape is presented in symbol waveform.The present invention is by code
First waveform approximation regards isosceles triangle shape as, and median sample value is relatively normalized waveform peak, not only makes
The estimated value is insensitive to signal strength or weakness and symbol waveform, while being switched to estimated value approximation very using approximate geometric similarity
Real bit timing error amount.As shown in figure 3, peak A, sampled value x (k), dotted line and the horizontal axis composition for connecting origin and peak point
Shape can approximation be considered as similar triangles, then the ratio of x (k) and peak A is equal to true bit timing error τ and half chip width
L.Improved estimation error calculation is as follows:
uτ=x [k] (xd[k-1]-xd[k+1])/(4A[k])≈τ (2)
This waveform approximation brings some deviations to estimation error, but has no effect on the convergence of track loop, while can be with
Find out in tenacious tracking, which can be very small.
A specific embodiment presented below
Embodiment 1, referring to shown in Fig. 2-Fig. 3, a kind of pair of Gardner bit timing error discriminator of the present invention it is simple adaptive
Answering improved method includes: the loop convergence stage: still in convergence process in this stage loop, it is meant that bit decision at this time
Sampling instant is inaccurate, and also can not accurately know the symbol peak value moment at which.The peak estimation in this stage can use one period
The maximum value of interior sampled value sequence carrys out approximate replacement.Due to intersymbol interference, symbol waveform peak value is not in entire wave train
Maximum value.The specific implementation process in the stage are as follows: symbol waveform is sampled with higher sample rate and obtains sample sequence
{x(k)}K=1,2,3..., and the sample sequence is separately input into window withdrawal device 1 and interpolation device 3.Higher sample rate can obtain
The information more about waveform shape is obtained, the estimation of accurate approximate peak is obtained, is also in addition inserting in track loop
Value filtering provides more interpolation reference points.Window withdrawal device 1 goes out adopting for maximum absolute value to the data pick-up in window width N
Sample value is sent into alpha filter 2, and N is not less than the sampled value number in a symbol width.Interpolation filter 3 is with every half yard
The rate of one sampled point of member exports sampled value, output to Timing error estimator 4.Since the presence of noise, signal strength become
Change and possible by the influence of signal processing bring before, the real-time change of peak value sampling value can be caused, in order to obtain one
Stable peak estimation is here filtered the peak value of extraction using the realization of alpha filter 2, and filtering is according to the following equation
It carries out:
After Timing error estimator 4 receives the sample sequence and peak estimation of half code element, using above-mentioned formula (2) into
Row estimation error simultaneously externally exports.Bit timing synchronization loop can adjust in real time 3 sampling instant of interpolation filter according to estimation error,
It is finally adjusted to correct position.
Loop stability tracking phase: convergence is completed in this stage loop, and interpolation filter 3 obtains front and back sampled value x (k-
1), x (k+1) is the peak value of symbol waveform.At this moment it just no longer needs to obtain peak value sampling by window withdrawal device 1, and it is direct
Use the output valve of interpolation filter 3 as peak estimation, output to alpha filter 2.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (5)
1. a kind of simple adaptive control improved method of timing error discriminator, which comprises the following steps:
Step (1): loop convergence stage；
Step (2): loop stability tracking phase.
2. a kind of simple adaptive control improved method of timing error discriminator as described in claim 1, which is characterized in that described
In step (1), symbol waveform is sampled with higher sample rate and obtains sample sequence { x (k) }K=1,2,3..., and should
Sample sequence is separately input into window withdrawal device and interpolation device.
3. a kind of simple adaptive control improved method of timing error discriminator as claimed in claim 2, which is characterized in that described
The sampled value that window withdrawal device goes out maximum absolute value to the data pick-up in window width N is sent into alpha filter, and N is not less than
Sampled value number in one symbol width；Interpolation filter is exporting sampled value with the rate of one sampled point of every half code element,
It exports to Timing error estimator.
4. a kind of simple adaptive control improved method of timing error discriminator as claimed in claim 2, which is characterized in that pass through
The alpha filter is filtered the peak value of extraction.
5. a kind of simple adaptive control improved method of timing error discriminator as claimed in claim 4, which is characterized in that described
Front and back sampled value x (k-1) is obtained by interpolation filter in step (2), x (k+1) is the peak value of symbol waveform, and interpolation is filtered
The output valve of wave device is as peak estimation, output to alpha filter.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112165368A (en) * | 2020-08-27 | 2021-01-01 | 西南科技大学 | Time-synchronized real-time adaptive convergence estimation system |
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| KR100584475B1 (en) * | 2003-04-18 | 2006-05-29 | 전남대학교산학협력단 | Timing-offset compensation algorithm for DTV |
| CN104378129A (en) * | 2014-11-26 | 2015-02-25 | 成都中远信电子科技有限公司 | Land-to-air wideband communication system for unmanned aerial vehicle |
| CN106998236A (en) * | 2017-02-07 | 2017-08-01 | 中国人民解放军国防科学技术大学 | A kind of feedback-type symbol timing synchronizing apparatus and method based on filtering interpolation |
| CN108989260A (en) * | 2018-08-01 | 2018-12-11 | 清华大学 | The digital time synchronization method of modified and device based on Gardner |
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2019
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100584475B1 (en) * | 2003-04-18 | 2006-05-29 | 전남대학교산학협력단 | Timing-offset compensation algorithm for DTV |
| CN1614961A (en) * | 2004-09-03 | 2005-05-11 | 杭州国芯科技有限公司 | Timing recovering method |
| CN104378129A (en) * | 2014-11-26 | 2015-02-25 | 成都中远信电子科技有限公司 | Land-to-air wideband communication system for unmanned aerial vehicle |
| CN106998236A (en) * | 2017-02-07 | 2017-08-01 | 中国人民解放军国防科学技术大学 | A kind of feedback-type symbol timing synchronizing apparatus and method based on filtering interpolation |
| CN108989260A (en) * | 2018-08-01 | 2018-12-11 | 清华大学 | The digital time synchronization method of modified and device based on Gardner |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112165368A (en) * | 2020-08-27 | 2021-01-01 | 西南科技大学 | Time-synchronized real-time adaptive convergence estimation system |
| CN112165368B (en) * | 2020-08-27 | 2021-12-21 | 西南科技大学 | Time-synchronized real-time adaptive convergence estimation system |
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