CN109786254A - 后栅极工艺中的选择性高k形成 - Google Patents
后栅极工艺中的选择性高k形成 Download PDFInfo
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- CN109786254A CN109786254A CN201811355126.5A CN201811355126A CN109786254A CN 109786254 A CN109786254 A CN 109786254A CN 201811355126 A CN201811355126 A CN 201811355126A CN 109786254 A CN109786254 A CN 109786254A
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Classifications
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Abstract
一种方法包括:去除伪栅极堆叠件以在栅极间隔件之间形成开口;选择性地在栅极间隔件的侧壁上形成抑制膜,栅极间隔件的侧壁面向开口;和选择性地在半导体区域的表面上形成介电层。抑制膜抑制介电层在抑制膜上的生长。该方法还包括去除抑制膜;和在开口的剩余部分中形成替换栅电极。本发明提供了一种半导体器件及其形成方法。本发明实施例涉及后栅极工艺中的选择性高k形成。
Description
技术领域
本发明实施例涉及后栅极工艺中的选择性高k形成。
背景技术
晶体管是集成电路中的基本构建元件。在集成电路的最新发展中,晶体管采用金属栅极,其通常以替换栅极的形式形成。替换栅极的形成通常涉及形成伪栅极堆叠件,在伪栅极堆叠件的侧壁上形成栅极间隔件,去除伪栅极堆叠件以在栅极间隔件之间形成开口,将栅极介电层和金属层沉积到开口中,和然后进行化学机械抛光(CMP)以去除栅极介电层和金属层的多余部分。栅极介电层和金属层的其余部分是替换栅极。替换栅极中通常存在多个子层。随着集成电路尺寸的逐渐缩小,替换栅极的宽度变得越来越小,使得容纳多个子层变得更加困难。
发明内容
根据本发明的一些实施例,提供了一种形成半导体器件的方法,包括:去除伪栅极堆叠件以在栅极间隔件之间形成开口;选择性地在栅极间隔件的侧壁上形成抑制膜,其中,所述栅极间隔件的侧壁面向所述开口;选择性地在半导体区域的表面上方形成介电层,其中,所述抑制膜抑制所述介电层在所述抑制膜上的生长;去除所述抑制膜;以及在所述开口的剩余部分中形成替换栅电极。
根据本发明的另一些实施例,还提供了一种形成半导体器件的方法,包括:去除伪栅极堆叠件以在栅极间隔件之间形成开口,其中,半导体区域的表面暴露于所述开口;形成接触所述半导体区域的表面的介电界面层;在沉积工艺中,选择性地在所述介电界面层上方沉积接触所述介电界面层的高k介电层,其中,被沉积后,所述高k介电层不具有位于所述栅极间隔件的侧壁上的部分;以及在所述开口的剩余部分中形成替换栅电极。
根据本发明的另一些实施例,还提供了一种半导体器件,包括:半导体区域;栅极间隔件,位于所述半导体区域上方;和栅极堆叠件,位于所述半导体区域上方,其中,所述栅极堆叠件包括:介电界面层,位于所述半导体区域上方;高k栅极电介质,包括覆盖所述介电界面层的水平部分,其中,所述高k栅极电介质不具有位于所述栅极间隔件的侧壁上的部分,并且所述高k栅极电介质的水平部分与所述栅极间隔件间隔开;以及导电栅电极,位于所述高k栅极电介质上方,其中,所述导电栅电极接触所述栅极间隔件,并且所述导电栅电极包括子层,所述子层包括底部,和连接至所述底部的相对端部的侧壁部分,其中,所述侧壁部分高于所述底部。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该强调,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1、2、3A、3B、4A、4B、5A、5B、6、7、8、9A、9B和10至13A示出了根据一些实施例的形成鳍式场效应晶体管(FinFET)的中间阶段的截面图和透视图。
图13B,13C和13D是根据一些实施例的FinFET的截面图。
图14示出了根据一些实施例的FinFET的截面图。
图15说明根据一些实施例的用于形成FinFET的工艺的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各种示例性实施例提供了晶体管及其形成方法。根据一些实施例示出了形成晶体管的中间阶段。讨论了一些实施例的一些变型。在各种视图和说明性实施例中,相同的附图标记用于表示相同的元件。在所示的示例性实施例中,使用Fin场效应晶体管(FinFET)的形成作为示例来解释本公开的概念。平面晶体管还可以采用本公开的实施例。
图1至图13A示出了根据本公开的一些实施例的晶体管形成中的中间阶段的透视图和截面图。图1至13A所示的步骤也在图15所示的工艺流程300中示意性地反映。根据一些示例性实施例,所形成的晶体管包括p型晶体管(诸如p型FinFET)和n型晶体管(诸如n型FinFET)。
图1示出了初始结构的透视图。初始结构包括晶圆10,晶圆10还包括衬底20。衬底20可以是半导体衬底,其可以是硅衬底,硅锗衬底,或由其他半导体材料形成的衬底。根据本公开的一些实施例,衬底20包括体硅衬底和位于体硅衬底上方的外延硅锗(SiGe)层或锗层(其中没有硅)。衬底20可以掺杂有p型或n型杂质。诸如浅沟槽隔离(STI)区域的隔离区域22可以形成为延伸到衬底20中。相邻STI区22之间的衬底20的部分被称为半导体条124和224,其分别位于器件区域100和200中。器件区100是p型晶体管区,其中将形成诸如p型FinFET的p型晶体管。器件区200是n型晶体管区,其中将形成诸如n型FinFET的n型晶体管。
STI区22可包括衬垫氧化物(未示出)。衬垫氧化物可以由通过衬底20的表面层的热氧化形成的热氧化物。衬垫氧化物也可以是使用例如原子层沉积(ALD),高密度等离子体化学气相沉积(HDPCVD)或化学气相沉积(CVD)形成的沉积的氧化硅层。STI区22还可以包括位于衬垫氧化物上方的介电材料,并且可以使用可流动化学气相沉积(FCVD),旋涂等形成介电材料。
参考图2,凹进STI区22,使得半导体条124和224的顶部突出为高于相邻STI区22的顶面22A,以形成突出鳍124'和224'。相应的步骤在图15所示的工艺流程中示为步骤302。可以使用干蚀刻工艺实施蚀刻,其中NH3和NF3用作蚀刻气体。在蚀刻过程中,可以产生等离子体。也可以包括氩气。根据本公开的可选实施例,使用湿蚀刻工艺实施STI区22的凹进。例如,蚀刻化学品可包括稀释的HF。
在上面示出的示例性实施例中,可以通过任何合适的方法图案化鳍。例如,可以使用一个或多个光刻工艺来图案化鳍,包括双重图案化或多重图案化工艺。通常,双重图案化或多重图案化工艺组合光刻和自对准工艺,允许创建具有例如比使用单个直接光刻工艺可获得的间距更小的间距的图案。例如,在一个实施例中,在衬底上方形成牺牲层并使用光刻工艺图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层,然后可以使用剩余的间隔件或芯轴来图案化鳍。
突出鳍124'和224'的材料也可以用不同于衬底20的材料代替。例如,突出鳍124'可以由Si、SiP、SiC、SiPC或诸如InP、GaAs、AlAs、InAs、InAlAs、InGaAs等的III-V族化合物半导体形成。突出鳍224'可以由Si,SiGe,SiGeB,Ge或诸如InSb,GaSb,InGaSb等的III-V族化合物半导体形成。
参考图3A,分别在突出鳍124'和224'的顶面和侧壁上形成伪栅极堆叠件130和230。相应的步骤在图15所示的工艺流程中示为步骤304。伪栅极堆叠件130可以包括伪栅极电介质132和位于伪栅极电介质132上方的伪栅电极134。伪栅极堆叠件230可以包括伪栅极电介质232和位于伪栅极电介质232上方的伪栅电极234。例如,可以使用多晶硅形成伪栅电极134和234,并且也可以使用其他材料。伪栅极堆叠件130和230中的每一个还可以包括一个(或多个)硬掩模层136和236。硬掩模层136和236可以由SiN、SiO、SiC、SiOC、SiON、SiCN、SiOCN、TiN、AlON、Al2O3等形成。硬掩模层136和236的厚度可以在约10nm和约60nm之间的范围内。伪栅极堆叠件130和230中的每一个分别跨越单个或多个突出鳍124'和224'。伪栅极堆叠件130和230也可以分别具有垂直于相应突出鳍124'和224'的纵向方向的纵向方向。
图3B示出了根据一些实施例的器件区域100和200的截面图。该截面图组合了从包含图3A中的线BB的垂直平面获得的截面图和从包含图3A中的线CC的垂直平面获得的截面图,其中在图3B中,STI区22分隔器件区100和200。示意性地示出了突出鳍124'和224'。而且,n阱区108和p阱区208形成为分别延伸到突出鳍124'和224'中。N阱区108和p阱区208也可以延伸到低于突出鳍124'和224'的半导体衬底20的主体部分中。除非另有说明,否则后续图(图9B和15除外)中的截面图也可以从与图3A所示的垂直平面相同的平面获得,这些平面分别包含线B-B和C-C。
接下来,还如图3A和3B所示,栅极间隔件138和238分别形成在伪栅极堆叠件130和230的侧壁上。在图15所示的工艺流程中,相应的步骤也被示为步骤304。同时,也可以在突出鳍124'和224'的侧壁上形成鳍间隔件(未示出)。根据本公开的一些实施例,栅极间隔件138和238由诸如氧氮化硅(SiON)、碳氮氧化硅(SiOCN)、氧化硅(SiO2)、碳氧化硅(SiOC)等的含氧介电材料形成。取决于随后形成的抑制膜的形成方法,也可以使用诸如氮化硅(SiN)和/或碳化硅(SiC)的非含氧材料来形成栅极间隔件138和238。栅极间隔件138和238可以包括气隙,或者可以形成为包括孔,并且可以具有单层结构或包括多个介电层的多层结构。
图4A和4B分别示出了器件区100和200中的源极/漏极区142和242的形成。根据本公开的一些实施例,外延区140和240分别生长在突出鳍124'和224'上,从而形成包层(cladding)源极/漏极区。相应的步骤在图15所示的工艺流程中示为步骤306。外延区140和240可以分别掺杂有p型杂质和n型杂质,可以利用先前的外延原位掺杂。根据本公开的一些实施例,外延区140包括Si、SiGe、SiGeB、Ge或诸如InSb、GaSb、InGaSb等的III-V族化合物半导体。外延区240可以包括Si、SiP、SiC、SiPC或诸如InP、GaAs、AlAs、InAs、InAlAs、InGaAs等的III-V族化合物半导体。外延区140和240的厚度可以在约3nm和约30nm之间的范围内。
在外延步骤之后,外延区140和突出鳍124'可以进一步注入p型杂质以形成源极区和漏极区142。外延区240和突出鳍224'可以进一步注入n型杂质以形成源极区和漏极区242。根据本公开的替代实施例,跳过注入步骤,例如,当外延区140和240已经分别用p型和n型杂质原位掺杂时。
根据本公开的一些实施例,代替形成包层源极/漏极区,实施蚀刻步骤(下文中称为源极/漏极凹进)以蚀刻突出鳍124'和224'的未被伪栅极堆叠件130/230和栅极间隔件138/238覆盖的部分。蚀刻可以是各向异性的,并且因此鳍124'和224'的直接位于伪栅极堆叠件130和230以及栅极间隔件138和238下面的部分受到保护,并且不被蚀刻。因此,在STI区22之间形成凹槽(未示出)。然后从凹槽生长外延源极/漏极区。
图4B还分别示意性地示出了源极/漏极硅化物区域144和244,其可以通过沉积毯式金属层,实施退火以使毯式金属层与源极/漏极区域142和242反应并且去除金属层的未反应部分来形成。用于形成源极/漏极硅化物区144和244的金属可包括Ti,Co,Ni,NiCo,Pt,NiPt,Ir,PtIr,Er,Yb,Pd,Rh,Nb等。根据可选实施例,在形成替换金属栅极之后形成源极/漏极硅化物区域,并且形成为穿过接触开口,接触开口穿透层间电介质(ILD)如图13A,13B,13C和13D所示。因此,在图4B中,使用虚线示出源极/漏极硅化物区域144和244以指示它们此时可以形成或不形成。在随后的附图中,未示出源极/漏极硅化物区域144和244。
然后形成接触蚀刻停止层(CESL)46和层间电介质(ILD)48,如图5A和5B所示,其分别示出了透视图和截面图。相应的步骤如图15所示的工艺流程中的步骤308所示。CESL 46可以由SiN,SiCN,SiOC,SiON,SiCN,SiOCN等形成。根据本公开的一些实施方案,CESL 46可以在其中包含氧或可以不含氧。例如,可以使用诸如ALD或CVD的共形沉积方法来形成CESL46。ILD 48可以包括使用例如FCVD,旋涂,CVD或其他沉积方法形成的介电材料。ILD 48也可以由含氧介电材料形成,其可以是基于氧化硅(SiO)或基于碳氧化硅(SiOC)的,诸如正硅酸四乙酯(TEOS)氧化物,等离子体增强CVD(PECVD)氧化物(SiO2),磷硅酸盐玻璃(PSG),硼硅酸盐玻璃(BSG),硼掺杂的磷硅酸盐玻璃(BPSG)等。可以实施诸如化学机械抛光(CMP)或机械研磨的平坦化步骤以使ILD 48、伪栅极堆叠件130和230以及栅极间隔件138和238的顶面彼此齐平。
接下来,去除包括硬掩模层136和236,伪栅电极134和234以及伪栅极电介质132和232的伪栅极堆叠件130和230,从而分别形成开口150和250,如图6所示。相应的步骤在图15所示的工艺流程中示为步骤310。暴露突出鳍124'和224'的表面。图6示出了突出鳍124'和224'的顶面的暴露。突出鳍124'和224'的侧壁表面也暴露于开口150和250。接下来,实施清洁步骤以清洁突出鳍124'和224'的表面以去除原生氧化物。可以例如使用稀释的HF溶液进行清洁。
图7示出了抑制膜52的选择性形成。相应的步骤在图15所示的工艺流程中示为步骤312。根据本公开的一些实施例,通过沉积工艺形成抑制膜52,其中,晶圆10暴露于工艺气体(前体),以使抑制膜沉积在其上。在不导通等离子体的情况下进行沉积。取决于工艺气体,沉积温度可以在约50℃和约300℃之间的范围内,或者在约50℃和约200℃之间的范围内。沉积时间可以在约30秒至约60分钟的范围内。在沉积中,工艺气体的流速可以在约500sccm和约10,000sccm之间的范围内。其中形成抑制膜52的工艺室的压力可以在约0.5毫托至约100毫托的范围内。工艺气体可包括Si-Cl基工艺气体,包括十八烷基三氯硅烷(CH3(CH2)17SiCl3),三氯(1H,1H,2H,2H-全氟辛基)硅烷(CF3(CF2)5(CH2)2SiCl3),二甲基二氯硅烷((CH3)2SiCl2),或其组合。可选地或另外地,工艺气体可包括Si-N基工艺气体,包括(二甲基氨基)三甲基硅烷((CH3)2NSi(CH3)3),1-(三甲基甲硅烷基)吡咯烷((CH3)3Si-NC4H8),六甲基二硅氮烷([(CH3)3Si]2NH),双(二甲基氨基)二甲基硅烷([(CH3)2N]2Si(CH3)2),或它们的组合。
根据本公开的替代实施例,通过将晶圆10浸泡在化学溶液中来形成抑制膜52,其中一种或多种上述基于Si-Cl的工艺气体或基于Si-N的工艺气体溶解在溶剂中。溶剂可包括丙酮或异丙醇(IPA)。在一些其他实施例中,溶剂可包括软化水。浸泡时间可以在约30秒至约60分钟的范围内。
根据本公开的一些实施例,可以包含在IL 54,栅极间隔件138/238和ILD 48中的氧化物在其表面处具有OH键,并且OH键包括键合至带正电的氢(H)的带负电的氧(O)。当使用基于Si-Cl的前体或基于Si-N的前体时,由于氮(N)和氯(Cl)具有高电负性值,它们可以容易地与氢键合。因此,在抑制膜52的形成中,OH键和Si-N(或Si-Cl)键断裂,并且前体中的硅与氧键合,并且前体中的官能团因此附接到下面的层中的氧,下面的层例如IL 54,栅极间隔件138/238和ILD 48。用于附接键的相应工艺是甲硅烷基化工艺。氢和Cl(或N)键合,并被排出。然而,在突出鳍124'和224'上,不存在OH键,并且即使突出鳍124'和224'也暴露于相同的前体,这种反应也不会发生在突出鳍124'和224'上。因此,在栅极间隔件138和238的顶面和侧壁以及ILD 48的顶面上形成抑制膜52。此外,在STI区22的顶面上形成抑制膜52,如图9B所示,其示出了从在突出鳍的长度方向上切割穿过突出鳍124'或224'的垂直平面获得的截面图。抑制膜52可以或可以不形成在CESL 46的顶面上。无论抑制膜52是否形成在CESL 46上,所得结构不会受到影响,这是由于位于CESL 46的顶面上的抑制膜52的部分(如果有的话)在随后的平坦化过程中将被去除。抑制膜52的厚度可以为约0.3nm至约2nm。
在抑制膜52的形成中,前体(气体或溶液)中的硅原子可与栅极间隔件138/238,ILD 48,STI区32(图9B)以及可能的CESL中的氧原子形成键。由此生长抑制膜52。另一方面,在前体和突出鳍124'和224'之间没有形成键。因此,抑制膜52选择性地形成在栅极间隔件138/238,ILD 48,STI区22和可能的CESL 46上,但不形成在突出鳍124'和224'上。根据一些实施例,为了确保在突出鳍124'和224'上不形成抑制膜52,在抑制膜52开始生长时,氧化物不能存在于突出鳍124'和224'的表面上。否则,抑制膜52也可以生长在突出鳍124'和224'上。因此,在清洁鳍124'和224'以去除氧化物之后(并且包括)并且在形成抑制膜52之前(并且包括)的时间段内,晶圆10不暴露于将导致氧化物形成在突出鳍124'和224'上的物质。例如,晶圆10不暴露于开放气体、氧气(O2)、臭氧(O3)、水等。取决于前体的组成,抑制膜52可以包括Si,C,H,并且可以或可以不包括Cl。而且,抑制膜52可以是有机膜,并且可以包括官能团CH3,CH2,CF2或其组合。抑制膜52还可以包括碳链(和CH3链),其中多个碳原子(例如约2至20个碳原子)连接以形成链。氮(N)和氯(Cl)可以从前体破坏,并且可以不包括在抑制膜52中。因此,即使N和Cl在抑制膜52中,抑制膜52中N和Cl的百分比也将较低。
图8示出了界面层(IL)54的形成,其包括诸如SiO2的氧化硅。相应的步骤在图15所示的工艺流程中示为步骤314。根据本公开的一些实施例,IL 54是通过在NH4OH和H2O2(和/或H2O)的混合物、HCl和H2O2(和/或H2O)的混合物,H2SO4和H2O2的混合物等中处理晶圆10而形成的化学氧化物层。通过化学处理,由于突出鳍124'和224'的表面材料与化学溶液反应,在突出鳍124'和224'的表面上形成氧化硅。IL 54的厚度可以在约0.2nm和约2nm之间的范围内。根据本公开的一些实施例,使用化学溶液的处理是非原位进行的,随后形成高k栅极电介质。
根据本公开的可选实施例,IL 54是通过在含氧工艺气体(诸如O2,O3,O2和O3的混合物或O3和水蒸汽(H2O)的混合物)中对晶圆10进行热处理而形成的热氧化物层。通过处理,由于突出鳍124'和224'的表面材料的氧化,在突出鳍124'和224'的表面上形成氧化硅。温度可高于约150℃,高于约200℃,或高于约300℃。温度的示例范围在约150℃和约300℃之间。应当理解,抑制膜52可能在高于约200℃或300℃的温度下被损坏,这取决于抑制膜52的组成。为了避免抑制膜52的损坏,在抑制膜52可以承受而不会使其受损的温度下,形成IL54的热氧化物。根据本公开的一些实施例,在随后形成高k栅极电介质的情况下,原位实施用于形成IL 54的热处理,并且可以在用于形成高k栅极电介质的相同工艺室中实施,从而降低了制造成本。根据本公开的又一些可选实施例,通过首先实施化学处理,随后通过热处理来形成IL 54,其中化学处理和热处理的前体类似于前面段落中讨论的。
在上面讨论的实施例中,在形成IL 54之前形成抑制膜52。这种顺序不能逆转。否则,抑制膜52也将形成在IL 54上,并且随后形成的高k介电层将不会在IL 54上延伸。
图9A和9B示出了在形成高k栅极电介质56之后的晶圆10的截面图。相应的步骤如图15所示的工艺流程中的步骤316所示。另外,图9B是从包含图9A中的线9B1-9B1或9B2-9B2的垂直平面获得的,其中垂直平面垂直于突出鳍124'和224'的长度方向。因此,图9B表示切穿突出鳍124'的截面图和切穿突出鳍224'的截面图。根据本公开的一些实施例,高k栅极电介质56包括高k介电材料,诸如HfO2,ZrO2,HfZrOx,HfSiOx,HfSiON,ZrSiOx,HfZrSiOx,Al2O3,HfAlOx,HfAlN,ZrAlOx,La2O3,TiO2,Yb2O3等。高k栅极电介质56可以是单层或包括多于一层的复合层。根据一些示例性实施例,使用包括HfCl4和O3的工艺气体来实施形成。形成可以在约250℃至约350℃的温度范围内实施形成。形成方法可以包括原子层沉积(ALD)。高k栅极电介质56的厚度可以在约0.5nm和约3nm之间的范围内。
由于抑制膜52的存在,高k栅极电介质56的沉积是选择性的。例如,高k栅极电介质56选择性地形成在IL 54上,而不是抑制膜52上,抑制膜52抑制高k栅极电介质56的生长。因此,如图9A和9B所示,高k栅极电介质56在突出鳍124'和224'(其间具有IL 54)的顶面和侧壁(图9B)上生长,并且不在栅极间隔件138和238的侧壁和顶面上生长。例如,虚线57(图9A)示意性地示出了如果高k栅极电介质56是毯式层而不是选择性地形成时的高k栅极电介质56将延伸的位置。根据本公开的一些实施例,通过选择性地形成高k栅极电介质56,提供由区域57标记的空间用于形成替换栅电极。而且,如图9B所示,高k栅极电介质56也不在STI区22上方生长。
根据本公开的一些实施例,在形成高k栅极电介质56之后,去除抑制膜52,并且所得到的结构在图10中示出(也参考图14)。相应的步骤在图15所示的工艺流程中示为步骤318。根据本公开的一些实施例,通过将晶圆10加热到抑制膜52分解的温度来实施抑制膜52的去除。例如,温度可高于约200℃或高于约300℃。根据本公开的一些实施方案,温度在约200℃至约600℃的范围内,并且可以在约250℃至约450℃的范围内。加热过程可持续约1分钟至约60分钟的一段时间。根据本公开的替代实施例,通过使用蚀刻剂侵蚀抑制膜52的蚀刻工艺来实施抑制膜52的去除,并且蚀刻剂不侵蚀高k栅极电介质56、栅极间隔件138和238、CESL 46和ILD48。可以通过干蚀刻或湿蚀刻来实施蚀刻。例如,根据其中使用湿蚀刻的本公开的一些实施例,蚀刻剂包括H3PO4、H2SO4、HCl等作为蚀刻溶液。根据使用干蚀刻的一些实施例,可以使用HBr等作为蚀刻气体。
取决于材料、去除方法和去除工艺,可能发生若干结果。例如,图10示出了区域58,其是抑制膜52的底部部分用于占据的区域。在去除抑制膜52之后,区域58可以被栅极间隔件138/238,IL 54和/或高k栅极电介质56的材料占据。这可以在抑制膜52较薄时发生,并且抑制膜52是通过热去除来除去,因此没有残留物。围绕区域58的材料的膨胀和迁移导致通过去除的抑制膜52留下的空隙(在区域58中)被填充。
区域58还可以形成保留在最终FinFET中的空隙。示例性的空隙在图13B中示意性地示出为空隙78。此外,图13C所示的结构也是形成为具有空隙的所得结构,除了空隙部分地填充有金属栅电极的金属材料,其在随后的工艺步骤中形成。
再次参见图10,区域58还可以包括抑制膜52的残留部分,该残留部分在去除步骤中不被除去。例如,当使用蚀刻去除抑制膜52时,蚀刻剂可能无法到达栅极间隔件138/238和相应的IL 54和高k栅极介电层56的角落(或无法渗透到其间的间隙中),因此留下了抑制膜52的一些底部。剩余的抑制膜52的顶面可以高于,齐平于或低于高k栅极介电层56的顶面。
根据本公开的替代实施例,不去除抑制膜52,并将其留在最终的FinFET中。得到的结构如图13A所示,虚线表示未去除的抑制膜52。
进一步参见图11,堆叠层60和62沉积为毯式层,其延伸到开口150和250中(图10)。相应的步骤在图15所示的工艺流程中示为步骤320。堆叠层60和62中的每一个可包括多个子层。堆叠层60和62中的子层未单独示出,而子层可以彼此区分。可以使用诸如ALD或CVD的共形沉积方法来实施沉积,使得堆叠层60和62(以及每个子层)的垂直部分的厚度和水平部分的厚度基本上彼此相等。堆叠层60和62包括ILD 48上方的一些部分。
堆叠层60和62中的每一个可以包括扩散阻挡层和在扩散阻挡层上方的一个(或多个)功函数层。扩散阻挡层可以由氮化钛(TiN)形成,其可以(或可以不)掺杂硅。功函数层确定相应栅极的功函数,并且包括至少一个层或由不同材料形成的多个层。根据相应的FinFET是n型FinFET还是p型FinFET来选择功函数层的材料。例如,对于在器件区100中形成的p型FinFET,堆叠层60中的功函数层可以包括Ti,Al,TiAl,TiAlN,Ta,TaN,TiAlC,TaAlCSi,TaAlC,TiSiN等。层60中的示例性堆叠功函数层包括TaN层,TaN层上方的TiN层和TiN层上方的TiAl层。对于在器件区200中形成的n型FinFET,堆叠层62中的功函数层可以包括TiN,TaN,TiAl,W,Ta,Ni,Pt等。层62中的示例性堆叠功函数层包括TaN层和TaN层上的TiAl层。在沉积功函数层之后,形成阻挡层,该阻挡层可以是另一个TiN层,在示例性实施例中,该层包括在堆叠层62中。
在如图11所示的示例性实施例中,堆叠层的形成工艺包括毯式沉积堆叠层60,其包括用于p型晶体管的功函数金属,图案化堆叠层60以去除器件区域200中的部分,然后毯式沉积堆叠层62,使得堆叠层62具有与堆叠层60重叠的部分。器件区100中的晶体管的功函数主要由堆叠层60确定,并且器件区200中的晶体管的功函数为主要由堆叠层62确定。
接下来,也如图11所示,沉积金属材料64,其可以由钨,钴,铜等形成。相应的步骤也在图15所示的工艺流程中示为步骤320。金属材料64完全填充剩余的开口150和250(图10)。在如图12所示的后续步骤中,实施诸如CMP或机械研磨的平坦化步骤,从而去除ILD 48上的层60,62和64的部分。结果,形成替换金属栅电极166和266,其包括层60,62和64的剩余部分。相应的步骤在图15所示的工艺流程中示为步骤322。替换金属栅电极166和266与下面的IL 54和高k栅极电介质56的组合分别称为替换栅极堆叠件168和268。
如图12所示,高k栅极介电层56不具有位于栅极间隔件138和238的侧壁上的部分。这与传统替换栅极中的高k栅极介电层不同。结果,替换栅电极166和266与栅极间隔件138和238的侧壁表面接触。
图13A示出了源极/漏极硅化物区70和源极/漏极接触插塞72的形成。相应步骤示出为图15中所示的工艺流程中的步骤324。根据本发明的一些实施例,蚀刻ILD 48和CESL46以形成接触开口。硅化物区域可以在前面的步骤中形成,如图4B所示,并且显示为硅化物区域144和244。可选地,在形成替换栅极之后形成硅化物区域。例如,在形成接触开口之后,沉积金属层(未示出)作为毯式层并延伸到接触开口中,随后在金属层的顶部上进行氮化工艺以形成金属氮化物层。金属层可以由Ti,Co,Ni,NiCo,Pt,Ni(Pt),Ir,Pt(Ir),Er,Yb,Pd,Rh,Nb或其合金形成。金属层的底部未被氮化。接下来,实施退火(可以是快速热退火)以使金属层与源极/漏极区142和242的顶部反应以形成硅化物区70。ILD 48的侧壁上的金属层的部分没有反应。接下来,将先前形成的金属氮化物层留作导电阻挡层,或者去除先前形成的金属氮化物层,然后沉积新的金属氮化物层(例如氮化钛)。然后用诸如钨,钴,铜等金属填充剩余的接触开口,接着进行平坦化以去除多余的材料,得到源极/漏极接触插塞72。由此形成P型FinFET 176和n型FinFET 276。
根据本公开的一些实施例,抑制膜52未被去除,并且因此保留在P型FinFET 176和n型FinFET 276中,如虚线所示。如果没有除去抑制膜52,则抑制膜52位于间隔件138/238和相应的栅电极166和266之间并接触间隔件138/238和相应的栅电极166和266。
图13B示出了根据本发明的一些实施例形成的p型FinFET 176和n型FinFET 276。在区域58(图10)中形成的空隙未被栅电极166和266填充。因此,如图13B所示的空隙78保留在p型FinFET 176和/或n型FinFET 276中。应当理解,虽然图13B示出了空隙78位于突出鳍124'和224'的顶部上,空隙78也可以跟随突出鳍124'和224'的轮廓,并且在突出鳍124'和224'的侧壁上延伸。
图13C示出了根据本发明的一些实施例形成的p型FinFET 176和n型FinFET 276。不完全除去抑制膜52,留下残留部分。因此,抑制膜52具有残留在p型FinFET 176和/或n型FinFET 276中的残留部分。可以认识到,尽管图13C示出了抑制膜52的残留部分位于突出鳍124'和224'的顶部上。,残留部分也可以跟随突出鳍124'和224'的轮廓,并且在突出鳍124'和224'的侧壁上延伸。
图13D示出了根据本发明的一些实施例形成的p型FinFET 176和n型FinFET 276。根据这些实施例,层60和/或62延伸为低于高k栅极电介质56的顶面,并且部分地填充栅极间隔件138/238和层54和56之间的间隙。区域80可以是空隙(气隙或真空),或者可以是抑制膜52的残留部分。应当理解,部分填充的区域和区域80也可以遵循突出鳍124'和224'的轮廓,并且在突出鳍124'和224'的侧壁上延伸。
此外,图13A,13B,13C和13D中所示的结构可以以任何组合存在于同一芯片和相同晶圆上。例如,一些晶体管可以具有接触栅极间隔件138和/或238的层54和56,如图13A所示,而同一芯片上的一些其他晶体管可以具有图13B中的空隙78,图13C中的残留抑制膜52,或具有图13D中的结构。
图14示出了FinFET 176和276的截面图。截面图可以从器件区域100中的包含线14-14的平面(例如,参见图13A)获得,或者从器件区域200中包含线14-14的平面获得。图14中的区域82可以是空隙(气隙或真空),抑制膜残留物,或者可以部分地填充有堆叠层60/62。例如,区域82可以包括部分82A和82B,其中区域82A可以是空隙,并且区域82B可以包括其中的抑制膜52的残余物,这是由于抑制膜52的不完全去除。
本公开的实施例具有一些有利特征。通过选择性地形成抑制膜,在突出鳍上选择性地形成高k栅极电介质,并且不包括栅极间隔件的侧壁上的侧壁部分。如果形成高k栅极电介质的侧壁部分,则由于高k栅极电介质的高k值,将导致相邻栅极和相邻鳍之间的寄生电容的不利增加。因此,选择性地形成高k栅极电介质导致期望的寄生电容减小。另外,通过不形成高k栅极电介质的侧壁部分,否则将被高k栅极电介质的侧壁部分占据的空间现在提供为用于形成替换栅电极。这是有利的,因为随着栅电极尺寸的减小,用于形成替换栅电极的多层的间隙填充变得越来越困难。
根据本发明的一些实施例,一种方法包括:去除伪栅极堆叠件以在栅极间隔件之间形成开口;选择性地在栅极间隔件的侧壁上形成抑制膜,栅极间隔件的侧壁面向开口;和选择性地在半导体区域的表面上形成介电层。抑制膜抑制介电层在抑制膜上的生长。该方法还包括去除抑制膜;和在开口的剩余部分中形成替换栅电极。在实施例中,该方法还包括:在半导体区域的暴露表面上形成介电界面层,其中,介电层位于介电界面层上方并与介电界面层接触。在实施例中,在形成抑制膜之后形成介电界面层。在实施例中,去除抑制膜包括热处理。在实施例中,使用基于Si-Cl的前体形成抑制膜。在实施例中,使用基于Si-N的前体形成抑制膜。在实施例中,形成抑制膜包括在工艺气体中热处理包括栅极间隔件和半导体区域的相应晶圆。在实施例中,在去除抑制膜之后,在介电层与栅极间隔件的最近边缘之间形成间隙,并且在形成替换栅电极之后,间隙保留。在实施例中,在去除抑制膜之后,抑制膜的残留部分保留,并且在形成替换栅电极之后,残留部分位于替换栅电极下面。
根据本发明的一些实施例,一种方法包括:去除伪栅极堆叠件以在栅极间隔件之间形成开口,其中,半导体区域的表面暴露于开口;形成接触半导体区域的表面的介电界面层;在沉积工艺中,选择性地在介电界面层上方沉积接触介电界面层的高k介电层,其中,沉积的高k介电层没有在栅极间隔件的侧壁上的部分;和在开口的剩余部分中形成替换栅电极。在实施例中,该方法还包括形成与栅极间隔件的侧壁接触的抑制膜,其中,在形成高k介电层期间,抑制膜抑制高k介电层在抑制膜上的生长。在实施例中,该方法还包括在形成替换栅电极之前去除抑制膜。在实施例中,形成替换栅电极以接触抑制膜的侧壁。在实施例中,形成替换栅电极包括沉积功函数金属层,并且在沉积功函数金属层时,整个高k介电层低于栅极间隔件的顶面。
根据本发明的一些实施例,一种器件包括:半导体区域;栅极间隔件,位于半导体区域上方;和栅极堆叠件,位于半导体区域上方。栅极堆叠件包括:介电界面层,位于半导体区域上方;高k栅极电介质,包括覆盖介电界面层的水平部分,其中,高k栅极电介质没有在栅极间隔件的侧壁上的部分,并且高k栅极电介质的水平部分与栅极间隔件间隔开;和导电栅电极,位于高k栅极电介质上方,其中,导电栅电极接触栅极间隔件。导电栅电极包括子层,子层包括底部,和连接至底部的相对端部的侧壁部分,其中,侧壁部分高于底部。在实施例中,高k栅极电介质通过气隙与栅极间隔件间隔开。在实施例中,气隙包括在介电界面层和栅极间隔件之间延伸并与介电界面层和栅极间隔件处于同一水平的部分。在实施例中,高k栅极电介质通过抑制膜与栅极间隔件间隔开,并且抑制膜由与栅极间隔件,介电界面层和高k栅极电介质的材料不同的材料形成。在实施例中,抑制膜具有接触栅极间隔件的侧壁的第一边缘,以及接触高k栅极电介质的边缘的第二边缘,并且第一边缘和第二边缘位于抑制膜的相对边缘。在实施例中,抑制膜包含硅和选自由CH3、CH2和CF2组成的组中的官能团。
根据本发明的一些实施例,提供了一种形成半导体器件的方法,包括:去除伪栅极堆叠件以在栅极间隔件之间形成开口;选择性地在栅极间隔件的侧壁上形成抑制膜,其中,所述栅极间隔件的侧壁面向所述开口;选择性地在半导体区域的表面上方形成介电层,其中,所述抑制膜抑制所述介电层在所述抑制膜上的生长;去除所述抑制膜;以及在所述开口的剩余部分中形成替换栅电极。
在上述方法中,还包括:在所述半导体区域的暴露表面上形成介电界面层,其中,所述介电层位于所述介电界面层上方并与所述介电界面层接触。
在上述方法中,在形成所述抑制膜之后形成所述介电界面层。
在上述方法中,去除所述抑制膜包括热处理。
在上述方法中,使用基于Si-Cl的前体形成所述抑制膜。
在上述方法中,使用基于Si-N的前体形成所述抑制膜。
在上述方法中,形成所述抑制膜包括在处于50℃至200℃之间的温度下的工艺气体中热处理包括所述栅极间隔件和所述半导体区域的相应晶圆。
在上述方法中,在去除所述抑制膜之后,在所述介电层与所述栅极间隔件的最近边缘之间形成间隙,并且在形成所述替换栅电极之后,所述间隙保留。
在上述方法中,在去除所述抑制膜之后,所述抑制膜的残留部分保留,并且在形成所述替换栅电极之后,所述残留部分位于所述替换栅电极下面。
根据本发明的另一些实施例,还提供了一种形成半导体器件的方法,包括:去除伪栅极堆叠件以在栅极间隔件之间形成开口,其中,半导体区域的表面暴露于所述开口;形成接触所述半导体区域的表面的介电界面层;在沉积工艺中,选择性地在所述介电界面层上方沉积接触所述介电界面层的高k介电层,其中,被沉积后,所述高k介电层不具有位于所述栅极间隔件的侧壁上的部分;以及在所述开口的剩余部分中形成替换栅电极。
在上述方法中,还包括:形成与所述栅极间隔件的侧壁接触的抑制膜,其中,在形成高k介电层期间,所述抑制膜抑制所述高k介电层在所述抑制膜上的生长。
在上述方法中,还包括在形成所述替换栅电极之前去除所述抑制膜。
在上述方法中,形成所述替换栅电极以接触所述抑制膜的侧壁。
在上述方法中,形成所述替换栅电极包括沉积功函数金属层,并且在沉积所述功函数金属层时,整个所述高k介电层低于所述栅极间隔件的顶面。
根据本发明的另一些实施例,还提供了一种半导体器件,包括:半导体区域;栅极间隔件,位于所述半导体区域上方;和栅极堆叠件,位于所述半导体区域上方,其中,所述栅极堆叠件包括:介电界面层,位于所述半导体区域上方;高k栅极电介质,包括覆盖所述介电界面层的水平部分,其中,所述高k栅极电介质不具有位于所述栅极间隔件的侧壁上的部分,并且所述高k栅极电介质的水平部分与所述栅极间隔件间隔开;以及导电栅电极,位于所述高k栅极电介质上方,其中,所述导电栅电极接触所述栅极间隔件,并且所述导电栅电极包括子层,所述子层包括底部,和连接至所述底部的相对端部的侧壁部分,其中,所述侧壁部分高于所述底部。
在上述半导体器件中,所述高k栅极电介质通过气隙与所述栅极间隔件间隔开。
在上述半导体器件中,所述气隙包括在所述介电界面层和所述栅极间隔件之间延伸并与所述介电界面层和所述栅极间隔件处于同一水平的部分。
在上述半导体器件中,所述高k栅极电介质通过抑制膜与所述栅极间隔件间隔开,并且所述抑制膜由与所述栅极间隔件、所述介电界面层和所述高k栅极电介质的材料不同的材料形成。
在上述半导体器件中,所述抑制膜具有接触所述栅极间隔件的侧壁的第一边缘,以及接触所述高k栅极电介质的边缘的第二边缘,并且所述第一边缘和所述第二边缘位于所述抑制膜的相对边缘。
在上述半导体器件中,所述抑制膜包含硅和选自由CH3、CH2和CF2组成的组中的官能团。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成半导体器件的方法,包括:
去除伪栅极堆叠件以在栅极间隔件之间形成开口;
选择性地在栅极间隔件的侧壁上形成抑制膜,其中,所述栅极间隔件的侧壁面向所述开口;
选择性地在半导体区域的表面上方形成介电层,其中,所述抑制膜抑制所述介电层在所述抑制膜上的生长;
去除所述抑制膜;以及
在所述开口的剩余部分中形成替换栅电极。
2.根据权利要求1所述的方法,还包括:
在所述半导体区域的暴露表面上形成介电界面层,其中,所述介电层位于所述介电界面层上方并与所述介电界面层接触。
3.根据权利要求2所述的方法,其中,在形成所述抑制膜之后形成所述介电界面层。
4.根据权利要求1所述的方法,其中,去除所述抑制膜包括热处理。
5.根据权利要求1所述的方法,其中,使用基于Si-Cl的前体形成所述抑制膜。
6.根据权利要求1所述的方法,其中,使用基于Si-N的前体形成所述抑制膜。
7.根据权利要求1所述的方法,其中,形成所述抑制膜包括在处于50℃至200℃之间的温度下的工艺气体中热处理包括所述栅极间隔件和所述半导体区域的相应晶圆。
8.根据权利要求1所述的方法,其中,在去除所述抑制膜之后,在所述介电层与所述栅极间隔件的最近边缘之间形成间隙,并且在形成所述替换栅电极之后,所述间隙保留。
9.一种形成半导体器件的方法,包括:
去除伪栅极堆叠件以在栅极间隔件之间形成开口,其中,半导体区域的表面暴露于所述开口;
形成接触所述半导体区域的表面的介电界面层;
在沉积工艺中,选择性地在所述介电界面层上方沉积接触所述介电界面层的高k介电层,其中,被沉积后,所述高k介电层不具有位于所述栅极间隔件的侧壁上的部分;以及
在所述开口的剩余部分中形成替换栅电极。
10.一种半导体器件,包括:
半导体区域;
栅极间隔件,位于所述半导体区域上方;和
栅极堆叠件,位于所述半导体区域上方,其中,所述栅极堆叠件包括:
介电界面层,位于所述半导体区域上方;
高k栅极电介质,包括覆盖所述介电界面层的水平部分,其中,所述高k栅极电介质不具有位于所述栅极间隔件的侧壁上的部分,并且所述高k栅极电介质的水平部分与所述栅极间隔件间隔开;以及
导电栅电极,位于所述高k栅极电介质上方,其中,所述导电栅电极接触所述栅极间隔件,并且所述导电栅电极包括子层,所述子层包括底部,和连接至所述底部的相对端部的侧壁部分,其中,所述侧壁部分高于所述底部。
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