CN109783395A - Memory pool access method, exchange chip, memory modules and electronic equipment - Google Patents
Memory pool access method, exchange chip, memory modules and electronic equipment Download PDFInfo
- Publication number
- CN109783395A CN109783395A CN201711132919.6A CN201711132919A CN109783395A CN 109783395 A CN109783395 A CN 109783395A CN 201711132919 A CN201711132919 A CN 201711132919A CN 109783395 A CN109783395 A CN 109783395A
- Authority
- CN
- China
- Prior art keywords
- memory
- bit wide
- memory block
- data
- grain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Read Only Memory (AREA)
- Static Random-Access Memory (AREA)
Abstract
The embodiment of the present application provides a kind of memory pool access method, exchange chip, memory modules and electronic equipment.In the embodiment of the present application, increase exchange chip in memory modules, exchange chip interconnects the memory grain that the bit wide that memory block each in memory modules includes is L1, and virtual memory block compatible with the bit wide L of Memory Controller Hub is provided to Memory Controller Hub based on these memory blocks, the bit wide of virtual memory space is L2, and meet L=L2*N, L2 < L1, so that Memory Controller Hub can be with the first memory block of successful access.Because the actual memory space of the first memory block is L1*N > L2*N, it can be seen that memory dilatation may be implemented in the case where the quantity without increasing the CPU for being integrated with Memory Controller Hub, cost of implementation is relatively low.
Description
Technical field
This application involves technical field of memory more particularly to a kind of memory pool access method, exchange chip, memory modules and electricity
Sub- equipment.
Background technique
In the use process of the equipment such as server, terminal device, often there is the case where low memory.Memory size master
It is limited to the capacity of Memory Controller Hub and single memory grain.The volume dependent of single memory grain is deposited in dynamic randon access
The particle technique and processing procedure of reservoir (Dynamic Random Access Memory, DRAM), and the progress of particle technique is compared
Slowly, can not meet the needs of using to memory size in time.
In face of memory requirements problem, traditional method is to increase memory size by increasing the quantity of Memory Controller Hub, by
It is integrated in Memory Controller Hub and central processing unit (Central Processing Unit, CPU), institute is in this way
Cost of implementation it is higher, therefore, it is necessary to a kind of new schemes to solve the problems, such as memory dilatation.
Summary of the invention
The many aspects of the application provide a kind of memory pool access method, exchange chip, memory modules and electronic equipment, to
It realizes memory dilatation, reduces cost of implementation.
The embodiment of the present application provides a kind of memory pool access method, is suitable for memory modules, and the memory modules include at least
One memory block, each memory block include N number of memory grain that bit wide is L1, which comprises
According to the bit wide mapping relations between the corresponding bit wide L and bit wide L2 of the first memory block in the memory modules,
The data-signal that the bit wide that Memory Controller Hub exports is L is split as the downlink data signal that N number of bit wide is L2；
It, will be described N number of according to the addressing mapping relations between first memory block corresponding bit wide L1 and bit wide L2
The downlink data signal that bit wide is L2 is spliced into the data-signal that K1 bit wide is L1；
The data-signal that the K1 bit wide is L1 is written in K1 memory grain of first memory block；Its
In, L=L2*N, L2 < L1, K1≤N, and L1, L2, K1, N are positive integer.
The embodiment of the present application also provides a kind of memory pool access method, is suitable for memory modules, and the memory modules include extremely
A few memory block, each memory block include N number of memory grain that bit wide is L1, which comprises
The data that K2 bit wide is L1 are read from K2 memory grain of the first memory block in the memory modules to believe
Number；
According to the addressing mapping relations between first memory block corresponding bit wide L1 and bit wide L2, by the K2
The data-signal that bit wide is L1 is split as the upstream data signals that N group bit wide is L2, and every group includes that L1/L2 bit wide is the upper of L2
Row data-signal；
According to the bit wide mapping relations between first memory block corresponding bit wide L and bit wide L2, by N group position
The upstream data signals that width is L2 merge into the data-signal that L1/L2 bit wide is L, are sequentially output to Memory Controller Hub；Wherein,
L=L2*N, L2 < L1, K2≤N, and L1, L2, K2, N are positive integer.
The embodiment of the present application also provides a kind of memory modules, comprising: at least one memory block and exchange chip, each
Memory block includes N number of memory grain that bit wide is L1；
The exchange chip include: control unit, the uplink port group being connect with Memory Controller Hub and with it is described at least
Multiple downlink port groups that each memory grain is correspondingly connected in one memory block；Described control unit respectively with the upstream ends
Mouth and the connection of the multiple downlink port group；
Described control unit is used for: based at least one described memory block to the Memory Controller Hub provide with it is described interior
The compatible virtual memory space of bit wide L of memory controller, the bit wide of the virtual memory space are L2, and L=L2*N, L2 <
L1, L1, L2, N are positive integer.
The embodiment of the present application also provides a kind of exchange chip, comprising: control unit, the upstream ends connecting with Memory Controller Hub
Multiple downlink ports that each memory grain is correspondingly connected in mouth group and at least one memory block for including with memory modules
Group；Described control unit is connect with the uplink port and the multiple downlink port group respectively；
Described control unit is used for: based at least one described memory block to the Memory Controller Hub provide with it is described interior
The compatible virtual memory space of bit wide L of memory controller, the bit wide of the virtual memory space are L2, and L=L2*N, L2 <
L1, L1, L2, N are positive integer.
The embodiment of the present application also provides a kind of electronic equipment, comprising: memory modules provided by the above embodiment, Memory control
Device and processor；The processor accesses the memory modules by the Memory Controller Hub.
In the embodiment of the present application, increase exchange chip in memory modules, exchange chip is by memory each in memory modules
The bit wide that block includes is that the memory grain of L1 is interconnected, and is based on these memory blocks to Memory Controller Hub offer and memory
The bit wide of the compatible virtual memory block of the bit wide L of controller, virtual memory space is L2, and meets L=L2*N, L2 < L1,
So that Memory Controller Hub can be with each memory block of successful access.Because the actual memory space of memory block is L1*N > L2*N, by
This it is visible without increase be integrated with Memory Controller Hub CPU quantity in the case where memory dilatation, cost of implementation may be implemented
It is relatively low.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present application, constitutes part of this application, this Shen
Illustrative embodiments and their description please are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 is the structural schematic diagram for the memory modules that one exemplary embodiment of the application provides；
Fig. 2 is a kind of structural schematic diagram for exchange chip that the application another exemplary embodiment provides；
Fig. 3 is the structural schematic diagram for another exchange chip that the application another exemplary embodiment provides；
Fig. 4 is a kind of flow diagram for memory pool access method that the application another exemplary embodiment provides；
Fig. 5 is the flow diagram for another memory pool access method that the application another exemplary embodiment provides；
Fig. 6 is the structural schematic diagram for a kind of electronic equipment that the application another exemplary embodiment provides.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with the application specific embodiment and
Technical scheme is clearly and completely described in corresponding attached drawing.Obviously, described embodiment is only the application one
Section Example, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall in the protection scope of this application.
In face of memory dilatation problem of the existing technology, the embodiment of the present application provides a solution, basic ideas
It is: increases exchange chip in memory modules, is L1 by the bit wide that memory block each in memory modules is included by exchange chip
Memory grain is interconnected, and is provided based on these memory blocks to Memory Controller Hub and be adapted with the bit wide L of Memory Controller Hub
Virtual memory block, the bit wide of virtual memory space is L2, and meets L=L2*N, L2 < L1, so that Memory Controller Hub can be with
Each memory block of successful access.Because the actual memory space of memory block is L1*N > L2*N, it can be seen that without increasing collection
Memory dilatation may be implemented in the case where quantity at the CPU for having Memory Controller Hub, cost of implementation is relatively low.
Below in conjunction with attached drawing, the technical scheme provided by various embodiments of the present application will be described in detail.
Fig. 1 is the structural schematic diagram for the memory modules 100 that one exemplary embodiment of the application provides.As shown in Figure 1, this is interior
Depositing mould group 100 includes: at least one memory block (RANK) and exchange chip.
Each RANK includes N number of memory grain that bit wide is L1.Memory grain is the minimum memory to form memory modules 100
Unit is referred to as memory chip.The bit wide L1 of memory grain indicates that memory grain is available within a clock cycle
Data bits.L1 and N is positive integer.In general L1=2n, n is positive integer.For example, L1 can be any memories such as 8,4,16
The digit that particle technique is supported.The memory space truly of at least one RANK composition memory modules 100.CPU is logical
Memory Controller Hub access memory modules 100, which are crossed, indeed through each RANK in Memory Controller Hub access memory modules 100 includes
Memory grain process.It to simplify the description, can be by " CPU passes through Memory Controller Hub and accesses memory modules 100 or memory
Grain " is simply expressed as " Memory Controller Hub accesses memory modules 100 or memory grain ".
Optionally, above-mentioned memory grain can select phase change memory (PRAM), static random access memory (SRAM), move
State random access memory (DRAM), other kinds of random access memory (RAM), read-only memory (ROM), electric erasable
Programmable read only memory (EEPROM), flash memory, read-only disc read only memory (CD-ROM) (CD-ROM), digital versatile disc
(DVD) any one and in magnetic tape cassette etc..
For convenient for distinguish, if the bit wide of Memory Controller Hub be L, i.e., can be to memory mould in one clock cycle of Memory Controller Hub
Data bits group 100 write-in or read.In general, the bit wide L of Memory Controller Hub is greater than the bit wide of single memory grain
L1.According to the processing mode of the prior art, in order to be adapted with the bit wide L of Memory Controller Hub, the memory that a RANK may include
The maximum quantity of particle is L/L1.For example, it is assumed that the bit wide L=72bit of Memory Controller Hub, bit wide=8bit of memory grain,
A RANK then, which can be obtained, according to the processing mode of the prior art at most may include 72/8=9 memory grain.If it is intended to
The memory capacity of the RANK is extended, general way is to try to the memory grain using larger capacity.If 9 memory grains are
It is maximum capacity that memory grain technique is supported, it is meant that the memory capacity of the RANK will be unable to be extended again.
In the present embodiment, in order to realize memory dilatation, exchange chip is increased in memory modules 100.Exchange chip
On the one hand the interconnection between memory grain for including for realizing each RANK and memory modules 100 and Memory Controller Hub it
Between interconnection；On the other hand the memory block in mould group 100 provides the position with Memory Controller Hub to Memory Controller Hub based on memory
The compatible virtual memory space of wide L, to achieve the purpose that dilatation.As shown in Figure 1, exchange chip specifically include that control unit,
Uplink port group and multiple downlink port groups.
Wherein, uplink port group is for connecting Memory Controller Hub, to realize between memory modules 100 and Memory Controller Hub
Interconnection.Uplink port group includes data wire pin, control wire pin, multiple pins such as address wire pin, respectively with Memory control
Device is corresponded towards the signal pins of memory modules 100.Optionally, the interface standard that uplink port group is deferred to can be with memory
The interface standard that controller is deferred to is identical, to improve the collocation degree between port.Optionally, uplink port group and Memory Controller Hub
The interface standard deferred to can be JTAG standard, but not limited to this.As shown in Figure 1, uplink port group is expressed as INTERFACE_
M.Wherein, M indicates the quantity for the RANK that memory modules 100 include, M=2n, n can be the integers such as 0,1,2,3.
Wherein, multiple downlink port groups are for connecting the memory grain that each RANK includes, in realizing that each RANK includes
Deposit the interconnection between particle.In Fig. 1, only to show a case where RANK is connect with exchange chip, but not convenient for diagram
It is limited to a RANK.Correspondingly, N number of downlink port group that exchange chip includes also only is shown in Fig. 1, be respectively PORT_1,
PORT_2 ... and PORT_N, N here indicate the quantity for the memory grain that a RANK includes.One downlink port group
A corresponding memory grain.Each downlink port group, which also includes that data wire pin, control wire pin, address wire pin etc. are multiple, draws
Foot is corresponded with the signal pins of correspondence memory particle respectively.Optionally, the interface standard that each downlink port group is deferred to can
It is identical with the interface standard deferred to corresponding memory grain.Optionally, the interface that downlink port group and memory grain are deferred to
Standard can be JTAG standard, but not limited to this.
Control unit is mainly used at least one memory block that mould group 100 based on memory includes and provides to Memory Controller Hub
Virtual memory space compatible with the bit wide L of Memory Controller Hub realizes memory expansion.
Optionally, control unit can pass through data during Memory Controller Hub accesses the RANK in memory modules 100
The mapping of bit wide provides virtual memory space compatible with the bit wide L of Memory Controller Hub to Memory Controller Hub, realizes that memory expands
Exhibition.Wherein, the mapping process of data bit width is carried out as unit of RANK.In other words, each in Memory Controller Hub access
During RANK, control unit can carry out the mapping of data bit width for each RANK, different to provide to Memory Controller Hub
Virtual RANK.
By taking the first RANK in memory modules 100 as an example, control unit can be in the mistake of the first RANK of Memory Controller Hub access
Cheng Zhong carries out the mapping of data bit width to the first RANK, to be adapted to Memory Controller Hub offer with the bit wide L of Memory Controller Hub
Empty memory headroom, realize memory expansion.Wherein, the bit wide of the virtual memory space is L2, and meets L=L2*N, L2 < L1.
L2 is positive integer, in general L2=2m, m is positive integer.For example, L2 can be the position that the memory grains techniques such as 2,4 are supported
It is less than any digit of L1 in number.Data bit width mapping for the first RANK actually will be the N number of interior of L1 comprising bit wide
The first RANK for depositing particle is mapped as the virtual RANK comprising N number of memory grain that bit wide is L2.
In the case where the bit wide of Memory Controller Hub is L, in memory modules 100 provided in this embodiment, a RANK
The quantity N=L/L2 for the memory grain that maximum may include, because L2 is less than L1, compared with prior art, each RANK
The quantity for the memory grain that may include increases, and in the case where the bit wide L1 of memory grain is constant, is equivalent in increasing
Deposit capacity.For example, it is assumed that the bit wide L=72bit of Memory Controller Hub, bit wide=8bit of memory grain, virtual memory space
Bit wide L2=4bit, then a RANK can be obtained according to the processing mode of the prior art at most may include 72/8=9 memory
Particle；And in the present embodiment, a RANK at most may include 72/4=18 memory grain.It means that in face of same
Memory Controller Hub, the memory modules of the prior art can at most support the RANK comprising 9 memory grains, and the present embodiment
Memory modules 100 can support the RANK comprising 18 memory grains, greatly extend memory size.
In above-described embodiment or following embodiments, Memory Controller Hub relates generally to from interior the access of memory modules 100
It deposits and reads data in mould group 100 and write two processes of data into memory modules 100, and Memory Controller Hub carries out each RANK
The process of read-write operation is similar, and difference is only that the data of read-write are different.Therefore, in the application following embodiment, by within
For the process that memory controller is written and read the first RANK in memory modules 100, data bit width is carried out to control unit
The process of mapping is described in detail.
Wherein, Memory Controller Hub the oneth RANK into memory modules 100 provided by the embodiments of the present application writes the process of data
Include:
The first step, Memory Controller Hub send the memory address of data to be written by address wire to the first RANK.The process
Be it is straight-through, control unit does not do specially treated, i.e., the memory address that Memory Controller Hub issues can be directly to by exchange chip
Up to memory grain.
Second step, Memory Controller Hub issue memory write order by control line, choose the memory grain in the first RANK, with
The memory grain is notified to need to be written to data.The process be also it is straight-through, control unit does not do specially treated, i.e. memory control
The memory write order of device processed can be directly to by exchange chip up to memory grain.In this example, it is assumed that Memory Controller Hub selects
In K1 memory grain in the first RANK, K1≤N, and K1 is positive integer.
Third step, Memory Controller Hub export the data that bit wide is L to exchange chip by data line；Control in exchange chip
Unit processed is according to the bit wide mapping relations between the first RANK corresponding bit wide L and bit wide L2, the position that Memory Controller Hub is exported
The data-signal that width is L is split as the downlink data signal that N number of bit wide is L2；According to the corresponding bit wide L1 of the first RANK and bit wide
The downlink data signal that N number of bit wide is L2 is spliced into the data-signal that K1 bit wide is L1 by the addressing mapping relations between L2；
The data-signal that K1 bit wide is L1 is written in K1 memory grain of the first memory block.So far, Memory Controller Hub is to originally
The process of the first RANK write-in data terminates in the memory modules 100 that embodiment provides.
Wherein, Memory Controller Hub the oneth RANK from memory modules 100 provided by the embodiments of the present application reads the mistake of data
Journey includes:
The first step, Memory Controller Hub send the memory address of data to be read by address wire to the first RANK.The process
Be it is straight-through, control unit does not do specially treated, i.e., the memory address that Memory Controller Hub issues can be directly to by exchange chip
Up to memory grain.
Second step, Memory Controller Hub issue memory read command by control line, choose the memory grain in the first RANK, with
The memory grain is notified to need therefrom to read data.The process be also it is straight-through, control unit does not do specially treated, i.e. memory control
The memory read command of device processed can be directly to by exchange chip up to memory grain.In this example, it is assumed that Memory Controller Hub selects
In K2 memory grain in the first RANK, K2≤N, and K2 is positive integer.
Third step, it is L1 that the control unit in exchange chip reads K2 bit wide from the K2 memory grain of the first RANK
Data-signal；It is L1 by K2 bit wide according to the addressing mapping relations between the first RANK corresponding bit wide L1 and bit wide L2
Data-signal be split as N group bit wide be L2 upstream data signals, every group include L1/L2 bit wide be L2 upstream data letter
Number；According to the bit wide mapping relations between the first RANK corresponding bit wide L and bit wide L2, the upstream data for being L2 by N group bit wide
Signal merges into the data-signal that L1/L2 bit wide is L, is sequentially output to Memory Controller Hub.So far, Memory Controller Hub is from this reality
The process for applying reading data in the first RANK in the memory modules 100 of example offer terminates.
It is worth noting that using memory modules 100 provided by the embodiments of the present application, in Memory Controller Hub to the first RANK
During writing data and reading data from the first RANK, the processing of hardly change Memory Controller Hub and memory grain is patrolled
Volume, compatibility is preferably.
Using the memory grain that before memory modules 100 provided in this embodiment, can include according to each RANK
The parameters such as the bit wide L2 of quantity N, the bit wide L1 of memory grain and virtual memory space be pre-formed bit wide L1 and bit wide L2 it
Between addressing mapping relations.It is worth noting that the addressing mapping relations between the corresponding bit wide L1 and bit wide L2 of different RANK
Forming process it is identical, but because the corresponding memory address range of different RANK is different, therefore the corresponding bit wide L1 of difference RANK
The content of addressing mapping relations between bit wide L2 is different.
By taking the addressing mapping relations formed between the corresponding bit wide L1 and bit wide L2 of the first RANK as an example, in exchange chip
Control unit can serially address N number of memory grain in the first RANK, to obtain addressing sequence；Then, by the volume
Memory address in the sequence of location is split as L1*N/L2 address field, and the memory address in each address field belongs to suitable with bit wide L2
The address matched；Then, L1*N/L2 address field is divided into N number of group of addresses, each group includes L1/L2 address field；Finally,
Establish mapping relations between the addressing sequence and N number of group of addresses as be the corresponding bit wide L1 and bit wide L2 of the first RANK it
Between addressing mapping relations.
It is alternatively possible to which the address field for belonging to same memory grain in L1*N/L2 address field is divided into an address
Group, so that L1*N/L2 address field is divided into N number of group of addresses.Certainly, it other than this packet mode, can also use
Other packet modes.
In some exemplary embodiments, during generating memory modules 100, can by bit wide L1, bit wide L2 with
And the preset parameters such as each RANK memory grain number N for including are in memory modules 100.Based on this, bit wide L1 and position are being formed
During addressing mapping relations between wide L2, can directly using bit wide L1, bit wide L2 preset in memory modules 100 with
And the parameters such as each RANK memory grain number N for including.
In other exemplary embodiments, in order to improve the flexibility of memory modules 100 when in use, memory modules
100 support configuration operation.Based on this, can using before memory modules 100, at any time by configuration-direct configuration bit wide L1,
The memory grain number N that bit wide L2 and each RANK include.For example, interaction circle of 100 place equipment of memory modules can be passed through
Face configures the parameters such as memory grain number N that bit wide L1, bit wide L2 and each RANK include.It in this way can be according to using need
It asks, flexible configuration bit wide L2, improves the usage mode of memory modules 100.
In the above-described embodiments, data bit width mapping is carried out to control unit by taking the first RANK in memory modules 100 as an example
Process be described in detail.In some embodiments, memory modules 100 include a RANK, i.e. the first RANK.In memory
Mould group 100 includes that can directly determine the first RANK in the embodiment of a RANK, then be written and read behaviour to the first RANK
Make.In further embodiments, memory modules 100 include two or more RANK.It include two in memory modules 100
It can be each RANK setting number, the number of different RANK is different, and pre-establishes or in the embodiment of two or more RANK
RANK is numbered and memory address range mapping table, is stored with the corresponding memory address range of each RANK in the mapping table, different
RANK corresponds to different memory address ranges, the sum of corresponding memory address range of all RANK that memory modules 100 include shape
At the addressing range of memory modules 100.Based on this, it can need to write data into memory modules 100 in Memory Controller Hub or need
When reading data from memory modules 100, the memory address being adapted to bit wide L2 that can be exported according to Memory Controller Hub, inquiry
RANK number and memory address range mapping table, to obtain the first RANK number；From at least one RANK, the first RANK is determined
Identified RAK is numbered as the first RANK, then the first RANK is written and read again.For example, control unit can incite somebody to action
The memory address of Memory Controller Hub output being adapted to bit wide L2 is matched in each memory address range in the mapping table, so
RANK number corresponding to the memory address range in matching, i.e. the first RANK number are obtained afterwards.Wherein, the first RANK is carried out
The process of read-write operation is referring to the description of previous embodiment, and details are not described herein.
Optionally, in some embodiments, memory modules 100 can be realized as standard type, such as can be implemented as standard
Bilateral memory modules (Dual In-line Memory Modules, DIMM), small outline dual memory modules (Small
Outline Dual In-line Memory Module, SO-DIMM) etc..The memory modules 100 of standard type can be with existing skill
The various equipment for needing memory modules, such as server, terminal device etc. are mutually compatible in art.
Optionally, in further embodiments, memory modules 100 can be realized as non-standard form.For example, memory modules
100 width, length and thickness etc. can be realized depending on concrete application demand, without being limited by various memory standards
The diversification of memory modules pattern.
Further, other than memory modules 100, the embodiment of the present application also provides a kind of exchange chip, the exchange chip
Suitable for memory modules 100.As shown in Fig. 2, one exemplary embodiment of the application provide exchange chip include: control unit,
Uplink port group and multiple downlink port groups.In Fig. 2, INTERFACE_M indicates uplink port group, " INTERFACE_M "
In M it is identical as the quantity for the RANK that memory modules 100 include, M=2n, n can be the integers such as 0,1,2,3.In Fig. 2,
PORT_1 to PORT_i indicates multiple downlink port groups, and i is natural number, identical as the sum of memory grain in memory modules 100.
Wherein, uplink port group is for connecting Memory Controller Hub, to realize between memory modules 100 and Memory Controller Hub
Interconnection.Uplink port group includes data wire pin, control wire pin, multiple pins such as address wire pin, respectively with Memory control
Device is corresponded towards the signal pins of memory modules 100.Optionally, the interface standard that uplink port group is deferred to can be with memory
The interface standard that controller is deferred to is identical, to improve the collocation degree between port.Optionally, uplink port group and Memory Controller Hub
The interface standard deferred to can be JTAG standard, but not limited to this.
Wherein, multiple downlink port groups are each to realize for connecting the memory grain that each RANK includes in memory modules 100
The interconnection between memory grain that RANK includes.The corresponding memory grain of one downlink port group.Each downlink port group
Including data wire pin, control wire pin, multiple pins such as address wire pin, respectively with the signal pins one of correspondence memory particle
One is corresponding.Optionally, the interface mark that the interface standard that each downlink port group is deferred to can be deferred to corresponding memory grain
It is quasi- identical.Optionally, the interface standard that downlink port group and memory grain are deferred to can be JTAG standard, but not limited to this.
Control unit is mainly used at least one memory block that mould group 100 based on memory includes and provides to Memory Controller Hub
Virtual memory space compatible with the bit wide L of Memory Controller Hub realizes memory expansion.
Optionally, control unit can pass through data during Memory Controller Hub accesses the RANK in memory modules 100
The mapping of bit wide provides virtual memory space compatible with the bit wide L of Memory Controller Hub to Memory Controller Hub, realizes that memory expands
Exhibition.Wherein, the mapping process of data bit width is carried out as unit of RANK.In other words, each in Memory Controller Hub access
During RANK, control unit can carry out the mapping of data bit width for each RANK, different to provide to Memory Controller Hub
Virtual RANK.
By taking the first RANK in memory modules 100 as an example, control unit can be in the mistake of the first RANK of Memory Controller Hub access
Cheng Zhong provides empty memory headroom compatible with the bit wide L of Memory Controller Hub to Memory Controller Hub by the mapping of data bit width,
Realize memory expansion.Wherein, the bit wide of the virtual memory space is L2, and meets L=L2*N, L2 < L1.L2 is positive integer, one
As for L2=2m, m is positive integer.For example, L2 can be appointing less than L1 in the digit that the memory grains techniques such as 2,4 are supported
Meaning digit.Data bit width mapping for the first RANK is actually by first comprising N number of memory grain that bit wide is L1
RANK is mapped as the virtual RANK comprising N number of memory grain that bit wide is L2.
In the case where the bit wide of Memory Controller Hub is L, it is based on exchange chip provided in this embodiment, memory modules 100
In the quantity N=L/L2 of memory grain that may include of a RANK maximum because L2 is less than L1, with prior art phase
Than the quantity for the memory grain that each RANK may include increases, in the case where the bit wide L1 of memory grain is constant, quite
In increasing memory size.For example, it is assumed that the bit wide L=72bit of Memory Controller Hub, bit wide=8bit of memory grain, virtually
The bit wide L2=2bit of memory headroom, then a RANK can be obtained according to the processing mode of the prior art at most may include 72/8
=9 memory grains；And it is based on exchange chip provided in this embodiment, a RANK of memory modules 100 at most may include
72/2=36 memory grain.It means that facing same Memory Controller Hub, the memory modules of the prior art can at most be propped up
The RANK comprising 9 memory grains is held, and the exchange chip based on the present embodiment, memory modules 100 can be supported comprising 36
The RANK of memory grain, greatly extends memory size.
Wherein, by taking the process of the first RANK in Memory Controller Hub access memory modules 100 as an example, control unit passes through data
The mapping of bit wide is mainly wrapped to the process that Memory Controller Hub provides virtual memory space compatible with the bit wide L of Memory Controller Hub
Include: Memory Controller Hub to the first RANK be written data during carry out data bit width mapping and Memory Controller Hub from
The mapping that data bit width is carried out during reading data in first RANK specifically describes reference can be made to aforementioned carry out memory modules
The embodiment of description, details are not described herein.
In some exemplary embodiments, the realization structure of another exchange chip is as shown in Figure 3, comprising: control unit,
Uplink port group and multiple downlink port groups, wherein control unit specifically include that port virtual module, addressing module and
Mapping table module.Wherein, the function of uplink port group and multiple downlink port groups can be found in previous embodiment, no longer superfluous herein
It states.In the present embodiment, the function of port virtual module, addressing module and mapping table module is stressed.
Port virtual module is mainly used for passing through data bit width during Memory Controller Hub accesses memory modules 100
Mapping provide empty memory headroom compatible with the bit wide L of Memory Controller Hub, realization memory expansion to Memory Controller Hub.Its
In, the process that port virtual module carries out data bit width mapping during Memory Controller Hub accesses memory modules 100 can join
See the description of previous embodiment, details are not described herein.
Addressing module is primarily used to form the addressing mapping relations between each RANK corresponding bit wide L1 and bit wide L2.Its
In, the process of addressing mapping relations that addressing module is formed between each RANK corresponding bit wide L1 and bit wide L2 is identical, and difference exists
In: the content of addressing mapping relations between the corresponding bit wide L1 and bit wide L2 of different RANK is different.
By taking the addressing mapping relations formed between the corresponding bit wide L1 and bit wide L2 of the first RANK as an example, addressing module can be with
N number of memory grain in first RANK is serially addressed, to obtain addressing sequence；It then, will be in the addressing sequence
Depositing address dividing is L1*N/L2 address field, and the memory address in each address field belongs to the address being adapted to bit wide L2；So
Afterwards, L1*N/L2 address field is divided into N number of group of addresses, each group includes L1/L2 address field；Finally, establishing the addressing sequence
It arranges with the mapping relations between N number of group of addresses as being addressing mapping between the corresponding bit wide L1 and bit wide L2 of the first RANK
Relationship.
Optionally, the address field that same memory grain is belonged in L1*N/L2 address field can be divided by addressing module
One group of addresses, so that L1*N/L2 address field is divided into N number of group of addresses.Certainly, other than this packet mode, also
Other packet modes can be used.
Correspondingly, mapping table module is mainly used for storing the mapping of the addressing between each RANK corresponding bit wide L1 and bit wide L2
Relationship.Optionally, the addressing mapping relations between each RANK corresponding bit wide L1 and bit wide L2 can be written and be reflected by addressing module
In firing table module.
Still optionally further, as shown in figure 3, exchange chip further include: configuration unit.The configuration unit supports user internal
Mould group 100 is deposited to be configured.For example, configuration unit may be in response to configuration-direct, configuration bit wide L1, bit wide L2 and each RANK
The parameters such as the memory grain number N for including.
Still optionally further, as shown in figure 3, exchange chip further include: multiple correspondingly with multiple downlink port groups
Port driving unit.In the present embodiment, it is contemplated that the quantity of downlink port group is increased, in order to realize to Memory Controller Hub
Compatibility, by for each downlink port group be arranged port driving unit, each downlink port group is normally driven, thus
Enable Memory Controller Hub with the memory modules 100 after original power successful access dilatation.To the port virtual of control unit
For module, it can be attached by the corresponding port driver block of each downlink port group with each downlink port group.
It is worth noting that the exchange chip that the various embodiments described above provide is suitable for memory modules 100.
Further, in addition to above-mentioned memory modules 100 and exchange chip, the embodiment of the present application also provides a kind of be applicable in
In the memory pool access method of memory modules 100.As shown in figure 4, a kind of exemplary memory pool access method includes:
401, it is mapped according to the bit wide in memory modules between the first memory block (RANK) corresponding bit wide L and bit wide L2
The data-signal that the bit wide that Memory Controller Hub exports is L is split as the downlink data signal that N number of bit wide is L2 by relationship.
It 402, is L2 by N number of bit wide according to the addressing mapping relations between the first RANK corresponding bit wide L1 and bit wide L2
Downlink data signal be spliced into K1 bit wide be L1 data-signal.
403, the data-signal that K1 bit wide is L1 is written in the K1 memory grain of the first RANK；Wherein, L is memory
The bit wide of controller, L1 are the bit wides for the memory grain that each RANK includes in memory modules, and N is that each RANK includes in memory modules
Memory grain quantity, and L=L2*N, L2 < L1, K1≤N, L1, L2, K1, N are positive integer.
Embodiment illustrated in fig. 4 essentially describes the general procedure that Memory Controller Hub writes data to memory modules, detailed process
Referring to the description of aforementioned implementation.In this embodiment, K1 memory grain in the first RANK can be issued by Memory Controller Hub
Memory write order is chosen.
Memory Controller Hub, can also be by exchanging core other than it data can be written to memory modules by exchange chip
Piece reads data from memory modules.As shown in figure 5, another exemplary memory pool access method includes:
It 501, is L1's from K2 bit wide is read in memory modules in K2 memory grain of the first memory block (RANK)
Data-signal.
It 502, is L1 by K2 bit wide according to the addressing mapping relations between the first RANK corresponding bit wide L1 and bit wide L2
Data-signal be split as N group bit wide be L2 upstream data signals, every group include L1/L2 bit wide be L2 upstream data letter
Number.
It 503, is L2's by N group bit wide according to the bit wide mapping relations between the first RANK corresponding bit wide L and bit wide L2
Upstream data signals merge into the data-signal that L1/L2 bit wide is L, are sequentially output to Memory Controller Hub；Wherein, L is memory
The bit wide of controller, L1 are the bit wides for the memory grain that each RANK includes in memory modules, and N is that each RANK includes in memory modules
Memory grain quantity, and L=L2*N, L2 < L1, K2≤N, and L1, L2, K2, N are positive integer.
Embodiment illustrated in fig. 5 essentially describes the general procedure that Memory Controller Hub reads data from memory modules, detailed process
Referring to the description of aforementioned implementation.In this embodiment, K2 memory grain in the first RANK can be issued by Memory Controller Hub
Memory read command is chosen.
It in some embodiments, can be to the N in the first RANK before data are written to the first RANK or read data
A memory grain is serially addressed, to obtain addressing sequence；The memory address addressed in sequence is split as L1*N/L2 ground
Location section, the memory address in each address field belong to the address being adapted to bit wide L2；L1*N/L2 address field is divided into N number of
Group of addresses；The mapping relations between addressing sequence and N number of group of addresses are established as the first RANK corresponding bit wide L1 and bit wide L2
Between addressing mapping relations.
Optionally, in above process, the address field that same memory grain is belonged in L1*N/L2 address field can be drawn
It is divided into a group of addresses, so that L1*N/L2 address field is divided into N number of group of addresses.
In some embodiments, memory modules support configuration operation.Based on this, to N number of memory grain in the first RANK
It is serially addressed, to obtain before addressing sequence, bit wide L1, bit wide L2 and each can be configured according to configuration-direct
The memory grain number N that RANK includes, parameter needed for forming the addressing mapping relations between bit wide L1 and bit wide L2 with offer.
In some embodiments, memory modules include a RANK.Based on this, it can directly determine what memory modules included
RANK is the first RANK, then executes read operation shown in write operation and/or Fig. 5 shown in Fig. 4 for the first RANK.
In further embodiments, memory modules include two or more RANK.It in these embodiments, can be with
It is arranged for each RANK and numbers, the number of different RANK is different, and pre-establishes RANK number and memory address range mapping table,
The corresponding memory address range of each RANK is stored in the mapping table, different RANK correspond to different memory address ranges, interior
Deposit the addressing range that the sum of corresponding memory address range of all RANK that mould group includes forms memory modules.It, can be with based on this
It, can be according to interior when Memory Controller Hub needs to write data into memory modules 100 or needs to read data from memory modules 100
The memory address of memory controller output being adapted to bit wide L2, inquiry RANK number and memory address range mapping table, to obtain
First RANK number；From at least one RANK, determine that the first RANK numbers identified RAK as the first RANK, then needle
Read operation shown in write operation and/or Fig. 5 shown in Fig. 4 is executed to the first RANK.For example, can by Memory Controller Hub export with position
The memory address of wide L2 adaptation is matched in each memory address range in the mapping table, with then obtaining the memory in matching
The number of RANK corresponding to the range of location, i.e. the first RANK number.
It should be noted that the executing subject of each step of above-described embodiment institute providing method may each be same equipment,
Alternatively, this method is also by distinct device as executing subject.For example, the executing subject of step 401 to step 403 can be equipment
A；For another example, step 401 and 402 executing subject can be equipment A, the executing subject of step 403 can be equipment B；Etc..
In addition, containing in some processes of the description in above-described embodiment and attached drawing according to particular order appearance
Multiple operations, but it should be clearly understood that these operations can not execute or parallel according to its sequence what appears in this article
It executes, serial number of operation such as 401,402 etc. is only used for distinguishing each different operation, and serial number itself does not represent any
Execute sequence.In addition, these processes may include more or fewer operations, and these operations can execute in order or
It is parallel to execute.It should be noted that the description such as herein " first ", " second ", be for distinguish different message, equipment,
Module etc. does not represent sequencing, does not also limit " first " and " second " and is different type.
Further, other than above-mentioned memory modules 100, exchange chip and memory pool access method, the application is implemented
Example also provides a kind of electronic equipment.As shown in fig. 6, the electronic equipment includes memory modules 100 provided by the above embodiment, memory
Controller 200 and processor 300.Processor 300 accesses memory modules 100 by Memory Controller Hub 200.
Optionally, Memory Controller Hub 200 is integrated with processor 300.Pass through Memory Controller Hub in processor 300
200 access memory modules 100 during, the processing logic of processor 300 and Memory Controller Hub 200 with prior art phase
Together, details are not described herein.The processing logic of memory modules 100 can be found in the description of previous embodiment, and details are not described herein.
Optionally, which can be server, terminal device, mobile unit etc..Server can be conventional clothes
Business device, Cloud Server, cloud host, virtual center etc..Terminal device can be with smart phone, PC, desktop computer, plate electricity
Brain etc..
Further, according to the difference of electronic equipment way of realization, as shown in fig. 6, electronic equipment can also include with down toward
A few component: other components such as communication component 400, display 500, power supply module 600, audio component 700.Only show in Fig. 6
Meaning property provides members, is not meant to that electronic equipment only includes component shown in Fig. 6.
Communication component 400 in Fig. 6 can be configured to convenient between 400 corresponding device of communication component and other equipment
The communication of wired or wireless way.400 corresponding device of communication component can access the wireless network based on communication standard, such as
WiFi, 2G or 3G or their combination.In one exemplary embodiment, communication component 400 comes from via broadcast channel reception
The broadcast singal or broadcast related information of external broadcasting management system.In one exemplary embodiment, the communication component 400
It further include near-field communication (NFC) module, to promote short range communication.For example, radio frequency identification (RFID) skill can be based in NFC module
Art, Infrared Data Association (IrDA) technology, ultra wide band (UWB) technology, bluetooth (BT) technology and other technologies are realized.
Display 500 in Fig. 6, may include screen, and screen may include liquid crystal display (LCD) and touch surface
Plate (TP).If screen includes touch panel, screen may be implemented as touch screen, to receive input signal from the user.
Touch panel includes one or more touch sensors to sense the gesture on touch, slide, and touch panel.The touch passes
Sensor can not only sense the boundary of a touch or slide action, but also detect associated with the touch or slide operation lasting
Time and pressure.
Power supply module 600 in Fig. 6, the various assemblies for 600 corresponding device of power supply module provide electric power.Power supply module
600 may include power-supply management system, one or more power supplys and other with for power supply module corresponding device generate, management and
Distribute the associated component of electric power.
Audio component 700 in Fig. 6, is configured as output and/or input audio signal.For example, audio component includes
One microphone (MIC), when 700 corresponding device of audio component is in operation mode, as call model, logging mode and voice are known
When other mode, microphone is configured as receiving external audio signal.The received audio signal can be further stored in and deposit
Reservoir is sent via communication component 400.In some embodiments, audio component 700 further includes a loudspeaker, for exporting
Audio signal.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
In a typical configuration, calculating equipment includes one or more processors (CPU), input/output interface, net
Network interface and memory.
Memory may include the non-volatile memory in computer-readable medium, random access memory (RAM) and/or
The forms such as Nonvolatile memory, such as read-only memory (ROM) or flash memory (flash RAM).Memory is computer-readable medium
Example.
Computer-readable medium includes permanent and non-permanent, removable and non-removable media can be by any method
Or technology come realize information store.Information can be computer readable instructions, data structure, the module of program or other data.
The example of the storage medium of computer includes, but are not limited to phase change memory (PRAM), static random access memory (SRAM), moves
State random access memory (DRAM), other kinds of random access memory (RAM), read-only memory (ROM), electric erasable
Programmable read only memory (EEPROM), flash memory or other memory techniques, read-only disc read only memory (CD-ROM) (CD-ROM),
Digital versatile disc (DVD) or other optical storage, magnetic cassettes, tape magnetic disk storage or other magnetic storage devices
Or any other non-transmission medium, can be used for storage can be accessed by a computing device information.As defined in this article, it calculates
Machine readable medium does not include temporary computer readable media (transitorymedia), such as the data-signal and carrier wave of modulation.
It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability
It include so that the process, method, commodity or the equipment that include a series of elements not only include those elements, but also to wrap
Include other elements that are not explicitly listed, or further include for this process, method, commodity or equipment intrinsic want
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including described want
There is also other identical elements in the process, method of element, commodity or equipment.
The above description is only an example of the present application, is not intended to limit this application.For those skilled in the art
For, various changes and changes are possible in this application.All any modifications made within the spirit and principles of the present application are equal
Replacement, improvement etc., should be included within the scope of the claims of this application.
Claims (22)
1. a kind of memory modules characterized by comprising at least one memory block and exchange chip, each memory block
The N number of memory grain for being L1 including bit wide；
The exchange chip include: control unit, the uplink port group being connect with Memory Controller Hub and with it is described at least one
Multiple downlink port groups that each memory grain is correspondingly connected in memory block；Described control unit respectively with the uplink port with
And the multiple downlink port group connection；
Described control unit is used for: being provided and the memory control based at least one described memory block to the Memory Controller Hub
The compatible virtual memory space of bit wide L of device processed, the bit wide of the virtual memory space are L2, and L=L2*N, L2 < L1,
L1, L2, N are positive integer.
2. memory modules according to claim 1, which is characterized in that described control unit is specifically used for:
During the Memory Controller Hub accesses the first memory block in the memory modules, to first memory block
The mapping of data bit width is carried out, to provide the virtual memory space to the Memory Controller Hub.
3. memory modules according to claim 2, which is characterized in that described control unit is specifically used for:
According to the bit wide mapping relations between first memory block corresponding bit wide L and bit wide L2, by the Memory control
The data-signal that the bit wide of device output is L is split as the downlink data signal that N number of bit wide is L2；
According to the addressing mapping relations between first memory block corresponding bit wide L1 and bit wide L2, by N number of bit wide
The data-signal that K1 bit wide is L1 is spliced into for the downlink data signal of L2；
The data-signal that the K1 bit wide is L1 is written in K1 memory grain of first memory block；Wherein, K1 <
=N, and K1 is positive integer.
4. memory modules according to claim 2, which is characterized in that described control unit is specifically used for:
The data-signal that K2 bit wide is L1 is read from K2 memory grain of first memory block；
According to the addressing mapping relations between first memory block corresponding bit wide L1 and bit wide L2, by the K2 bit wide
The upstream data signals that N group bit wide is L2 are split as the data-signal of L1, and every group includes upper line number that L1/L2 bit wide is L2
It is believed that number；
According to the bit wide mapping relations between first memory block corresponding bit wide L and bit wide L2, it is by the N group bit wide
The upstream data signals of L2 merge into the data-signal that L1/L2 bit wide is L, are sequentially output to the Memory Controller Hub；Wherein,
K2≤N, and K2 is positive integer.
5. memory modules according to claim 3 or 4, which is characterized in that described control unit is also used to:
N number of memory grain in first memory block is serially addressed, to obtain addressing sequence；
Memory address in the addressing sequence is split as L1*N/L2 address field, the memory address category in each address field
In the address being adapted to bit wide L2；
The L1*N/L2 address field is divided into N number of group of addresses；
The mapping relations between the addressing sequence and N number of group of addresses are established as between the bit wide L1 and bit wide L2
Address mapping relations.
6. memory modules according to claim 5, which is characterized in that described control unit is specifically used for: by the L1*N/
The address field for belonging to same memory grain in L2 address field is divided into a group of addresses.
7. according to the described in any item memory modules of claim 2-6, which is characterized in that described control unit is also used to:
According to the memory address being adapted to bit wide L2 that the Memory Controller Hub exports, audit memory block number and memory address
Scope map table, to obtain the first memory block number；
From at least one described memory block, determine that first memory block is numbered described in identified memory block conduct
First memory block.
8. memory modules according to claim 1-6, which is characterized in that described control unit is also used to: according to
Configuration-direct, the memory grain number N that configuration bit wide L1, bit wide L2 and each memory block include.
9. a kind of exchange chip characterized by comprising control unit, the uplink port group being connect with Memory Controller Hub and
Multiple downlink port groups that each memory grain is correspondingly connected at least one memory block for including with memory modules；The control
Unit is connect with the uplink port and the multiple downlink port group respectively；
Described control unit is used for: being provided and the memory control based at least one described memory block to the Memory Controller Hub
The compatible virtual memory space of bit wide L of device processed, the bit wide of the virtual memory space are L2, and L=L2*N, L2 < L1,
L1, L2, N are positive integer.
10. exchange chip according to claim 9, which is characterized in that described control unit is specifically used for:
During the Memory Controller Hub accesses the first memory block in the memory modules, to first memory block
The mapping of data bit width is carried out, to provide the virtual memory space to the Memory Controller Hub.
11. exchange chip according to claim 10, which is characterized in that described control unit is specifically used for:
According to the bit wide mapping relations between first memory block corresponding bit wide L and bit wide L2, by the Memory control
The data-signal that the bit wide of device output is L is split as the downlink data signal that N number of bit wide is L2；
According to the addressing mapping relations between first memory block corresponding bit wide L1 and bit wide L2, by N number of bit wide
The data-signal that K1 bit wide is L1 is spliced into for the downlink data signal of L2；
The data-signal that the K1 bit wide is L1 is written in K1 memory grain of first memory block；Wherein, K1 <
=N, and K1 is positive integer.
12. exchange chip according to claim 10, which is characterized in that described control unit is specifically used for:
The data-signal that K2 bit wide is L1 is read from K2 memory grain of first memory block；
According to the addressing mapping relations between first memory block corresponding bit wide L1 and bit wide L2, by the K2 bit wide
The upstream data signals that N group bit wide is L2 are split as the data-signal of L1, and every group includes upper line number that L1/L2 bit wide is L2
It is believed that number；
According to the bit wide mapping relations between first memory block corresponding bit wide L and bit wide L2, it is by the N group bit wide
The upstream data signals of L2 merge into the data-signal that L1/L2 bit wide is L, are sequentially output to the Memory Controller Hub；Wherein,
K2≤N, and K2 is positive integer.
13. exchange chip according to claim 11 or 12, which is characterized in that described control unit is also used to:
N number of memory grain in first memory block is serially addressed, to obtain addressing sequence；
Memory address in the addressing sequence is split as L1*N/L2 address field, the memory address category in each address field
In the address being adapted to bit wide L2；
The L1*N/L2 address field is divided into N number of group of addresses；
The mapping relations between the addressing sequence and N number of group of addresses are established as between the bit wide L1 and bit wide L2
Address mapping relations.
14. according to the described in any item exchange chips of claim 9-13, which is characterized in that further include: with the multiple downlink
Port set multiple port driving units correspondingly；Described control unit by the multiple port driving unit respectively with institute
State multiple downlink port group connections.
15. a kind of electronic equipment characterized by comprising the described in any item memory modules of claim 1-8, Memory control
Device and processor；The processor accesses the memory modules by the Memory Controller Hub.
16. a kind of memory pool access method, which is characterized in that be suitable for memory modules, the memory modules include at least one
Block is deposited, each memory block includes N number of memory grain that bit wide is L1, which comprises
It, will be interior according to the bit wide mapping relations between the corresponding bit wide L and bit wide L2 of the first memory block in the memory modules
The data-signal that the bit wide of memory controller output is L is split as the downlink data signal that N number of bit wide is L2；
According to the addressing mapping relations between first memory block corresponding bit wide L1 and bit wide L2, by N number of bit wide
The data-signal that K1 bit wide is L1 is spliced into for the downlink data signal of L2；
The data-signal that the K1 bit wide is L1 is written in K1 memory grain of first memory block；Wherein, L=
L2*N, L2 < L1, K1≤N, and L1, L2, K1, N are positive integer.
17. according to the method for claim 16, which is characterized in that further include:
The data-signal that K2 bit wide is L1 is read from K2 memory grain of first memory block；
According to the addressing mapping relations between the bit wide L1 and bit wide L2, the data-signal that the K2 bit wide is L1 is split
The upstream data signals for being L2 for N group bit wide, every group include L1/L2 bit wide be L2 upstream data signals；
According to the bit wide mapping relations between the bit wide L and bit wide L2, the upstream data signals that the N group bit wide is L2 are closed
And be the data-signal that L1/L2 bit wide is L, it is sequentially output to the Memory Controller Hub；Wherein, K2≤N, and K2 be positive it is whole
Number.
18. according to the method for claim 16, which is characterized in that according to the corresponding bit wide L1 of first memory block
Before addressing mapping relations between bit wide L2, the method also includes:
N number of memory grain in first memory block is serially addressed, to obtain addressing sequence；
Memory address in the addressing sequence is split as L1*N/L2 address field, the memory address category in each address field
In the address being adapted to bit wide L2；
The L1*N/L2 address field is divided into N number of group of addresses；
The mapping relations between the addressing sequence and N number of group of addresses are established as the corresponding position of first memory block
Addressing mapping relations between wide L1 and bit wide L2.
19. according to the method for claim 18, which is characterized in that it is described the L1*N/L2 address field is divided into it is N number of
Group of addresses, comprising:
The address field for belonging to same memory grain in the L1*N/L2 address field is divided into a group of addresses.
20. according to the method for claim 19, which is characterized in that N number of memory in first memory block
Grain is serially addressed, to obtain before addressing sequence, the method also includes:
According to configuration-direct, bit wide L1 is configured, the memory grain number N that bit wide L2 and each memory block include.
21. the described in any item methods of 6-20 according to claim 1, which is characterized in that in the data-signal for being L by the bit wide
It is split as before the downlink data signal that bit wide is L2, the method also includes:
According to the memory address being adapted to bit wide L2 that the Memory Controller Hub exports, audit memory block number and memory address
Scope map table, to obtain the first memory block number；
From at least one described memory block, determine that first memory block is numbered described in identified memory block conduct
First memory block.
22. a kind of memory pool access method, which is characterized in that be suitable for memory modules, the memory modules include at least one
Block is deposited, each memory block includes N number of memory grain that bit wide is L1, which comprises
The data-signal that K2 bit wide is L1 is read from K2 memory grain of the first memory block in the memory modules；
According to the addressing mapping relations between first memory block corresponding bit wide L1 and bit wide L2, by the K2 bit wide
The upstream data signals that N group bit wide is L2 are split as the data-signal of L1, and every group includes upper line number that L1/L2 bit wide is L2
It is believed that number；
According to the bit wide mapping relations between first memory block corresponding bit wide L and bit wide L2, it is by the N group bit wide
The upstream data signals of L2 merge into the data-signal that L1/L2 bit wide is L, are sequentially output to Memory Controller Hub；Wherein, L=
L2*N, L2 < L1, K2≤N, and L1, L2, K2, N are positive integer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711132919.6A CN109783395B (en) | 2017-11-15 | 2017-11-15 | Memory access method, exchange chip, memory module and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711132919.6A CN109783395B (en) | 2017-11-15 | 2017-11-15 | Memory access method, exchange chip, memory module and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109783395A true CN109783395A (en) | 2019-05-21 |
| CN109783395B CN109783395B (en) | 2023-03-31 |
Family
ID=66495338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711132919.6A Active CN109783395B (en) | 2017-11-15 | 2017-11-15 | Memory access method, exchange chip, memory module and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109783395B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111328257A (en) * | 2020-03-11 | 2020-06-23 | 广东省电信规划设计院有限公司 | Data synchronization method and device for upper computer and lower computer |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11265315A (en) * | 1997-10-31 | 1999-09-28 | Hewlett Packard Co <Hp> | High-speed and compact address bit route specifying mechanism for supporting various dram bank sizes and plural interleaving mechanisms |
| JPH11282747A (en) * | 1998-03-27 | 1999-10-15 | Brother Ind Ltd | Device and method for control of storage device in data processing system |
| US20080183985A1 (en) * | 2007-01-30 | 2008-07-31 | Mark David Bellows | Rank Select Operation Between an XIO Interface and a Double Data Rate Interface |
| US20090177861A1 (en) * | 2008-01-08 | 2009-07-09 | Mario Mazzola | System and methods for memory expansion |
| CN101971150A (en) * | 2008-01-08 | 2011-02-09 | 思科技术公司 | System and methods for memory expansion |
| CN103154917A (en) * | 2010-06-04 | 2013-06-12 | 思科技术公司 | Memory expansion using rank aggregation |
| CN103488436A (en) * | 2013-09-25 | 2014-01-01 | 华为技术有限公司 | Memory extending system and memory extending method |
| CN106155577A (en) * | 2015-04-23 | 2016-11-23 | 华为技术有限公司 | The access method of exented memory, equipment and system |
-
2017
- 2017-11-15 CN CN201711132919.6A patent/CN109783395B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11265315A (en) * | 1997-10-31 | 1999-09-28 | Hewlett Packard Co <Hp> | High-speed and compact address bit route specifying mechanism for supporting various dram bank sizes and plural interleaving mechanisms |
| JPH11282747A (en) * | 1998-03-27 | 1999-10-15 | Brother Ind Ltd | Device and method for control of storage device in data processing system |
| US20080183985A1 (en) * | 2007-01-30 | 2008-07-31 | Mark David Bellows | Rank Select Operation Between an XIO Interface and a Double Data Rate Interface |
| US20090177861A1 (en) * | 2008-01-08 | 2009-07-09 | Mario Mazzola | System and methods for memory expansion |
| CN101971150A (en) * | 2008-01-08 | 2011-02-09 | 思科技术公司 | System and methods for memory expansion |
| CN103154917A (en) * | 2010-06-04 | 2013-06-12 | 思科技术公司 | Memory expansion using rank aggregation |
| CN103488436A (en) * | 2013-09-25 | 2014-01-01 | 华为技术有限公司 | Memory extending system and memory extending method |
| CN106155577A (en) * | 2015-04-23 | 2016-11-23 | 华为技术有限公司 | The access method of exented memory, equipment and system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111328257A (en) * | 2020-03-11 | 2020-06-23 | 广东省电信规划设计院有限公司 | Data synchronization method and device for upper computer and lower computer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109783395B (en) | 2023-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104657284B (en) | The extended utilization area of storage device | |
| CN104704563B (en) | Flash memory controller with double mode pin | |
| CN105612501A (en) | System and method for uniform interleaving of data across a multiple-channel memory architecture with asymmetric storage capacity | |
| CN104423888B (en) | Method for writing data, memorizer control circuit unit and memory storage apparatus | |
| CN106681652B (en) | Storage management method, memorizer control circuit unit and memory storage apparatus | |
| CN104054133B (en) | Programmed via the multipurpose register of every DRAM addressabilities pattern | |
| CN107608910A (en) | For realizing the apparatus and method of the multi-level store hierarchy with different operation modes | |
| CN106453730A (en) | Smart card and terminal equipment | |
| CN104079686A (en) | Setting method and distributing method for terminal equipment MAC address | |
| CN104217768B (en) | A kind of detection method and device of eMMC embedded memories | |
| CN106681932A (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN106575273A (en) | Systems and methods for expanding memory for system on chip | |
| CN106598548A (en) | Solution method and device for read-write conflict of storage unit | |
| CN103258173A (en) | Wearable device, write-in system and write-in method for card | |
| CN105988950B (en) | Storage management method, memorizer control circuit unit and memory storage apparatus | |
| CN109783395A (en) | Memory pool access method, exchange chip, memory modules and electronic equipment | |
| CN102486719B (en) | Intelligent memory card and transaction-writing method thereof | |
| CN100452907C (en) | Data transmission method and device between user identification module and mobile terminal | |
| CN102890653A (en) | Instruction executing method, memory controller and memory storage device | |
| CN101788888A (en) | Method for realizing target end driver and target end driver | |
| CN103902298B (en) | Method to set up and the device of status information write with a brush dipped in Chinese ink by a kind of instruction set firmware | |
| CN203689503U (en) | Single-board system achieved based on field-programmable gate array | |
| CN107870878A (en) | Storage system, terminal and computer installation | |
| CN103731313B (en) | Counter and its implementation based on DDR SDRAM | |
| CN108958640B (en) | Memory management method, memory control circuit unit and memory storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |