CN109766233B - Detection circuit and method for sensing NBTI effect delay of processor - Google Patents
Detection circuit and method for sensing NBTI effect delay of processor Download PDFInfo
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Abstract
The invention belongs to the field of high-performance processor reliability, and relates to a detection circuit for sensing processor NBTI effect delay, which comprises an aging detection module and an aging measurement module, and is characterized in that the input end of the aging detection module is connected with the output end of a processor critical path, the output end of the aging detection module is connected with the input end of the aging measurement module through a multiplexer, and the output end of the aging measurement module outputs the delay amount of the processor critical path; according to the invention, the aging detection module converts the signal turnover information output by the processor critical path into the pulse signal, the aging measurement module processes and calculates the pulse signal to measure the delay amount of the critical path, the specific aging state of the processor can be accurately reflected, and fine-grained information is provided for protection.
Description
Technical Field
The invention relates to a detection circuit and a method for a processor, in particular to a detection circuit and a method for sensing NBTI effect delay of a processor, belonging to the field of high-performance processor reliability.
Background
According to the blueprint prediction of the international semiconductor technology, as the process size is continuously reduced, the circuit aging caused by Negative Bias Temperature Instability (NBTI) is gradually becoming a key factor influencing the chip reliability and reducing the service life of the chip. Threshold voltage Δ V of PMOS due to NBTI effect TH May reach +100 mV, resulting in an increase in overall latency of the data path, leading to the occurrence of errors. For microprocessing in systems such as aerospace, automotive electronics and the like, the life cycle of the microprocessing is very long (more than 10 years), the working environment is worse, and the aging of the processor can be accelerated by long-time high-temperature, high-pressure and high-load work, so that a severe challenge is brought to the life cycle of the processor.
In the design work of a microprocessor circuit, under given environmental conditions and working modes, how to accurately and quickly calculate the NBTI degradation amount of each path in the circuit is a very critical problem. Therefore, the method for accurately predicting the logic delay of the processor combination under the influence of the NBTI effect has great significance on the reliability circuit design and the circuit key path selection analysis.
In 2007, the Sensor circuit is embedded into a standard trigger by the s.mitra group of stanford university, and the Sensor circuit delays a clock signal by using a delay unit to form a detection window to monitor the delay output in the upper-stage combinational logic. Subsequently, some work has improved it, for example, 2011, j.semi proposes an online adaptive aging sensor prediction circuit, and integrates the monitoring function by using a feedback circuit, thereby significantly improving the performance. The main drawbacks of this type of process are: the aging Sensor can only judge whether the circuit aging causes the fault, cannot measure the actual aging degree of the circuit, and cannot provide necessary information for the aging maintenance of the circuit; the margin of the time sequence in the critical path cannot be detected specifically, fine-grained guidance is difficult to provide for the reliability design of the processor, and in addition, the large use of the aging Sensor increases the circuit load, increases the circuit power consumption and reduces the circuit performance.
Disclosure of Invention
The invention aims to provide a detection circuit and a method for sensing NBTI effect delay of a processor aiming at the problem that circuit delay is caused by aging failure of a processor circuit caused by the existing NBTI effect.
In order to realize the technical purpose, the technical scheme of the invention is as follows: the detection circuit for sensing the NBTI effect delay of the processor comprises an aging detection module and an aging measurement module, and is characterized in that the input end of the aging detection module is connected with the output end of a processor critical path, the output end of the aging detection module is connected with the input end of the aging measurement module through a multiplexer, and the output end of the aging measurement module outputs the delay amount of the processor critical path.
Further, the aging detection module comprises a master latch D1, a slave latch D2, a slave latch D3, an inverter NOT1, an inverter NOT2, a NAND gate NAND1, a NAND gate NAND2 and a NAND gate NAND3, wherein the signal inversion information output by the critical path is input to the input D end of the master latch D1, the output QM end of the master latch D1 is respectively connected with the input D end of the slave latch D2 and the input end of the inverter NOT1, the output QMN end of the master latch D1 is connected with the input end of the inverter NOT2, the output Q end of the slave latch D2 is connected with the input D end of the slave latch D3, the output QS end of the slave latch D3 and the output end of the inverter NOT1 are respectively connected with the input end of the NAND gate NAND1, the output QSN end of the slave latch D3 and the output end of the inverter NOT2 are respectively connected with the input end of the NAND gate NAND2, and the output PF of the NAND gate NAND1 and the output PR of the NAND gate NAND2 are respectively connected with the input end of a multiplexer; the output end of the multiplexer is connected with the input end of the NAND gate NAND3, and the output end of the NAND gate NAND3 outputs a critical path pulse signal.
Further, the aging measurement module comprises a ring oscillator module, a delay line module and an N-bit counter module, wherein the input end of the delay line module is connected with the output end of the NAND gate NAND3, the input end of the ring oscillator module is connected with the output end of the delay line module, the output ends of the ring oscillator module and the delay line module are connected with the input end of the N-bit counter module, and the output end of the N-bit counter module outputs the delay amount of the processor critical path.
Furthermore, the ring oscillator module is formed by connecting a nand gate and N and gates in series to form a ring oscillation loop, wherein the nand gate generates positive feedback.
Further, the oscillation period of the ring oscillator module is T RO =Nt delay Where N is the number of AND gates, t delay The oscillation period of the circuit can be changed by changing the number of AND gates in the circuit for the propagation delay time of the gate.
Furthermore, the delay line module is formed by connecting a plurality of NOT gates in series, and the frequency of the delay line module is greater than the oscillation frequency of the ring oscillator module.
Further, the N-bit counter module calculates a delay amount of the pulse signal, and the calculation formula is: pulsewidth=k*T RO +（N 1 -N 2 ）*T delay Wherein T is RO Is the period of the ring oscillator module, T delay K is the period of the delay line module and is the number from the number of the N-bit counter module to the number of the pulse edges.
Furthermore, the processor comprises a plurality of critical paths, each critical path is connected with an aging detection module, and each aging detection module is connected with the aging measurement module through two multiplexers.
The aging detection module is connected with the aging detection module, the aging measurement module and the multiplexer respectively.
In order to further achieve the above technical object, the present invention further provides a processor detection method for detecting NBTI effect circuit delay, which is characterized by comprising the following steps:
the method comprises the following steps: connecting a trigger at the tail end of each key path of a processor with an aging detection module to obtain signal turnover information of the key path;
step two: each aging detection module is connected with two multiplexers, the multiplexers receive information output by the aging detection modules, judge which path information is input according to the control enabling signals output by the control modules, and output the path information;
step three: inputting the path information into a NAND gate NAND3, converting the path information into a pulse signal through the NAND gate NAND3, and outputting the pulse signal to an aging measurement module;
step four: the pulse signal is input into the delay line module, pulse information is completely transmitted to the N-bit counter module through the delay line module, and meanwhile delay time of the quantization path is calculated through the ring oscillator module and the N-bit counter module.
Compared with the traditional processing circuit for sensing the time delay of the NBTI effect circuit, the invention has the following advantages:
(1) The invention utilizes the enable signal to control the aging detection module to be opened or closed, so that the module is in a closed state when not in work, the dynamic power consumption of the whole circuit can be better reduced, and meanwhile, the aging detection module has a simple structure, has lower area and power consumption overhead, and can be conveniently embedded into a processor;
(2) The method can measure the delay information of the critical path in a fine-grained manner, can accurately reflect the specific aging state of the processor, and provides fine-grained information for protection;
(3) Compared with the traditional ring oscillator, the ring oscillator module has more flexible structure and frequency adjustment, and can obtain a corresponding circuit structure after Electronic Design Automation (EDA) software synthesis;
(4) All structures and modules of the invention are realized in RTL level, and can be better integrated with the IP core of the processor.
Drawings
Fig. 1 is a block diagram of the overall structure of the present invention.
Fig. 2 is a schematic circuit diagram of the aging detection module of the present invention.
FIG. 3 is an architecture diagram of the multiplexer and aging measurement module of the present invention.
Figure 4 is a circuit schematic of a ring oscillator module of the present invention.
FIG. 5 is a schematic diagram of the embedded position of the aging detection module in the processor according to the present invention.
FIG. 6 is a timing diagram of the aging detection module of the present invention.
FIG. 7 is a timing diagram of the aging measurement module of the present invention.
Description of the reference numerals: the system comprises a 1-aging detection module, a 2-aging measurement module, a 21-ring oscillator module, a 22-delay line module, a 23-N bit counter module, a 3-multiplexer and a 4-control module.
Detailed description of the preferred embodiments
The invention is further illustrated by the following specific figures and examples.
Example 1: as shown in fig. 1, the detection circuit for sensing processor NBTI effect delay in embodiment 1 includes an aging detection module 1 and an aging measurement module 2, an input end of the aging detection module 1 is connected to an output end of a processor critical path, an output end of the aging detection module 1 is connected to an input end of the aging measurement module 2 through two multiplexers 3, and an output end of the aging measurement module 2 outputs a delay amount of the processor critical path;
the aging detection device further comprises a control module 4, wherein the control module 4 is respectively connected with the aging detection module 1, the aging measurement module 2 and the multiplexer 3.
As shown in fig. 2 and fig. 3, the aging detection module 1 includes a master latch D1, a slave latch D2, a slave latch D3, an inverter NOT1, an inverter NOT2, a NAND gate NAND1, a NAND gate NAND2, and a NAND gate NAND3, wherein the signal inversion information output by the critical path is input to the input D of the master latch D1, the output QM of the master latch D1 is connected to the input D of the slave latch D2 and the input of the inverter NOT1, the output QMN of the master latch D1 is connected to the input of the inverter NOT2, the output Q of the slave latch D2 is connected to the input D of the slave latch D3, the QS output end of the slave latch D3 and the output end of the inverter NOT1 are respectively connected with the input end of the NAND gate NAND1, the QSN output end of the slave latch D3 and the output end of the inverter NOT2 are respectively connected with the input end of the NAND gate NAND2, the PF output end of the NAND gate NAND1 and the PR output end of the NAND gate NAND2 are respectively connected with the input end of a multiplexer 3, a Control enable signal Control vector output by the Control module 4 is input to the EN end of the multiplexer 3, the output end of the multiplexer 3 is connected with the input end of the NAND gate NAND3, and the output end of the NAND gate NAND3 outputs a critical path pulse signal; meanwhile, the aging detection module 1 is controlled to be turned on or turned off through an enabling signal of the control module 3;
the aging detection module 1 captures signal turnover information of the critical path trigger through an input D end of the master latch D1, the NAND gate NAND2 and the NAND gate NAND3 process the information, the signal turnover information is converted to generate a pulse signal, and the pulse width of the pulse signal represents the timing margin of the circuit.
The aging measurement module 2 comprises a ring oscillator module 21, a delay line module 22 and an N-bit counter module 23, wherein the input end of the delay line module 22 is connected with the output end of an NAND gate NAND3, the input end of the ring oscillator module 21 is connected with the output end of the delay line module 22, the output ends of the ring oscillator module 21 and the delay line module 22 are connected with the input end of the N-bit counter module 23, and the output end of the N-bit counter module 23 outputs the delay amount of a processor critical path.
As shown in fig. 4, the ring oscillator module 21 is formed by a nand gate and N and gates connected in series to form a ring oscillator circuit; the ring oscillator module 21 has an oscillation period T RO =2Nt delay Where N is the number of AND gates, t delay The oscillation period of the circuit can be changed by changing the number of AND gates in the circuit for the transmission delay time of the gate;
the nand gate generates positive feedback, the N and gates connected in series play a role of delay buffering, the oscillation frequency of the output end is changed by changing the number of the gates and the types of the gates, meanwhile, the ring oscillator module 21 is not limited by the odd gates, and oscillation can be formed as long as the first gate is ensured to obtain the positive feedback;
the delay line module 22 is composed of a plurality of not gates connected in series, and the frequency of the delay line module 22 is greater than the oscillation frequency of the ring oscillator module 21.
The N-bit counter module 23 calculates the delay amount of the pulse signal, and the calculation formula is: pulsewidth=k*T RO +（N 1 -N 2 ）*T delay Wherein T is RO Is the period, T, of the ring oscillator module 21 delay K is the number of the pulse edges counted by the N-bit counter module 23 for the period of the delay line module 22.
As shown in fig. 5, the processor includes a plurality of critical paths Path1, path2 \8230 \ 8230;, path N, each critical Path is connected with an aging detection module 1, and each aging detection module 1 is connected with an aging measurement module 2 through two multiplexers 3; the aging detection module 1 is embedded in the processor, the tail end of the trigger of each critical path receives the signal information of the trigger of the critical path, one trigger can be the end point of a plurality of critical paths, namely the trigger can be in a plurality of critical paths, so that the triggers can share the same aging detector module 1, the number of the inserted aging detection modules 1 can be reduced, and the circuit area and the power consumption can be reduced; meanwhile, in order to reduce the power consumption and the area overhead, all the aging detection modules 1 share one aging measurement module 2, and the multiplexer 3 can identify and separate the information of each aging measurement module 2, so that the delay of each path is measured independently.
The control module 4 in this embodiment 1 includes a single chip microcomputer.
The method for detecting a processor to detect the delay of the NBTI effect circuit according to embodiment 1 above, comprising the steps of:
the method comprises the following steps: connecting a trigger at the tail end of each key path of a processor with an aging detection module 1 to obtain signal turnover information of the key path;
step two: each aging detection module 1 is connected with two multiplexers 3, the multiplexers 3 receive information output by the aging detection modules 1, control enabling signals are output according to a control module 4, information in which path is input is judged, and meanwhile path information is output;
as shown in fig. 6, which is a timing diagram of the aging detection module 1, CLK is a clock signal waveform, EN is an enable signal waveform, D is an input D-side signal waveform of the master latch D1, QM is an output-side signal waveform of the master latch D1, Q is an output Q-side signal waveform of the slave latch D2, QS is an output QS-side signal waveform of the slave latch D3, PF is a signal waveform of an output terminal of the NAND gate NAND1, and PR is a signal waveform of an output terminal of the NAND gate 2; the aging detection module 1 processes the signal turnover information of the critical path and outputs signal waveforms of PR and PF;
step three: inputting the waveforms of PR and PF signals into a NAND gate NAND3, converting the path information into pulse signals through the processing of an aging detection module 1 and the NAND gate NAND3, and outputting the pulse signals to an aging measurement module 2;
step four: inputting a pulse signal into a delay line module 22, completely transmitting pulse information to an N-bit counter module 4 through the delay line module 22, and calculating delay time of a quantization path through a ring oscillator module 21 and the N-bit counter module 23;
FIG. 7 is a timing diagram of the aging measurement module 2, where EN is the enable signal waveform, RO _ CLK is the waveform of the ring oscillator module 21, and T delay The waveform of the delay line module 22, pulse is the delay of the Pulse signal; the ring oscillator module 21 forms a ring loop with nand gates and gates, and generates a 0-1 cycle oscillation signal.
The present invention and its embodiments have been described above, and the description is not intended to be limiting, and the embodiments shown in the drawings are only one embodiment of the present invention, and the actual structure is not limited thereto. In summary, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A detection circuit for sensing NBTI effect delay of a processor comprises an aging detection module (1) and an aging measurement module (2), wherein the input end of the aging detection module (1) is connected with the output end of a processor critical path, the output end of the aging detection module (1) is connected with the input end of the aging measurement module (2) through two multiplexers (3), and the output end of the aging measurement module (2) outputs the delay amount of the processor critical path;
the aging detection module (1) comprises a master latch D1, a slave latch D2, a slave latch D3, an inverter NOT1, an inverter NOT2, an NAND gate NAND1, an NAND gate NAND2 and an NAND gate NAND3, wherein signal inversion information output by a critical path is input to an input D end of the master latch D1, an output QM end of the master latch D1 is respectively connected with an input D end of the slave latch D2 and an input end of the inverter NOT1, an output QMN end of the master latch D1 is connected with an input end of the inverter NOT2, an output Q end of the slave latch D2 is connected with an input D end of the slave latch D3, an output QS end of the slave latch D3 and an output end of the inverter NOT1 are respectively connected with an input end of the NAND gate NAND1, an output end PF of the NAND gate D1 and an output end PR of the NAND gate NAND2 are respectively connected with an input end of a multiplexer (3); the output end of the multiplexer (3) is connected with the input end of a NAND gate NAND3, and the output end of the NAND gate NAND3 outputs a critical path pulse signal;
the aging measurement module (2) comprises a ring oscillator module (21), a delay line module (22) and an N-bit counter module (23), wherein the input end of the delay line module (22) is connected with the output end of the NAND gate NAND3, the input end of the ring oscillator module (21) is connected with the output end of the delay line module (22), the output ends of the ring oscillator module (21) and the delay line module (22) are connected with the input end of the N-bit counter module (23), and the output end of the N-bit counter module (23) outputs the delay amount of a processor critical path;
the ring oscillator module (21) is formed by connecting a NAND gate and N AND gates in series to form a ring oscillation loop, wherein the NAND gate generates positive feedback;
the ring oscillator module (21) has an oscillation period T RO =2Nt delay Where N is the number of AND gates, t delay The oscillation period of the circuit can be changed by changing the number of AND gates in the circuit for the transmission delay time of the gate;
the delay line module (22) is formed by connecting a plurality of NOT gates in series, and the frequency of the delay line module (22) is greater than the oscillation frequency of the ring oscillator module (21);
the N-bit counter module (23) calculates the delay amount of the pulse signal, and the calculation formula is as follows: pulsewidth = k × T RO +（N 1 -N 2 ）*T delay Wherein T is RO Is the period, T, of the ring oscillator module (21) delay K is the period of the delay line module (22) and is the number from the number of the N-bit counter module (23) to the number of the pulse edges.
2. The circuit for detecting processor NBTI effect delay as claimed in claim 1, wherein: the processor comprises a plurality of critical paths, each critical path is connected with an aging detection module (1), and each aging detection module (1) is connected with an aging measurement module (2) through two multiplexers (3).
3. The circuit for detecting processor NBTI effect delay as claimed in claim 1, wherein: the aging detection device is characterized by further comprising a control module (4), wherein the control module (4) is respectively connected with the aging detection module (1), the aging measurement module (2) and the multiplexer (3).
4. A method for detecting the NBTI effect delay of a perceptual processor as defined in any one of claims 1 to 3, wherein the method is applied to a circuit for detecting the NBTI effect delay of the perceptual processor, comprising the steps of:
the method comprises the following steps: connecting a trigger at the tail end of each key path of a processor with an aging detection module (1) to obtain signal turnover information of the key path;
step two: each aging detection module (1) is connected with two multiplexers (3), the multiplexers (3) receive information output by the aging detection modules (1), control enabling signals are output according to a control module (4), information in which path is input is judged, and meanwhile path information is output;
step three: inputting the path information into a NAND gate NAND3, converting the path information into a pulse signal through the NAND gate NAND3, and outputting the pulse signal to an aging measurement module (2);
step four: pulse signals are input into a delay line module (22), pulse information is completely transmitted to an N-bit counter module (23) through the delay line module (22), and meanwhile delay time of a quantization path is calculated through a ring oscillator module (21) and the N-bit counter module (23).
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| CN110672943B (en) * | 2019-09-26 | 2022-11-08 | 宁波大学 | Aging detection sensor based on voltage comparator |
| CN113176482B (en) * | 2020-01-08 | 2023-03-07 | 中芯国际集成电路制造（天津）有限公司 | Test circuit, test system and test method thereof |
| CN111651946A (en) * | 2020-05-12 | 2020-09-11 | 江南大学 | Method for hierarchically identifying circuit gate based on workload |
| CN112834890B (en) * | 2020-12-29 | 2021-11-30 | 北京智芯微电子科技有限公司 | Circuit for detecting NBTI (negative bias temperature instability) degradation of PMOS (P-channel metal oxide semiconductor) device |
| CN112667024B (en) * | 2020-12-31 | 2023-10-20 | 海光信息技术股份有限公司 | Delay calculation circuit, chip running frequency acquisition method and device and electronic equipment |
| CN113125941B (en) * | 2021-04-19 | 2022-09-09 | 海光信息技术股份有限公司 | Detection method, detection system and detection device for chip design |
| CN113391193B (en) * | 2021-06-25 | 2023-11-21 | 合肥工业大学 | Circuit burn-in test method based on BIST structure and self-oscillating ring |
| CN113552190A (en) * | 2021-07-26 | 2021-10-26 | 电子科技大学长三角研究院(湖州) | Sensor assembly integral screening system and method for aging monitoring |
| CN117805594B (en) * | 2024-02-29 | 2024-05-07 | 北京壁仞科技开发有限公司 | Process monitor and chip aging test method thereof |
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