CN109765778B - Time-analog conversion circuit and single photon flight time measuring method - Google Patents

Abstract

The invention discloses a time-analog conversion circuit and a single photon flight time measuring method. The signal input logic unit converts the photon signal into a logic level, the input ends of the signal input logic unit respectively receive the photon signal, the start signal and the stop signal, and the output end of the signal input logic unit is connected with the input end of the timing unit; the timing unit comprises a current mirror structure for providing stable charging current, a current mirror structure for providing a current source and a timing capacitor, and the voltage of a polar plate of the timing capacitor is linearly increased along with time after the timing capacitor starts timing; the voltage holding unit is used for holding the voltage of the timing capacitor plate, the input end of the voltage holding unit is connected with the output end of the timing unit, the output end of the voltage holding unit is connected with the reading unit, and the reading unit reads a plate voltage signal. The manufacturing process of the invention is compatible with the CMOS process, the manufacturing cost is low and the yield is high. Meanwhile, the time-analog conversion circuit also has the advantages of high filling factor, high resolution and large measurement range.

Description

Time-analog conversion circuit and single photon flight time measuring method

Technical Field

The invention relates to a time-analog conversion circuit for measuring single photon time of flight (TOF) and a method for measuring the TOF by using the time-analog conversion circuit, in particular to a single photon time of flight detection circuit based on a Wilson current source and a measuring method.

Background

The Single-Photon Avalanche Diode (SPAD) has the obvious advantages of large Avalanche gain, high response speed, high detection efficiency, low cost, low power consumption and the like, can obtain time and space information of Photon signals, and has wide application prospects in the aspects of bioluminescence life detection, laser ranging, 3D imaging and the like. These applications require time-of-flight (TOF) measurements to obtain time-dependent single photon counting/timing results. The method for measuring the photon flight time mainly comprises a time-digital conversion circuit TDC and a time-analog conversion circuit TAC.

The detection time of the TDC is influenced by the time resolution, and along with the increase of the detection distance, the measured flight time can be lengthened, so that the chip area of the TDC circuit is increased rapidly, the filling factor of each pixel unit is reduced, and the power consumption is increased. The TAC circuit has a simpler circuit and a smaller circuit area than the TDC circuit. However, the conventional TAC circuit has a short time measurement range, typically from several nanoseconds to several tens of nanoseconds, and thus can measure a small distance. Therefore, the measurement range is increased under the condition of ensuring that the circuit area is smaller, and the improvement of the filling factor of the pixel unit is an urgent problem to be solved.

Disclosure of Invention

The purpose of the invention is as follows: aiming at the problems, the invention provides a time-analog conversion circuit with high filling factor, high resolution and large measurement range and a method for measuring single photon flight time.

The technical scheme is as follows: the technical scheme adopted by the invention is a time-analog conversion circuit, which comprises a signal input logic unit, a timing unit, a voltage holding unit and a reading unit; the signal input logic unit converts the photon signal into logic level, three input ends of the signal input logic unit respectively receive the photon signal, the start signal and the stop signal, and the output end of the signal input logic unit is connected with the input end of the timing unit; the timing unit comprises a current mirror structure for providing stable charging current, a current mirror structure for providing a current source and a timing capacitor; the voltage holding unit is used for holding the plate voltage of the timing capacitor, the input end of the voltage holding unit is connected with the output end of the timing unit, the output end of the voltage holding unit is connected with the reading unit, and the reading unit reads a plate voltage signal.

Further, the signal input logic unit includes an or gate and an RS flip-flop, the start signal and the stop signal are connected to an input end of the or gate, an output end of the or gate is connected to an R end of the RS flip-flop, an S end of the RS flip-flop receives the photon signal, and a Q end of the RS flip-flop is an output end of the signal input logic unit.

Furthermore, the current mirror structure for providing stable charging current in the timing unit comprises four NMOS tubes with grounded substrates; the grid electrode of the first NMOS tube is the input end of the timing unit, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the second NMOS tube is connected with the drain electrode of the fifth PMOS tube; the drain electrode of the fourth NMOS tube is externally connected with a bias current and is connected with the grid electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with a power supply VDD, and the source electrode of the fifth NMOS tube is grounded; the current mirror structure for providing a current source in the timing unit comprises four PMOS tubes; the grid electrodes of the third PMOS tube and the fourth PMOS tube are mutually connected and are connected with the drain electrode of the fifth PMOS tube, the source electrodes of the third PMOS tube and the fourth PMOS tube are both connected with a power supply VDD, and the drain electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected with the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, and is connected with the grid electrode of the second NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the sixth PMOS tube is connected with the upper polar plate of the timing capacitor, the upper polar plate is the output end of the timing unit, and the lower polar plate of the timing capacitor is grounded.

Furthermore, the voltage holding unit comprises a buffer circuit, an eighth PMOS transistor and a third NMOS transistor, and the output end of the timing unit is connected to the input end of the buffer circuit and the source electrode of the eighth PMOS transistor; the drain electrode of the eighth PMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the eighth PMOS tube is connected with the inverted signal clb of the reset signal, the grid electrode of the third NMOS tube is connected with the reset signal cl, and the source electrode of the third NMOS tube is grounded; the output end of the buffer circuit is the output of the voltage holding unit and is connected with the input end of the reading unit; the voltage holding unit further includes two transmission gate circuits, a first transmission gate having a C terminal and

the output end of the buffer circuit is respectively connected with the output end of the buffer circuit, the output end of the buffer circuit is connected with the output end of the buffer circuit, and the output end of the buffer circuit is connected with the output end of the buffer circuit; terminal C of the second transmission gate TG2

The input 1 of the buffer circuit is connected to the drain of the eighth PMOS transistor MP8, and the output 2 of the buffer circuit is connected to the substrate of the eighth PMOS transistor MP 8.

Furthermore, the buffer circuit comprises a current mirror structure and a push-pull amplifier, the current mirror structure comprises three PMOS tubes and two NMOS tubes, and the grid electrode of the thirteenth PMOS tube is the input end of the buffer circuit and is connected with the output end of the input logic unit; the drain electrode of the thirteenth PMOS tube and the drain electrode of the fourteenth PMOS tube are respectively connected with the drain electrodes of the seventh NMOS tube and the eighth NMOS tube, the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube, the source electrodes of the seventh NMOS tube and the eighth NMOS tube are grounded, and the drain electrode of the eighth NMOS tube is connected with the grid electrode; the source electrode of the thirteenth PMOS tube is connected with the source electrode of the fourteenth PMOS tube and is connected with the drain electrode of the twelfth PMOS tube, the grid electrode of the twelfth PMOS tube is connected with the direct current level vb, and the source electrode of the twelfth PMOS tube is connected with the power supply VDD; the fifteenth PMOS tube and the ninth NMOS tube form a push-pull amplifier, drain electrodes of the fifteenth PMOS tube and the ninth NMOS tube are connected with a grid electrode of the fourteenth PMOS tube and used as the output of the buffer circuit, and the grid electrodes of the fifteenth PMOS tube and the ninth NMOS tube are connected with a drain electrode of the thirteenth PMOS tube; the source electrode of the fifteenth PMOS tube is connected with the power supply VDD, and the source electrode of the ninth NMOS tube is grounded.

The method for measuring the single photon flight time by using the time-analog conversion circuit comprises the following steps:

(1) a reset stage: the circuit is reset, a reset signal cl is high level, and charges on a capacitor are discharged through an eighth PMOS tube and a third NMOS tube, so that the voltage on the capacitor is 0; then the reset signal is changed into low level, the eighth PMOS tube and the third NMOS tube are cut off, and the reset is finished;

(2) a waiting stage: before the photon signal arrives, the starting signal is at a high level, the photon signal is at a low level, the output signal of the logic unit is at a low level, at the moment, a first NMOS tube in the timing unit is cut off, a current mirror for providing stable charging current does not work, no current exists in a current source, a sixth PMOS tube in the timing unit is cut off, the voltage on a capacitor is 0, and the arrival of a photon pulse is waited;

(3) photon flight time detection stage: when the photon signal pulse arrives, the rising edge of the output signal of the logic unit arrives, the first NMOS tube in the timing unit is conducted, a current source formed by the first NMOS tube, the second NMOS tube, the fourth NMOS tube and the fifth NMOS tube provides stable charging current, the sixth PMOS tube in the timing unit is conducted, the sampling capacitor starts to charge, and the voltage value linearly increases along with the time; in the process of increasing the voltage value, the voltage holding unit prevents the charge on the capacitor from losing;

(4) a voltage reading stage: after exposure is finished, the stop signal is at a high level, the read signal is at a high level, the output signal of the input logic unit is changed into a low level, the sixth PMOS tube is in a cut-off state, the voltage on the capacitor is kept unchanged, the voltage holding unit prevents charge loss on the capacitor, the voltage amplitude is output through the buffer circuit, the time difference from the arrival of photons to the arrival of the stop signal is obtained through the linear relation between the output voltage and time, and time-analog conversion is realized.

Has the advantages that: compared with the existing time-analog conversion circuit for measuring the single photon flight time, the invention has the following advantages: 1. the time-analog converter provided by the invention measures the time from the arrival of the photon to the stop signal stop in the form of voltage amplitude, reduces the occupied area of a circuit, improves the filling coefficient of a pixel unit and is convenient for large-scale integration of a pixel array compared with a time-digital converter. 2. The time-analog converter provided by the invention has good holding performance, and when the simulation time is 1ms, the voltage change is about 1.967mv and is less than 1 LSB. 3. The current mirror part of the time-analog converter provided by the invention adopts a structure of input and output short circuit, reduces the consumption of voltage redundancy, obtains a larger reading range, and has good linearity, thereby having good time resolution. 4. The time-analog converter provided by the invention has the advantages of simple structure, less control signals, complete compatibility of the manufacturing process and the CMOS process, good performance consistency among all circuits, low manufacturing cost and high yield.

Drawings

FIG. 1 is a circuit diagram of the present invention;

FIG. 2 is a circuit diagram of the buffer circuit of the present invention;

FIG. 3 is a timing diagram of the operation of the present invention;

fig. 4 is a graph of simulation results of the present invention.

Detailed Description

The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.

Fig. 1 is a circuit diagram of a time-to-analog conversion circuit according to the present invention. The circuit comprises a signal input logic unit, a timing unit, a voltage holding unit and a reading unit.

The signal input logic unit comprises an OR gate and an RS trigger, a start signal and a stop signal are connected with the input end of the OR gate, the output end of the OR gate is connected with the R end of the RS trigger, the S end of the RS trigger receives a photon signal, and the Q end of the RS trigger is the output end of the signal input logic unit.

The timing unit comprises a current mirror structure for providing stable charging current, a current mirror structure for providing a current source and a timing capacitor. The current mirror structure for providing stable charging current comprises four NMOS transistors (a first NMOS transistor MN1, a second NMOS transistor MN2, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5) with substrates all grounded. The grid electrode of the first NMOS transistor MN1 is the input end of the timing unit, the source electrode of the first NMOS transistor MN1 is grounded, and the drain electrode of the first NMOS transistor MN2 is connected with the source electrode of the second NMOS transistor MN 2; the grid electrode of the second NMOS transistor MN2 is connected with the grid electrode of the fourth NMOS transistor MN4, and the drain electrode of the second NMOS transistor MN2 is connected with the drain electrode of the fifth PMOS transistor MP 5; the drain electrode of the fourth NMOS tube MN4 is externally connected with a bias current and is connected with the grid electrode of the fourth NMOS tube MN4, and the source electrode of the fourth NMOS tube MN5 is connected with the drain electrode of the fifth NMOS tube MN 5; the gate of the fifth NMOS transistor MN5 is connected to the power supply VDD, and the source is grounded. The current mirror structure for providing the current source comprises four PMOS tubes (a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5 and a sixth PMOS tube MP 6); the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to each other and to the drain of the fifth PMOS transistor MP5, the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the power supply VDD, and the drains of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are respectively connected to the source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP 6; the grids of the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected with each other and are connected with the grid of the second NMOS tube; the drain of the fifth PMOS transistor MP5 is connected to the drain of the second NMOS transistor MN2, the drain of the sixth PMOS transistor MP6 is connected to the upper plate of the timing capacitor, which is the output terminal of the timing unit, and the lower plate of the timing capacitor is grounded.

The voltage holding unit includes a buffer circuit, an eighth PMOS transistor MP8, and a third NMOS transistor MN 3. The output end of the current mirror structure in the timing unit is connected with the input end of the buffer circuit and the source electrode of the eighth PMOS tube MP 8; the drain of the eighth PMOS transistor MP8 is connected to the drain of the third NMOS transistor MN3, the gate thereof is connected to the inverted signal clb of the reset signal, the source of the third NMOS transistor MN3 is grounded, and the gate thereof is connected to the reset signal cl. The output end of the buffer circuit is the output of the voltage holding unit and is connected with the input end of the reading unit.

The voltage holding unit further comprises twoAnd a transmission gate circuit. A first transmission gate TG1 is arranged between the output end of the buffer circuit and the drain electrode of the fourth PMOS transistor MP4 in the timing unit, and the C end thereof is connected with

The terminals respectively receive the signal in and the inverted signal inb thereof, the output 1 thereof is connected with the fourth PMOS transistor MP4, and the output 2 thereof is connected with the output terminal of the buffer circuit. Terminal C of the second transmission gate TG2

The ends of the NMOS transistor are respectively connected with the grid electrode of the eighth PMOS transistor and the grid electrode of the third NMOS transistor, and the C ends of the NMOS transistor and the NMOS transistor are connected

The terminals also receive a reset signal cl and its inverse clb, respectively. The input 1 of the second transmission gate TG2 is connected to the drain of the eighth PMOS transistor MP8, and the output 2 thereof is connected to the substrate of the eighth PMOS transistor MP8 and the output terminal of the buffer circuit.

The sensing unit comprises a tenth NMOS transistor MN10, a source of which is connected to the output terminal of the buffer circuit, a gate of which is connected to the sensing signal, and a drain of which is the output of the whole time-analog conversion circuit and outputs the voltage amplitude of the capacitor terminal.

As shown in fig. 2, the buffer circuit includes a current mirror structure and a push-pull amplifier. The current mirror structure comprises three PMOS tubes and two NMOS tubes. The thirteenth PMOS transistor MP13 is an input transistor, and its gate is an input terminal of the buffer circuit, and is connected to the output terminal of the input logic unit to receive the signal in. The twelfth PMOS transistor MP12 serves as a current source of the current mirror, and has a gate connected to the dc level vb, a source connected to the power supply VDD, and a drain connected to the source of the thirteenth PMOS transistor MP 13. The source electrodes of the thirteenth PMOS tube MP13 and the fourteenth PMOS tube MP14 are connected, the drain electrodes of the thirteenth PMOS tube MP13 and the fourteenth PMOS tube MP14 are respectively connected with the drain electrodes of the seventh NMOS tube MN7 and the eighth NMOS tube MN8, the grid electrodes of the seventh NMOS tube MN7 and the eighth NMOS tube MN8 are connected, the source electrodes of the seventh NMOS tube MN7 and the eighth NMOS tube MN8 are grounded, and the grid electrode and the drain electrode of the eighth NMOS tube MN8 are connected. The fifteenth PMOS transistor MP15 and the ninth NMOS transistor MN9 form a push-pull amplifier, the grids of the two transistors are connected and are connected with the drain electrode of the thirteenth PMOS transistor MP13, the drain electrodes of the two transistors are connected and are connected with the other input transistor of the current mirror, namely the grid electrode of the fourteenth PMOS transistor MP14, and the output of the buffer circuit is used for realizing the structure of input-output short circuit. The source of the fifteenth PMOS transistor MP15 is connected to the power supply VDD, and the source of the ninth NMOS transistor MN9 is connected to ground.

As shown in fig. 3, the work flow of the whole circuit includes four phases, namely, a reset phase, a waiting phase, a photon flight time detection phase, and a voltage readout phase.

(1) A reset stage: before the pixel array is exposed, the circuit is reset, the reset signal cl is in a high level, and the charge on the capacitor C is discharged through the eighth PMOS tube MP8 and the third NMOS tube MN3, so that the voltage on the capacitor C is 0; then the reset signal changes to low level, the eighth PMOS transistor MP8 and the third NMOS transistor MN3 are cut off, and the reset is completed;

(2) a waiting stage: before the photon signal arrives, the starting signal is at a high level, the photon signal is at a low level, the output signal of the logic unit is at a low level, at the moment, the first NMOS tube MN1 in the timing unit is cut off, the current mirror for providing stable charging current does not work, no current exists in the current source, the sixth PMOS tube MP6 in the timing unit is cut off, the voltage on the capacitor C is 0, and the arrival of a photon pulse is waited;

(3) photon flight time detection stage: when a Photon signal arrives, Photon is at a high level, the rising edge of an output signal of the logic unit arrives, a first NMOS tube MN1 in the timing unit is conducted, a current source formed by the first NMOS tube MN1, a second NMOS tube MN2, a fourth NMOS tube MN4 and a fifth NMOS tube MN5 provides stable charging current, the voltage value vp output by the grid electrode of the second NMOS tube MN2 is about 800mv, a sixth PMOS tube MP6 in the timing unit is conducted, the sampling capacitor C starts to charge, and the voltage value linearly increases along with time. The voltage value on the capacitor is input to the substrate of the eighth PMOS transistor MP8 and the second transmission gate through the buffer circuit, and is input to the drains of the eighth PMOS transistor MP8 and the third NMOS transistor MN3 through the transmission gate, so as to prevent the charge on the capacitor from losing. In addition, the voltage value on the capacitor is input to the first transmission gate through the buffer circuit, when the falling edge of the in signal arrives, the first transmission gate operates normally, the output voltage is copied to the drain terminal of the fourth PMOS transistor MP4 through the transmission gate, and the charge on the capacitor is prevented from being lost to the substrate of the sixth PMOS transistor MP 6. When the exposure time is over, the circuit enters the next readout phase.

(4) A voltage reading stage: after the exposure is finished, the stop signal is at a high level, the read signal is at a high level, the in signal becomes at a low level again, the sixth PMOS transistor MP6 is in a cut-off state again, the voltage on the capacitor C remains unchanged, the voltage output by the buffer circuit also remains unchanged, and the output voltage is in a linear relationship with time, so that the time from the arrival of the photon to the arrival of the stop signal can be obtained by measuring the output voltage, and the time-analog conversion can be realized.

The invention simulates the linear time-analog conversion circuit based on the capacitor charging based on the standard 0.18 mu m CMOS process, and the simulation parameters are as follows: the timing capacitor C is 110fF, a Photon signal is set as a narrow pulse with the pulse width of 0.2ns, and the time period from a start signal to a stop signal is set as 120 ns; based on the simulation parameters, the invention carries out the simulation with the time length of 200ns and obtains a simulation result diagram as shown in FIG. 4. In the figure, the abscissa represents simulation time, and the ordinate represents the voltage value at the output terminal. It can be seen that, when the external Photon signal Photon arrives, in changes to high level, so that the sixth PMOS transistor MP6 is turned on, the voltage on the capacitor increases linearly, the output signal Vm of the buffer circuit also increases linearly with time, when the read signal read is high level, the voltage value on the capacitor is read out to obtain the output voltage out of the circuit, and the time from the Photon arrival to the stop signal arrival can be obtained by calculation.

Claims (6)

1. A time-to-analog conversion circuit, characterized by: the circuit comprises a signal input logic unit, a timing unit, a voltage holding unit and a reading unit; the signal input logic unit converts the photon signal into logic level, three input ends of the signal input logic unit respectively receive the photon signal, the start signal and the stop signal, and the output end of the signal input logic unit is connected with the input end of the timing unit; the timing unit comprises a current mirror structure for providing stable charging current, a current mirror structure for providing a current source and a timing capacitor; the voltage holding unit is used for holding the plate voltage of the timing capacitor, the input end of the voltage holding unit is connected with the output end of the timing unit, the output end of the voltage holding unit is connected with the reading unit, and the reading unit reads a plate voltage signal.

2. The time-to-analog conversion circuit of claim 1, wherein: the signal input logic unit comprises an OR gate and an RS trigger, a start signal and a stop signal are connected with the input end of the OR gate, the output end of the OR gate is connected with the R end of the RS trigger, the S end of the RS trigger receives a photon signal, and the Q end of the RS trigger is the output end of the signal input logic unit.

3. The time-to-analog conversion circuit of claim 1, wherein: the current mirror structure for providing stable charging current in the timing unit comprises four NMOS tubes with grounded substrates; the grid electrode of the first NMOS tube is the input end of the timing unit, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the second NMOS tube is connected with the drain electrode of the fifth PMOS tube; the drain electrode of the fourth NMOS tube is externally connected with a bias current and is connected with the grid electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with a power supply (VDD), and the source electrode is grounded;

the current mirror structure for providing a current source in the timing unit comprises four PMOS tubes; the grid electrodes of the third PMOS tube and the fourth PMOS tube are mutually connected and are connected with the drain electrode of the fifth PMOS tube, the source electrodes of the third PMOS tube and the fourth PMOS tube are both connected with a power supply (VDD), and the drain electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected with the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, and is connected with the grid electrode of the second NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the sixth PMOS tube is connected with the upper polar plate of the timing capacitor, the upper polar plate is the output end of the timing unit, and the lower polar plate of the timing capacitor is grounded.

4. The time-to-analog conversion circuit of claim 3, wherein: the voltage holding unit comprises a buffer circuit, an eighth PMOS tube and a third NMOS tube, and the output end of the timing unit is connected with the input end of the buffer circuit and the source electrode of the eighth PMOS tube; the drain electrode of the eighth PMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the eighth PMOS tube is connected with an inverted signal (clb) of the reset signal, the grid electrode of the third NMOS tube is connected with the reset signal (c1), and the source electrode and the substrate of the third NMOS tube are both grounded; the output end of the buffer circuit is the output of the voltage holding unit and is connected with the input end of the reading unit;

the voltage holding unit further includes two transmission gate circuits, a first transmission gate having a C terminal and

the output end of the buffer circuit is respectively connected with the output end of the buffer circuit, the output end of the buffer circuit is connected with the output end of the fourth PMOS tube, and the output end of the buffer circuit is connected with the output end of the buffer circuit; terminal C of the second transmission gate TG2

The input 1 of the buffer circuit is connected to the drain of the eighth PMOS transistor MP8, and the output 2 of the buffer circuit is connected to the substrate of the eighth PMOS transistor MP 8.

5. The time-to-analog conversion circuit of claim 4, wherein: the buffer circuit comprises a current mirror structure and a push-pull amplifier, the current mirror structure comprises three PMOS tubes and two NMOS tubes, and the grid electrode of the thirteenth PMOS tube is the input end of the buffer circuit and is connected with the output end of the input logic unit; the drain electrode of the thirteenth PMOS tube and the drain electrode of the fourteenth PMOS tube are respectively connected with the drain electrodes of the seventh NMOS tube and the eighth NMOS tube, the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube, the source electrodes of the seventh NMOS tube and the eighth NMOS tube are grounded, and the drain electrode of the eighth NMOS tube is connected with the grid electrode; the source electrode of the thirteenth PMOS tube is connected with the source electrode of the fourteenth PMOS tube and is connected with the drain electrode of the twelfth PMOS tube, the grid electrode of the twelfth PMOS tube is connected with the direct current level (vb), and the source electrode of the twelfth PMOS tube is connected with the power supply (VDD);

the fifteenth PMOS tube and the ninth NMOS tube form a push-pull amplifier, drain electrodes of the fifteenth PMOS tube and the ninth NMOS tube are connected with a grid electrode of the fourteenth PMOS tube and used as the output of the buffer circuit, and the grid electrodes of the fifteenth PMOS tube and the ninth NMOS tube are connected with a drain electrode of the thirteenth PMOS tube; the source electrode of the fifteenth PMOS tube is connected with a power supply (VDD), and the source electrode of the ninth NMOS tube is grounded.

6. A method of single photon time of flight measurement using the time-to-analog conversion circuit of any one of claims 1-5, characterized by: the method comprises the following steps:

(1) a reset stage: firstly, resetting the circuit, wherein a reset signal c1 is high level, and charges on a timing capacitor are discharged through an eighth PMOS tube and a third NMOS tube, so that the voltage on the capacitor is 0; then the reset signal is changed into low level, the eighth PMOS tube and the third NMOS tube are cut off, and the reset is finished;

(2) a waiting stage: before the photon signal arrives, the starting signal is at a high level, the photon signal is at a low level, the output signal of the logic unit is at a low level, at the moment, a first NMOS tube in the timing unit is cut off, a current mirror for providing stable charging current does not work, no current exists in a current source, a sixth PMOS tube in the timing unit is cut off, the voltage on a capacitor is 0, and the arrival of a photon pulse is waited;

(3) photon flight time detection stage: when the photon signal pulse arrives, the rising edge of the output signal of the logic unit arrives, the first NMOS tube in the timing unit is conducted, a current source formed by the first NMOS tube, the second NMOS tube, the fourth NMOS tube and the fifth NMOS tube provides stable charging current, the sixth PMOS tube in the timing unit is conducted, the sampling capacitor starts to charge, and the voltage value linearly increases along with the time; in the process of increasing the voltage value, the voltage holding unit prevents the charge on the capacitor from losing;

(4) a voltage reading stage: after exposure is finished, the stop signal is at a high level, the read signal is at a high level, the output signal of the input logic unit is changed into a low level, the sixth PMOS tube is in a cut-off state, the voltage on the capacitor is kept unchanged, the voltage holding unit prevents charge loss on the capacitor, the voltage amplitude is output through the buffer circuit, the time difference from the arrival of photons to the arrival of the stop signal is obtained through the linear relation between the output voltage and time, and time-analog conversion is realized.

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