CN109742031A - 一种薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents
一种薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDFInfo
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Abstract
本发明提供一种薄膜晶体管及其制备方法、阵列基板、显示装置,属于显示技术领域,其可解决现有的导体化处理会导致有源层失去半导体性能或者TFT沟道长度在基板上分布均一性差的问题。本发明的薄膜晶体管的制备方法包括在导体化区域的邻接半导体区域的一侧形成过孔的步骤,该过孔可以防止导体化区域向半导体区域扩散,可以避免有源层的中部被扩散形成导体。
Description
技术领域
本发明属于显示技术领域,具体涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
随着显示器尺寸的不断增大,非晶硅薄膜晶体管出现了电子迁移率不足、均一性较差的问题,为了解决上述问题,使用IGZO、ITZO、IZO等氧化物半导体材料取代非晶硅作为有源层的技术应运而生。
在进行薄膜晶体管(Thin Film Transistor,简称TFT)制备时,为了保证TFT中的源极和漏极(S/D)与IGZO有很好的接触,减小S/D搭接阻抗,提升TFT的性能,需对有源层的边缘用于与源漏极接触的位置进行导体化处理。
发明人发现现有技术中至少存在如下问题:有源层的边缘导体化处理后无法避免导体化扩散问题,导体化扩散会致使有源层的中部被扩散形成导体,失去半导体性能或者造成TFT沟道长度在基板上分布均一性较差。
发明内容
本发明针对现有的导体化处理会导致有源层失去半导体性能或者TFT沟道长度在基板上分布均一性差的问题,提供一种薄膜晶体管及其制备方法、阵列基板、显示装置。
解决本发明技术问题所采用的技术方案是:
一种薄膜晶体管的制备方法,包括在衬底上形成氧化物有源层,以及源极和漏极的步骤,其中,所述氧化物有源层包括相连接的导体化区域和半导体区域,所述源极和漏极与所述导体化区域电连接;
所述方法还包括在导体化区域的邻接半导体区域的一侧形成过孔的步骤。
可选的是,所述形成氧化物有源层具体包括以下步骤:
在衬底上形成氧化物半导体材料且包括过孔的图形,所述氧化物半导体材料的图形包括相连接的导体化区域和半导体区域,所述过孔位于导体化区域的邻接半导体区域的一侧;
对导体化区域的氧化物半导体材料进行导体化处理得到氧化物有源层。
可选的是,所述对导体化区域进行导体化处理包括采用离子轰击的方式,将导体化区域的氧化物半导体材料氢化或去氧化。
可选的是,所述形成氧化物有源层,以及源极和漏极具体包括以下步骤:
在衬底上方形成氧化物有源层;
在完成上述步骤的衬底上形成栅绝缘层;
在完成上述步骤的衬底上形成栅极;
在完成上述步骤的衬底上形成层间绝缘层;
在完成上述步骤的衬底上形成源极和漏极。
可选的是,所述过孔包括侧壁,其中,远离半导体化区域的侧壁为第一侧壁;所述源极和漏极覆盖至少部分第一侧壁。
本发明还提供一种薄膜晶体管,包括衬底,设于所述衬底上方的氧化物有源层,以及源极和漏极,所述氧化物有源层包括相连接的导体化区域和半导体区域,所述源极和漏极与所述导体化区域电连接;其中,所述导体化区域靠近半导体区域的一侧设有过孔。
可选的是,所述导体化区域由与半导体区域相同的氧化物半导体材料氢化或去氧化后构成。
可选的是,所述导体化区域在过孔处形成侧面,其中,远离半导体化区域的侧面为第一侧面;所述源极和漏极覆盖至少部分第一侧面。
可选的是,所述薄膜晶体管为顶栅型。
本发明还提供一种阵列基板,包括上述的薄膜晶体管。
本发明还提供一种显示装置,包括上述的阵列基板。
附图说明
图1为本发明的实施例1的薄膜晶体管的结构示意图;
图2为本发明的实施例2的薄膜晶体管的流程示意图;
图3为本发明的实施例2的薄膜晶体管的有源层形成示意图;
图4为本发明的实施例2的薄膜晶体管的源极和漏极的形成示意图;
图5为本发明的实施例3的薄膜晶体管的一种结构示意图;
图6为本发明的实施例3的薄膜晶体管的另一种结构示意图;
其中,附图标记为:1、衬底;11、保护层;12、缓冲层;2、氧化物有源层;21、导体化区域;22、半导体区域;23、过孔;3、源极和漏极;4、栅绝缘层;5、栅极;6、层间绝缘层;7、光刻胶。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1:
本实施例提供一种薄膜晶体管的制备方法,如图1所示,包括在衬底1上形成氧化物有源层2,以及源极和漏极的步骤,其中,所述氧化物有源层2包括相连接的导体化区域21和半导体区域
22,所述源极和漏极与所述导体化区域21电连接;所述方法还包括在导体化区域21的邻接半导体区域22的一侧形成过孔23的步骤。
本实施例的薄膜晶体管的制备方法包括在导体化区域21的邻接半导体区域22的一侧形成过孔23的步骤,该过孔23可以防止导体化区域21向半导体区域22扩散,可以避免有源层的中部被扩散形成导体。
实施例2:
本实施例提供一种薄膜晶体管的制备方法,如图2-4所示,包括以下制备步骤:
可选的,S01、在衬底1上形成图案化的保护层11,以及覆盖保护层11的缓冲层12;其中,衬底1可以采用玻璃等透明材料制成、且经过预先清洗。缓冲层12可以是单层结构或多个子层的叠层结构,缓冲层12可以采用硅氧化物或硅氮化物形成。具体的,可以采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式形成缓冲层12。
S02、在完成上述步骤的衬底1上形成氧化物有源层2;其中,所述氧化物有源层2包括相连接的导体化区域21和半导体区域22;具体的,S02包括:
S02a、采用一步构图工艺,在完成上述步骤的衬底1上形成氧化物半导体材料且包括过孔23的图形,所述氧化物半导体材料的图形包括相连接的导体化区域21和半导体区域22,所述过孔23位于导体化区域21的邻接半导体区域22的一侧;具体的,如图3所示,可以在氧化物半导体材料上形成一层光刻胶7,对光刻胶7进行曝光和显影,然后进行干法刻蚀,以形成包括有源层和过孔23的图形。
S02b、对导体化区域21的氧化物半导体材料进行导体化处理得到氧化物有源层2。
作为本实施例的一种可选方案,所述对导体化区域21进行导体化处理包括采用离子轰击的方式,将导体化区域21的氧化物半导体材料氢化或去氧化。
本实施例中先形成过孔23后进行导体化,可以更大程度的避免导体化过程中氢原子的扩散,其中,过孔23可以与有源层一步掩膜形成。
作为本实施例的一种优选方案,所述过孔23包括侧壁,其中,远离半导体化区域21的侧壁为第一侧壁;所述源极和漏极3覆盖至少部分第一侧壁。
这样相当于增加了源漏极与导体化区域21的过孔23侧面的搭接接触面积,更利于电子传输。
S03、在完成上述步骤的衬底1上形成栅绝缘层4;具体的,可以采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式在有源层的上方形成栅绝缘层4。
S04、在完成上述步骤的衬底1上形成栅极5;栅极5可以采用钼、钼铌合金、铝、铝钕合金、钛或铜中的至少一种材料形成。具体的,可以采用溅射方式、热蒸发方式、等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式形成栅金属电极膜。
S05、在完成上述步骤的衬底1上形成层间绝缘层6;其中,层间绝缘层6可以采用硅氧化物、硅氮化物、铪氧化物或铝氧化物形成。
S06、在完成上述步骤的衬底1上形成源极和漏极3,所述源极和漏极3与所述导体化区域21电连接。其中,源极、漏极采用钼、钼铌合金、铝、铝钕合金、钛或铜中的至少一种材料形成。如图4所示,可以在上述导电材料层上形成一层光刻胶7,对光刻胶7进行曝光和显影,然后进行刻蚀,以形成包括源极和漏极3的图形。
本实施例的薄膜晶体管的制备方法包括在导体化前,在导体区域邻接半导体区域22的一侧形成过孔23,该过孔23可以防止导体化区域21向半导体区域22扩散,有效可以避免有源层的中部被扩散形成导体。在后续进行SD搭接时,源极和漏极3覆盖过孔23的至少部分第一侧壁,这样相当于增加了接触面积,可以有效降低搭接阻抗,提升导电性能。该方法制备的TFT均一性较好。
在本实施例对应的附图中,显示了各结构层的大小、厚度等仅为示意。在工艺实现中,各结构层在衬底1上的投影面积可以相同,也可以不同,可以通过刻蚀工艺实现所需的各结构层投影面积;同时,附图所示结构也不限定各结构层的几何形状,例如可以是附图所示的矩形,还可以是梯形,或其它刻蚀所形成的形状,同样可通过刻蚀实现。
实施例3:
本实施例提供一种薄膜晶体管,如图5所示,其包括衬底1,设于所述衬底1上方的氧化物有源层2,以及源极和漏极3,所述氧化物有源层2包括相连接的导体化区域21和半导体区域22,所述源极和漏极3与所述导体化区域21电连接;其中,所述导体化区域21靠近半导体区域22的一侧设有过孔23。
本实施例中的薄膜晶体管在导体化区域21的邻接半导体区域22的一侧设置了过孔23,该过孔23可以防止导体化区域21向半导体区域22扩散,可以避免有源层的中部被扩散形成导体。
作为本实施例的一种可选方案,所述导体化区域21由与半导体区域22相同的氧化物半导体材料氢化或去氧化后构成。
本实施例中提供了氢化或去氧化的导体化方式,采用其它导体化方法同样可以设置类似的过孔23。需要说明的是,先形成过孔23后进行导体化,可以更大程度的避免导体化过程中氢原子的扩散,其中,过孔23还可以与有源层一步掩膜形成。
在一个实施例中,所述薄膜晶体管为顶栅型。氧化物有源层2上方设有栅绝缘层4,栅绝缘层4上方设有栅极5,栅极5上方设有层间绝缘层6。
本实施例中以顶栅型薄膜晶体管为例进行了具体说明,其它底栅型薄膜晶体管,也可以采用类似的方案,在此不再赘述。
在一个实施例中,如图6所示,所述导体化区域21在过孔23处形成侧面,其中,远离半导体化区域21的侧面为第一侧面;所述源极和漏极3覆盖至少部分第一侧面。
也就是说,图6所示的方案中,相当于增加了源漏极与导体化区域21的过孔23侧面的搭接接触面积,更利于电子传输。
实施例4:
本实施例提供一种阵列基板,包括上述的薄膜晶体管。
实施例5:
本实施例提供了一种显示装置,其包括上述任意一种阵列基板。所述显示装置可以为:液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (11)
1.一种薄膜晶体管的制备方法,其特征在于,包括在衬底上形成氧化物有源层,以及源极和漏极的步骤,其中,所述氧化物有源层包括相连接的导体化区域和半导体区域,所述源极和漏极与所述导体化区域电连接;
所述方法还包括在导体化区域的邻接半导体区域的一侧形成过孔的步骤。
2.根据权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述形成氧化物有源层具体包括以下步骤:
在衬底上形成氧化物半导体材料且包括过孔的图形,所述氧化物半导体材料的图形包括相连接的导体化区域和半导体区域,所述过孔位于导体化区域的邻接半导体区域的一侧;
对导体化区域的氧化物半导体材料进行导体化处理得到氧化物有源层。
3.根据权利要求2所述的薄膜晶体管的制备方法,其特征在于,所述对导体化区域进行导体化处理包括采用离子轰击的方式,将导体化区域的氧化物半导体材料氢化或去氧化。
4.根据权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述形成氧化物有源层,以及源极和漏极具体包括以下步骤:
在衬底上方形成氧化物有源层;
在完成上述步骤的衬底上形成栅绝缘层;
在完成上述步骤的衬底上形成栅极;
在完成上述步骤的衬底上形成层间绝缘层;
在完成上述步骤的衬底上形成源极和漏极。
5.根据权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述过孔包括侧壁,其中,远离半导体化区域的侧壁为第一侧壁;所述源极和漏极覆盖至少部分第一侧壁。
6.一种薄膜晶体管,其特征在于,包括衬底,设于所述衬底上方的氧化物有源层,以及源极和漏极,所述氧化物有源层包括相连接的导体化区域和半导体区域,所述源极和漏极与所述导体化区域电连接;其中,所述导体化区域靠近半导体区域的一侧设有过孔。
7.根据权利要求6所述的薄膜晶体管,其特征在于,所述导体化区域由与半导体区域相同的氧化物半导体材料氢化或去氧化后构成。
8.根据权利要求6所述的薄膜晶体管,其特征在于,所述导体化区域在过孔处形成侧面,其中,远离半导体化区域的侧面为第一侧面;所述源极和漏极覆盖至少部分第一侧面。
9.根据权利要求6所述的薄膜晶体管,其特征在于,所述薄膜晶体管为顶栅型。
10.一种阵列基板,其特征在于,包括权利要求6-9任一项所述的薄膜晶体管。
11.一种显示装置,其特征在于,包括权利要求10所述的阵列基板。
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