CN109739699A - A kind of SPI verification method based on UVM verification methodology - Google Patents
A kind of SPI verification method based on UVM verification methodology Download PDFInfo
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Abstract
The present invention relates to a kind of SPI verification method based on UVM verification methodology, it is characterised in that verification platform is constructed using UVM verification methodology and system-level hardware description language, functional verification is implemented to SPI module.The verification platform includes: test case test, dummy excitation generation module vsqr, APB system environments apb_env, APB configuration module apb_master_cfg, APB proxy module apb_master_agt, SPI environment spi_env, SPI configuration module spi_cfg, SPI proxy module spi_agt, SPI register model spi_reg_mdl, format converting module adapter, motivate generation module sequencer, actuating circuit element driver, response collecting module collector, monitoring modular monitor, as a result comparison module scoreboard.The present invention realizes the strong verification platform of stratification height, reusability with UVM verification methodology, a plurality of types of randomization data packets can be generated under constraint condition, realize the traversal of all addresses and instruction, automatic collection report with function coverage, as a result than reciprocity self-checking function, the efficiency of verifying and the reliability of verifying are improved.
Description
Technical field
The present invention relates to the functional verifications of digit chip and verification methodology field, especially a kind of to be based on UVM authentication
The SPI verification method of the science of law is randomized the generation of excitation, the collection of function coverage, response knot by building for verification platform
The functional verification to SPI is completed in the operations such as the self-test of fruit.
Background technique
In recent years, with the continuous improvement of chip integration, the function complexity of chip is also greatly increased, the design of chip
Process is more easier to introduce mistake, and verifying work becomes more arduous.In integrated circuit design, verifying work has accounted for entirely
More than half of design cycle.And the insufficient caused capability error verified, it is that chip throws the not high master of piece success rate for the first time
Want reason.Traditional verification technique cannot meet growing verifying demand again, and verifying becomes in IC design
Bottleneck.
SPI is a kind of serial bus interface of prevalence, and main advantage is high speed, full duplex, easy to use, Yin Qite
Property, nowadays more and more chip interiors are all integrated with spi bus interface, therefore the function accuracy of SPI is most important.In order to
Meet the multifarious requirement of peripheral hardware, spi bus interface has various configurations mode and operating mode, and every kind of configuration mode requires
A large amount of test case is added to ensure correctness, this brings huge challenge to traditional verification method.
High level of authentication methodology introduces system-level hardware verification language SystemVerilog, and SystemVerilog is special
Language of the door for verifying, it becomes building for verification environment more efficiently.But only have hardware verification language not enough,
UVM verification methodology is the advantages of growing up on the basis of hardware verification language, inherit VMM and OVM verification methodology
Set of system level verification method, it has a whole set of and uses the class libraries based on hardware language, all sides provided in this library
Method can make building for verification platform become simpler convenience with the construction of test case.
Summary of the invention
It is an object of the invention to the above-mentioned deficiencies of customer service, provide a kind of SPI verification method based on UVM verification methodology,
The strong APB bus system verification platform of reusability height, a scalability is built, more reliably the various of SPI can be matched
The mode of setting is verified.
In order to solve the above-mentioned technical problem, the verification platform in the verification method uses UVM verification methodology and hardware
Description language SystemVerilog is completed, and the verification environment includes:
One test case TEST is used for example configuration verification platform, establishes testing scheme according to testing requirement, test case name can
It is specified after the UVM_TESTNAME of makefile, factory mechanism can be dissolved according to specified test case name, automatic example
Corresponding test case example；
A series of a series of virtual test use-case vseq, the scheduling executed for completing test case seq, pass through `uvm_do_on
() controls corresponding task phase's by raise_objection and drop_objection to specify sqr for seq
Beginning and end；One dummy excitation generation module vsqr, the starting for completing virtual test use-case vseq are run, and receive vseq
The randomization data packet sent, and by data packet dispatching to specified excitation generation module sqr；
One APB system environments apb_env can complete module for completing the instantiation of each component in APB system according to demand
Addition, connection, the distribution in module's address space；
One APB configuration module apb_master_cfg matches for top-down completion interface signal, address space, module I D
It sets；
One APB bus agent module apb_master_agt, for complete APB system incentive drive module, response collecting module,
The instantiation of monitoring modular, establishes the TLM communication mechanism between each module, and the initiator and recipient of communication pass through respectively
The port blocking_port is connected with the port blocking_imp, according to the value of UVM_IS_ACTIVE to determine whether example
monitor；
One SPI system environments spi_env, for completing in SPI system, including the statement example of spi_cfg, spi_agt, and lead to
It crosses uvm_config_db::set () function and system configuration spi_cfg is carried out to layer-by-layer configuration；
One SPI configuration module spi_cfg completes the configuration of SPI system according to the mirror value in SPI register model；
One SPI proxy module spi_agt completes driver in SPI system, collector, monitor, the integrated envelope for motivating generator
Dress；
One SPI register model spi_reg_mdl provides the SPI access interface of DUT register, spi_reg_ for verification platform
Mdl is inherited and uvm_reg_block, is the set of all registers in SPI, specifies a default_ in spi_reg_mdl
Map configures come base address, the access mode etc. to register, and all registers of definition are required to call the side add_reg
Method is added in default_map.It include 4 register models, respectively transmission register in spi_reg_mdl
Spdr_reg, status register spscr_reg divide register spdiv_reg, and slave piece selects register spss_reg, each
The information such as its mode of operation, bit wide, default value are configured with configure in register, and according to test request, are added
Function coverage is entered, by the way that sample () function is added in each register, each register has been enabled automatically to collect function
It can coverage rate；
One format converting module adapter, since the type of the data packet generated by register model is uvm_reg_bus_
Op type, the type for needing to be converted to the support of APB bus could use, and inside modules are mainly made of two functions, reg2bus
() and bus2reg ().Reg2bus () is mainly carried out in the write operation of front door by register model, completes register model
Conversion of the data type to APB bus data type；Bus2reg is mainly carried out in the read operation of front door by register model,
Complete conversion of the APB bus data type to register data type；
One excitation generation module sequencer, sequencer is mainly used for starting in its main_phase corresponding
Sequence is generated, and the sequence for defaulting starting is arranged at test layers by uvm_config_db::set (), and will
Starting_phase passes to sequence, makes it possible to call the function of phase in the sequence of object type
Raise_objection and drop_objection, the starting for controlling entire verification platform stop；
One actuating circuit element driver, according to the timing requirements of bus, by the data in randomization data packet transaction
Actual pumping signal is converted to drive to interface, phase is added jumps mechanism, when so that reset signal is effective,
Driver can automatically jump to the reset_phase stage, carry out the driving of reset signal；
One response collecting module collector, requires according to bus timing, and actual response signal is sampled and is packaged into
New data packet；
One monitoring modular monitor, in each system env, number that driver and collector can will drive and be collected into
It is transmitted to monitor according to packet, the comparison of the two data is carried out in monitor, the correctness for guaranteeing bus data driving and collecting,
It joined functional coverage group, the statistics of function coverage carried out to the data packet being collected into；
One result comparison module scoreboard completes data packet and SPI system reception/transmission that APB system sends/receives
Data packet Determination, as a result report.
The present invention verifies language using UVM verification methodology and SystemVerilog, builds reusable APB verifying system
System, and it is based on this, building for structuring SPI verification platform is completed, using randomization test, the side of function coverage guiding
Formula implements the functional verification of result self-test to SPI module.
Detailed description of the invention
Fig. 1 is the system block diagram of SPI verification platform.
Fig. 2 is the tree hierarchy figure of SPI verification platform.
Fig. 3 is the execution flow chart of phase in UVM.
Fig. 4 is the structure chart of SPI module.
Fig. 5 is the operational flowchart of SPI module.
Specific embodiment
The framework of verification platform of the present invention is as shown in Figure 1, entire verification platform mainly includes following sections: APB bus
System apb_env, spi bus system spi_env, SPI register model spi_reg_mdl, scoring board scoreboard, APB
With in SPI system include a configuration component and an Agent components, Agent components are by excitation generator, driver, collection
Device, monitor composition, the above are the primary clusterings of verification platform to be also added at TEST layers in addition to example said modules
sequence。
Sequence in test case is adjusted in virtual sequence by `uvm_do_on () task
Degree, and each sequence data packet generated is sent to specified sequencer by vsqr.According to each test requirement,
Different virtual sequence is constructed, and is added in vseq_lib, the raise_objection of main_phase
It is executed in the pre_body () of vseq and post_body () respectively with drop_objection；Vseq_lib building is completed
Later, it needs to set vsqr's for vseq_lib by uvm_config_db::set () function in test case
default_sequence.The authentication policy that the verifying uses for, to SPI items configure, be all made of a large amount of randomization datas
Read-write operation, by read and write data match condition and function coverage, guarantee verifying completeness.
In TOP layers interface apb_interface and spi_interface can be stated, example SPI DUT and
TEST is established the connection of SPI DUT and TEST verification environment by interface, and passes through uvm_config_db::set ()
Interface is passed to the component driver and collector of actual access bus in verification environment, interface by function
In joined assertion mechanism to be monitored in real time to signal in bus.
Entire verification platform is started by run_test () function in TOP module, and the test case of instantiation exists
It is indicated after UVM_TESTNAME in makefile, verification platform can be by factory mechanism, according to specified test case name
Such is instantiated, later according to phase mechanism in UVM, program defined in each phase is successively executed, executes process
As shown in Figure 3, wherein all components that build_phase can from top to down in example verification platform；Connect_phase is extremely
Lower and upper execution, establishes the communication connection between all components；Verification platform is completed in start_of_simulation_phase
The definition of configuration information before running, and configured downwards to pushing up, so far complete the building and configuration of verification platform all components.
The behavior of each module mainly executes in time-consuming task phase in verification platform.
In reset_phase, apb system driver and spi system driver can be carried out respective bus interface
The value of each field of register model can be resetted all default values in TEST by the driving of reset signal.Reset_phase executes knot
Shu Hou, entire verification platform, which resets, to be completed, and is prepared to enter into the operation phase.
The operation of verification platform operation phase each component is mainly defined in main_phase () task and is realized, each component
Main_phase is parallel to execute to lower and upper starting.The main implementation procedure of affairs is as follows:
Vsqr according to the vseq in the random starting vseq_lib of configuration, execute pre_body () in vseq, body (),
Post_body () task carries out in body () task according to the operating process of Fig. 5, and starting APB system register first is matched
Sequence is set, which configures the register of SPI DUT by the front door access mode of register, then exists
The read-write sequence of parallel starting APB system and SPI system in fork join carries out the read-write behaviour of a large amount of randomization datas
Make.The data packet of generation can be passed to the specified sequencer of each sequence by vsqr, then be passed to pair by sequencer
The driver answered.
After Driver receives packet by get_next_item, the information in data packet is extracted, is wanted according to agreement timing
It asks, it will be on data Qu Dongdao interface.Apb driver can monitor always the reset signal on apb interface, and one
Denier reset signal is effective, and entire verification platform will be allowed to jump to reset state by jump, executes reset operation.It is executing
After complete operation of giving out a contract for a project, driver can call put task that data packet is passed to monitor.
Collector can monitor always bus signals, according to protocol requirement, real-time sampling bus signals, and be packaged into pair
The transaction answered passes to monitor.
Monitor mainly collects the data packet of driving and sampling, and detection is compared to it, it is ensured that the transmission of data and adopts
Sample is errorless, and carries out the collection of function coverage.It joined event, packet touching received in the put task of corresponding collector
Event is sent out, waits event to be triggered in the put task of corresponding driver, to guarantee the data packet of driving and the data of sampling
The synchronization of packet.
Monitor in Apb_env and spi_env can be passed to the sampled data bag being collected by put () task
2 queues are maintained in scoreboard, scoreboard, for collecting the data packet from apb_env and spi_env.?
In compare () task, according to the Configuration Values of the register sampled, to the number in the data and spi_env in apb_env
According to being compared, reports comparison result, realize the self-checking function of verification platform.
Claims (5)
1. a kind of SPI verification method based on UVM verification methodology, it is characterised in that using UVM verification methodology and
SystemVerilog builds SPI verification platform, implements functional verification to SPI module, the verification platform includes: that a test is used
Example TEST, is used for example configuration verification platform, establishes testing scheme according to testing requirement；One dummy excitation generation module vsqr,
Starting vseq and the scheduling for completing the data packet that it is generated；
One APB system environments apb_env completes the integration packaging of each component in APB system；
One APB configuration module apb_master_cfg completes the addition of APB system module, the distribution of modules address；
One APB proxy module apb_master_agt completes driver in APB system, collector, monitor, excitation generator
Integration packaging；
One SPI system environments spi_env completes the integration packaging of SPI system；
One SPI configuration module spi_cfg completes the configuration of SPI system according to the mirror value in SPI register model；
One SPI proxy module spi_agt completes driver in SPI system, collector, monitor, the integrated envelope for motivating generator
Dress；
One SPI register model spi_reg_mdl provides the SPI access interface of DUT register for verification platform；One format turns
Block adapter is changed the mold, completes to access data packet caused by SPI register model and APB system institute by front door access mode
Need the conversion of data packet format；
One excitation generation module sequencer, complete randomization data contract for fixed output quotas it is raw with arbitration of shaking hands that is sending；
One actuating circuit element driver, according to the timing requirements of bus, by the data in randomization data packet transaction
Actual pumping signal is converted to drive to interface；
One response collecting module collector, requires according to bus timing, and actual response signal is sampled and is packaged into
New data packet；
One monitoring modular monitor is completed to collect the information of received data packet, be handled, analysis, the receipts of function coverage
Collection, as a result report etc.；
One result comparison module scoreboard completes data packet and SPI system reception/transmission that APB system sends/receives
Data packet Determination, as a result report.
2. a kind of SPI verification method based on UVM verification methodology according to claim 1, it is characterised in that: the interface
It is divided into APB interface apb_interface and SPI interface spi_interface, joined assertion mechanism in interface, uses
In being checked in real time interface signal.
3. a kind of SPI verification method based on UVM verification methodology according to claim 1, it is characterised in that: the APB
Configuration module and SPI configuration module implement top-down configuration in respective system top level, all modules in system
The logical which of configuration carries out, and configuration parameter is set in makefile file.
4. a kind of SPI verification method based on UVM verification methodology according to claim 1, it is characterised in that: the SPI
Joined function coverage in register model, the model can automatically to the data sent by front door mode of operation into
The collection of row function coverage.
5. a kind of SPI verification method based on UVM verification methodology according to claim 1, it is characterised in that: the driving
Module driver jumps mechanism using phase in UVM, can be automatically stopped current transmission when the reset signal of bus is effective,
And jump to reset state.
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| CN110532220A (en) * | 2019-08-02 | 2019-12-03 | 广州粒子微电子有限公司 | AES based on UVM verification methodology verifies device |
| CN110888767A (en) * | 2019-12-19 | 2020-03-17 | 山东方寸微电子科技有限公司 | Interface multiplexing module verification platform architecture and quick expansion implementation method |
| CN110908846A (en) * | 2019-11-21 | 2020-03-24 | 江苏旭微科技有限公司 | SPI bus verification method |
| CN111026590A (en) * | 2019-11-08 | 2020-04-17 | 广东高云半导体科技股份有限公司 | Data verification method and platform of interface circuit |
| CN111858217A (en) * | 2020-07-24 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | Hierarchical verification method, platform, equipment and storage medium |
| CN111913840A (en) * | 2020-04-30 | 2020-11-10 | 电子科技大学 | Verification method of APB-UART module based on UVM |
| CN112084802A (en) * | 2020-08-12 | 2020-12-15 | 广州芯世物科技有限公司 | RFID tag chip verification system |
| CN112181739A (en) * | 2020-09-03 | 2021-01-05 | 博流智能科技（南京）有限公司 | System bus test system and method |
| CN112486835A (en) * | 2020-12-11 | 2021-03-12 | 南京艾科朗克信息科技有限公司 | Verification platform and method applied to securities future counter |
| CN112527723A (en) * | 2020-12-16 | 2021-03-19 | 广州昂瑞微电子技术有限公司 | UVM-based SPI verification platform and verification method |
| CN112559273A (en) * | 2020-12-28 | 2021-03-26 | 杭州德旺信息技术有限公司 | QSPI verification system and method based on UVM |
| CN112579381A (en) * | 2020-12-28 | 2021-03-30 | 杭州德旺信息技术有限公司 | UVM-based UART bus UVM verification system and method |
| CN113609037A (en) * | 2021-06-30 | 2021-11-05 | 山东云海国创云计算装备产业创新中心有限公司 | GPIO module verification method, device and equipment based on UVM and readable medium |
| CN114218880A (en) * | 2022-02-23 | 2022-03-22 | 飞腾信息技术有限公司 | Universal verification methodology environment construction method, chip verification method and verification system |
| CN114465934A (en) * | 2022-02-10 | 2022-05-10 | 芯河半导体科技(无锡)有限公司 | Multi-rate flexible configurable Ethernet interface verification method |
| CN116432569A (en) * | 2023-06-13 | 2023-07-14 | 珠海星云智联科技有限公司 | Automatic configuration generation method of UVM verification platform and related equipment |
| CN116775394A (en) * | 2023-08-18 | 2023-09-19 | 腾讯科技（深圳）有限公司 | Chip verification method, device, apparatus, storage medium and computer program product |
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| CN110532220A (en) * | 2019-08-02 | 2019-12-03 | 广州粒子微电子有限公司 | AES based on UVM verification methodology verifies device |
| CN111026590A (en) * | 2019-11-08 | 2020-04-17 | 广东高云半导体科技股份有限公司 | Data verification method and platform of interface circuit |
| CN111026590B (en) * | 2019-11-08 | 2020-09-25 | 广东高云半导体科技股份有限公司 | Data verification method and platform of interface circuit |
| CN110908846A (en) * | 2019-11-21 | 2020-03-24 | 江苏旭微科技有限公司 | SPI bus verification method |
| CN110888767A (en) * | 2019-12-19 | 2020-03-17 | 山东方寸微电子科技有限公司 | Interface multiplexing module verification platform architecture and quick expansion implementation method |
| CN110888767B (en) * | 2019-12-19 | 2023-07-28 | 山东方寸微电子科技有限公司 | Interface multiplexing module verification platform architecture and quick expansion implementation method |
| CN111913840A (en) * | 2020-04-30 | 2020-11-10 | 电子科技大学 | Verification method of APB-UART module based on UVM |
| CN111858217B (en) * | 2020-07-24 | 2022-07-15 | 浪潮(北京)电子信息产业有限公司 | Hierarchical verification method, platform, equipment and storage medium |
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| CN112559273A (en) * | 2020-12-28 | 2021-03-26 | 杭州德旺信息技术有限公司 | QSPI verification system and method based on UVM |
| CN113609037A (en) * | 2021-06-30 | 2021-11-05 | 山东云海国创云计算装备产业创新中心有限公司 | GPIO module verification method, device and equipment based on UVM and readable medium |
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| CN114218880B (en) * | 2022-02-23 | 2022-05-03 | 飞腾信息技术有限公司 | Universal verification methodology environment construction method, chip verification method and verification system |
| CN114218880A (en) * | 2022-02-23 | 2022-03-22 | 飞腾信息技术有限公司 | Universal verification methodology environment construction method, chip verification method and verification system |
| CN116432569A (en) * | 2023-06-13 | 2023-07-14 | 珠海星云智联科技有限公司 | Automatic configuration generation method of UVM verification platform and related equipment |
| CN116432569B (en) * | 2023-06-13 | 2023-10-20 | 珠海星云智联科技有限公司 | Automatic configuration generation method of UVM verification platform and related equipment |
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| CN116775394B (en) * | 2023-08-18 | 2024-04-26 | 腾讯科技（深圳）有限公司 | Chip verification method, device, apparatus, storage medium and computer program product |
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Application publication date: 20190510 |