CN109728570B - Circuit for suppressing surge current - Google Patents
Circuit for suppressing surge current Download PDFInfo
- Publication number
- CN109728570B CN109728570B CN201711025371.5A CN201711025371A CN109728570B CN 109728570 B CN109728570 B CN 109728570B CN 201711025371 A CN201711025371 A CN 201711025371A CN 109728570 B CN109728570 B CN 109728570B
- Authority
- CN
- China
- Prior art keywords
- coupled
- terminal
- voltage
- capacitor
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Electronic Switches (AREA)
- Direct Current Feeding And Distribution (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
The invention discloses a circuit for suppressing surge current, which comprises a switch unit, a feedback control unit, a voltage coupling unit and a reference signal generating unit. The first terminal of the switch unit is used for being coupled to a voltage source. A second terminal of the switch unit is coupled to a first capacitor. The output end of the feedback control unit is coupled to the third end of the switch unit. The input port of the voltage coupling unit is coupled to the second end of the switch unit. The output port of the voltage coupling unit is coupled to the feedback signal input end of the feedback control unit. The reference signal generating unit is coupled to the reference signal input end of the feedback control unit.
Description
Technical Field
The invention relates to a circuit for suppressing surge current.
Background
Generally, for most electronic devices, the internal circuitry is powered by direct current. For the stability of dc power supply, the circuit needs to include an energy storage element, and the most common energy storage element is a capacitor. During the power-on (or power-on), the initial voltage of the capacitor is zero and is approximately short-circuited, so that a large transient current, i.e. an Inrush current (Inrush current), is generated. The surge current may cause noise, even malfunction of internal circuits of the electronic equipment or failure of internal parts.
In the prior art, the gate-source voltage (Vgs) rising slope of the electronic load switch is controlled to reduce the speed at which the switch impedance is greatly converted to near zero, thereby achieving the purpose of reducing the surge current. However, due to the characteristics of semiconductor electronic switches, the switch impedance does not drop linearly during the gate-source voltage rise. The waveform diagram obtained by actually measuring the prior art circuit is shown in fig. 8, wherein an arrow 1 on the left vertical axis indicates the gate-source voltage waveform of the electronic switch, an arrow 2 indicates the voltage waveform of the capacitor on the load side, and an arrow 4 indicates the current waveform of the capacitor on the load side. The abscissa is time, and a large scale is 20 ms. For the gate-source voltage waveform of the electronic switch, the ordinate axis is voltage, and a large grid scale is 2.5V. For the voltage waveform of the capacitor at the load side, the ordinate axis is voltage, and a large scale is 2V. For the current waveform of the capacitor at the load side, the ordinate axis is the current, and a large scale is 10A.
As can be seen, the impedance is almost maintained at a maximum value when the initial gate-source voltage has not reached the Threshold (Threshold), so that no current is flowing to charge the load-side capacitor during this time. When the gate-source voltage reaches the threshold, the gate-source voltage rises slightly (several millivolts to several hundred millivolts), the impedance drops sharply, which is the time for charging the main load capacitor, the surge current occurs at this time, and the capacitor is usually charged up in this time interval. The gate-source voltage exceeds the threshold value, at which time the electronic switch impedance continues to drop to nearly zero. That is, the charging time of the capacitor in the prior art is short, so that the surge current (the peak value of the surge current is up to 48.2A) cannot be effectively suppressed.
In order to prolong the time for charging the capacitor, the starting speed of the whole circuit is generally reduced. And the threshold voltage of the electronic switch has an error value, thereby increasing the difficulty of the circuit optimization design.
Therefore, how to provide a circuit for suppressing the surge current is an important issue.
Disclosure of Invention
The embodiment of the invention discloses a circuit for inhibiting surge current, which comprises a switch unit, a feedback control unit, a voltage coupling unit and a reference signal generating unit. The switch unit has a first end, a second end and a third end. The first terminal of the switch unit is used for being coupled to a voltage source. A second terminal of the switch unit is coupled to a first capacitor. The feedback control unit has a feedback signal input terminal, a reference signal input terminal and an output terminal. The output end of the feedback control unit is coupled to the third end of the switch unit. The voltage coupling unit has an input port and an output port. The input port of the voltage coupling unit is coupled to the second end of the switch unit. The output port of the voltage coupling unit is coupled to the feedback signal input end of the feedback control unit. The reference signal generating unit is coupled to the reference signal input end of the feedback control unit.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
Fig. 1 is a block diagram of a circuit for suppressing an inrush current according to a first embodiment of the invention.
Fig. 2 is a block diagram of a circuit for suppressing inrush current according to a second embodiment of the present invention.
Fig. 3 is a block diagram of a circuit for suppressing inrush current according to a third embodiment of the present invention.
FIG. 4 is a block diagram of a circuit for suppressing inrush current according to a fourth embodiment of the present invention.
Fig. 5 is a block diagram of a circuit for suppressing inrush current according to a fifth embodiment of the present invention.
Fig. 6 is a block diagram of a circuit for suppressing inrush current according to a sixth embodiment of the invention.
FIG. 7 is a waveform diagram illustrating the measurement of a circuit for suppressing inrush current according to a third embodiment of the present invention.
FIG. 8 is a waveform diagram illustrating measurement performed by a circuit according to the prior art.
Wherein the reference numerals
1a to 1 f: circuit arrangement
12: switch unit
14: feedback control unit
16: voltage coupling unit
18: reference signal generating unit
Vs: voltage source
C1: first capacitor
C2: second capacitor
Q1 n: n-type metal oxide semiconductor field effect transistor
Q1 p: p-type metal oxide semiconductor field effect transistor
Q2: PNP type bipolar transistor
Q3: NPN type bipolar transistor
D1: diode with a high-voltage source
R1: a first resistor
R2: second resistance
R3: third resistance
R4: fourth resistor
R5: fifth resistor
R6: sixth resistor
R7: seventh resistor
Rs 1: first voltage dividing resistor
Rs 2: second voltage dividing resistor
Rs 3: third voltage dividing resistor
Rs 4: fourth voltage dividing resistor
VDD: driving voltage source
Voffset: compensation voltage source
Is: current source
OP: operational amplifier
20: switch protection unit
And Rp: protective resistor
ZD 1: first Zener diode
ZD 2: second Zener diode
Detailed Description
The following detailed description of the embodiments of the present invention with reference to the drawings and specific examples is provided for further understanding the objects, aspects and effects of the present invention, but not for limiting the scope of the appended claims.
Referring to fig. 1, fig. 1 is a block diagram illustrating a circuit for suppressing an inrush current according to a first embodiment of the invention. The circuit 1a includes a switch unit 12, a feedback control unit 14, a voltage coupling unit 16 and a reference signal generating unit 18.
The switch unit 12 has a first terminal, a second terminal and a third terminal. The first terminal of the switch unit 12 is coupled to a voltage source Vs. The second terminal of the switch unit 12 is coupled to the first capacitor C1.
The feedback control unit 14 has a feedback signal input terminal, a reference signal input terminal and an output terminal. The output terminal of the feedback control unit 14 is coupled to the third terminal of the switch unit 12 to control the switch unit 12 to be turned on or off.
The voltage coupling unit 16 has an input port and an output port. The input port of the voltage coupling unit 16 is coupled to the second terminal of the switch unit 12 to obtain the feedback signal. An output port of the voltage coupling unit 16 is coupled to a feedback signal input terminal of the feedback control unit 14 to provide the feedback signal to the feedback control unit 14.
The reference signal generating unit 18 is coupled to a reference signal input terminal of the feedback control unit 14 to provide the generated reference signal to the feedback control unit 14.
In some embodiments, the voltage source Vs is, for example, an external power supply, and the circuit 1a is, for example, disposed in an electronic device for protecting the electronic device connected to the external power supply. When the external power supply is turned on, the circuit 1a starts to operate to limit the peak value of the surge current, thereby preventing the internal parts of the electronic device from being damaged.
In other embodiments, the circuit 1a is disposed in a power supply, for example, and is used to protect an electronic device coupled to the power supply. Similarly, when the power supply is turned on, the circuit 1a will start to operate to limit the peak value of the surge current, thereby preventing the internal components of the electronic device from being damaged.
The operation principle of the circuit 1a is to couple the voltage (terminal voltage) of the first capacitor C1 as a feedback signal to the feedback control unit 14 through the voltage coupling unit 16. The feedback control unit 14 outputs a control signal to control the switch unit 12 to be turned on or off according to the feedback signal and the reference signal. By controlling the switching unit 12 to be turned on or off, the rising slope of the voltage of the first capacitor C1 is controlled, so as to achieve the effect of suppressing the surge current.
Referring to fig. 2, fig. 2 is a block diagram of a circuit for suppressing an inrush current according to a second embodiment of the invention. The circuit 1b is similar to the circuit 1a, except that the input port of the voltage coupling unit 16 is further coupled to the first terminal of the switch unit 12. In this embodiment, the voltage coupling unit 16 couples the voltage across the first terminal and the second terminal of the switch unit 12 (i.e. the voltage difference) as the feedback signal to the feedback control unit 14. However, the basic operation principle of the circuit 1b is similar to that of the circuit 1a, and both the circuit 1b and the circuit 1a control the rising slope of the voltage of the first capacitor C1 by obtaining the feedback signal to control the switch unit 12. Several embodiments are described in order to further illustrate the principles and details of the invention.
Referring to fig. 3, fig. 3 is a block diagram of a circuit for suppressing an inrush current according to a third embodiment of the invention. The circuit 1C is similar to the circuit 1a, and uses the voltage of the first capacitor C1 as the feedback signal.
The switch unit 12 includes an NMOS transistor Q1N and a diode D1. A drain (drain) of the NMOS transistor Q1N is used as a first terminal of the switch unit 12 for coupling to a voltage source Vs. A source of the NMOS Q1N is used as a second terminal of the switch unit 12 for coupling to the first capacitor C1. A gate (gate) of the nmos transistor Q1N is coupled to the feedback control unit 14 as a third terminal of the switch unit 12. The diode D1 is coupled between the drain and the source of the NMOS Q1N to prevent the NMOS Q1N from being damaged.
The reference signal generating unit 18 includes a second capacitor C2 and a first resistor R1. A first terminal of the second capacitor C2 is grounded, and a second terminal of the second capacitor C2 is coupled to the reference signal input terminal of the feedback control unit 14. A first terminal of the first resistor R1 is coupled to a driving voltage source VDD, and a second terminal of the first resistor R1 is coupled to the second terminal of the second capacitor C2. In the present embodiment, the reference signal generating unit 18 charges the second capacitor C2 by the driving voltage source VDD, and outputs the voltage of the second capacitor C2 as the reference signal. In other words, the reference signal is a voltage waveform with a positive slope.
The feedback control unit 14 includes a PNP bipolar transistor Q2, an NPN bipolar transistor Q3, a second resistor R2 and a third resistor R3.
An emitter (emitter) of the PNP bipolar transistor Q2 is coupled to the driving voltage source VDD. A collector (collector) of the PNP bipolar transistor is coupled to the third terminal of the switch unit 12 through the second resistor R2. A base (base) of the PNP bipolar transistor Q2 is coupled to a first terminal of the third resistor R3.
A collector of the NPN bipolar transistor Q3 is coupled to a second terminal of the third resistor R3. An emitter of the NPN bipolar transistor Q3 is coupled to the output port of the voltage coupling unit 16. A base of the NPN bipolar transistor Q3 is coupled to the reference signal generating unit 18.
The voltage coupling unit 16 is a conductive line for directly coupling the voltage of the first capacitor C1 to the feedback signal input terminal of the feedback control unit 14.
The detailed operation principle of this embodiment is as follows.
Without loss of generality, when the voltage source Vs is turned on, the initial voltage of the first capacitor C1 is assumed to be zero. The reference signal generating unit 18 starts to output a voltage waveform having a positive slope, i.e., a reference signal, as the driving voltage source VDD charges the second capacitor C2. When the voltage value of the reference signal increases from zero to up, the NPN bipolar transistor Q3 is turned on first, and the base voltage of the PNP bipolar transistor Q2 drops to turn on the PNP bipolar transistor Q2. The gate voltage of the NMOS transistor Q1N rises and turns on, i.e. the switch unit 12 is turned on. The first capacitor C1 begins to charge, causing the voltage of the first capacitor C1 to increase.
When the voltage rising slope of the first capacitor C1 exceeds the rising slope of the reference signal, the PNP type bipolar transistor Q3 is turned off, and in turn, the NPN type bipolar transistor Q2 is turned off, thereby limiting the gate voltage of the NMOS transistor Q1N. Since the impedance of the NMOS Q1N is affected by the voltage difference between the gate and the source (i.e., the gate-source voltage), when the gate voltage of the NMOS Q1N rises less than the voltage of the first capacitor C1, the impedance of the NMOS Q1N increases, and the voltage rise rate of the first capacitor C1 decreases. When the voltage value of the reference signal exceeds the voltage value of the voltage source Vs, the NPN type bipolar transistor Q3, the PNP type bipolar transistor Q2 and the N type MOSFET Q1N are connected and fully turned on.
Therefore, by feeding back the voltage of the first capacitor C1 to the feedback control unit 14 and comparing it with the voltage waveform of the reference signal generated by the reference signal generating unit 18, the operation of the switching unit 12 can be controlled, and the voltage rising slope of the first capacitor C1 can be controlled, so as to achieve the effect of suppressing the surge current.
Referring to fig. 4, fig. 4 is a block diagram illustrating a circuit for suppressing an inrush current according to a fourth embodiment of the invention. The circuit 1d is similar to the circuit 1c except for the reference signal generating unit 18.
In the fourth embodiment, the reference signal generating unit 18 includes a second capacitor C2 and a current source Is. A first terminal of the second capacitor C2 is grounded, and a second terminal of the second capacitor C2 is coupled to the reference signal input terminal of the feedback control unit 14. The current source Is coupled to the second terminal of the second capacitor C2. In other words, the second capacitor C2 Is charged by the current source Is to generate the reference signal.
Referring to fig. 5, fig. 5 is a block diagram illustrating a circuit for suppressing an inrush current according to a fifth embodiment of the invention. The circuit 1e is similar to the circuit 1b, and uses the voltage across the first terminal and the second terminal of the switch unit 12 as the feedback signal. The fifth embodiment is a further concrete embodiment of the second embodiment, and details thereof are described below.
The reference signal generating unit 18 includes a second capacitor C2 and a first resistor R1. A first terminal of the second capacitor C2 is coupled to a driving voltage source VDD. A second terminal of the second capacitor C2 is coupled to a first terminal of the first resistor R1 and the reference signal input terminal of the feedback control unit 14. A second terminal of the first resistor R1 is connected to ground.
The feedback control unit 14 includes a PNP bipolar transistor Q2 and an NPN bipolar transistor Q3. An emitter of the PNP type bipolar transistor Q2 is coupled to the driving voltage source VDD. A collector of the PNP bipolar transistor Q2 is coupled to the third terminal of the switch unit 12 through a second resistor R2. A base of the PNP bipolar transistor Q2 is coupled to a first terminal of a third resistor R3.
A collector of the NPN bipolar transistor Q3 is coupled to a second terminal of the third resistor R3. An emitter of the NPN bipolar transistor Q3 is coupled to the reference signal generating unit 18 as a reference signal input terminal of the feedback control unit 14. A base of the NPN bipolar transistor Q3 is used as a feedback signal input terminal of the feedback control unit 14 and is coupled to the output port of the voltage coupling unit 16.
The voltage coupling unit 16 includes an operational amplifier OP. A non-inverting input terminal of the operational amplifier OP is coupled to the first terminal of the switch unit 12 through a fourth resistor R4. An inverting input terminal of the operational amplifier OP is coupled to the second terminal of the switch unit 12 through a fifth resistor R5. An output terminal of the operational amplifier OP is coupled to the inverting input terminal of the operational amplifier OP through a sixth resistor R6. The output terminal of the operational amplifier OP is used as the output port of the voltage coupling unit 16 to be coupled to the base of the NPN type bipolar transistor Q3 of the feedback control unit 14. In addition, the non-inverting input terminal of the operational amplifier OP is further coupled to an offset voltage Voffset through a seventh resistor R7.
In the fifth embodiment, the voltage difference between the first terminal and the second terminal of the switch unit 12 is large initially, so that the NPN type bipolar transistor Q3 is turned on, and the PNP type bipolar transistor Q2 and the NMOS transistor Q1N are turned on in parallel. When the voltage of the first capacitor C1 rises, the voltage difference between the first terminal and the second terminal of the switch unit 12 decreases, so that the NPN-type bipolar transistor Q3 and the PNP-type bipolar transistor Q2 are turned off, and the impedance of the nmos-type mosfet Q1N increases, thereby suppressing the voltage rising slope of the first capacitor C1.
Referring to fig. 6, fig. 6 is a block diagram illustrating a circuit for suppressing an inrush current according to a sixth embodiment of the invention. The circuit 1f operates in a similar manner as the above embodiments, but the switch unit 12 is implemented by a P-type metal oxide semiconductor field effect transistor. Therefore, the remaining unit components of the circuit 1f are different from the above embodiments, and the details will be described below.
The switch unit 12 includes a PMOS transistor Q1P and a diode D1. A source of the PMOS transistor Q1P is used as a first terminal of the switch unit 12 for coupling to a voltage source Vs. A drain of the PMOS transistor Q1P is used as a second terminal of the switch unit 12 for coupling to the first capacitor C1. A gate of the PMOS transistor Q1P is coupled to the feedback control unit 14 as a third terminal of the switching unit 12. The diode D1 is coupled between the source and the drain of the PMOS transistor Q1P to prevent the PMOS transistor Q1P from being damaged.
The reference signal generating unit 18 includes a second capacitor C2, a first resistor R1, a first voltage dividing resistor Rs1, and a second voltage dividing resistor Rs 2. A first terminal of the second capacitor C2 is grounded, and a second terminal of the second capacitor C2 is coupled to the reference signal input terminal of the feedback control unit 14. A first terminal of the first resistor R1 is coupled to a first terminal of the first voltage-dividing resistor Rs1 and a first terminal of the second voltage-dividing resistor Rs2, and a second terminal of the first resistor R1 is coupled to the second terminal of the second capacitor C2. A second terminal of the first voltage dividing resistor Rs1 is coupled to the voltage source Vs. A second terminal of the second voltage-dividing resistor Rs2 is grounded. In the present embodiment, the reference signal generating unit 18 divides the voltage source Vs through the first voltage dividing resistor Rs1 and the second voltage dividing resistor Rs2 to charge the second capacitor C2, and outputs the voltage of the second capacitor C2 as the reference signal.
The feedback control unit includes a PNP bipolar transistor Q2 and an NPN bipolar transistor Q3. An emitter of the PNP bipolar transistor Q2 is coupled to the reference signal generating unit 18 as a reference signal input terminal of the feedback control unit 14. A base of PNP bipolar transistor Q2 is used as the feedback signal input terminal of feedback control unit 14 and coupled to the output port of voltage coupling unit 16. A collector of the PNP bipolar transistor Q2 is coupled to a first terminal of a second resistor R2.
An emitter of the NPN bipolar transistor Q3 is grounded. A base of the NPN bipolar transistor Q3 is coupled to a second terminal of the second resistor R2. A collector of the NPN bipolar transistor Q3 is coupled as an output terminal of the feedback control unit 14 to the third terminal of the switching unit 12 through a first zener diode ZD1, and the collector of the NPN bipolar transistor Q3 is coupled to the emitter of the NPN bipolar transistor Q3 through a third resistor R3 and grounded.
The voltage coupling unit 16 includes a third voltage dividing resistor Rs3 and a fourth voltage dividing resistor Rs 4. A first terminal of the third voltage dividing resistor Rs3 is used as the input port of the voltage coupling unit 16 and is coupled to the second terminal of the switch unit 12. A second terminal of the third voltage dividing resistor Rs3 is used as an output port of the voltage coupling unit 16 and is coupled to the feedback signal input terminal of the feedback control unit 14. A first terminal of the fourth voltage dividing resistor Rs4 is coupled to the second terminal of the third voltage dividing resistor Rs 3. A second terminal of the fourth voltage dividing resistor Rs4 is grounded. In other words, in the present embodiment, the voltage coupling unit 16 couples the feedback control unit 14 by dividing the voltage of the first capacitor C1.
In general, the driving voltage of a PMOS transistor is low compared to that of an NMOS transistor. Therefore, the sixth embodiment can make the circuit 1f operate normally without using a high voltage driving voltage source (e.g., the driving voltage source VDD). In other words, in the circuit 1f, the PMOS transistor Q1P can be turned on with a lower driving voltage.
In addition, the circuit 1f further includes a switch protection unit 20 for protecting the switch unit 12. The switch protection unit 20 includes a second zener diode ZD2 and a protection resistor Rp, and the second zener diode ZD2 is coupled between the first terminal and the third terminal of the switch unit 12. The protection resistor Rp is coupled between the first terminal and the third terminal of the switch unit 12.
Referring to fig. 7, fig. 7 is a waveform diagram illustrating a measurement of a circuit for suppressing an inrush current according to a third embodiment of the invention. The left vertical axis indicates the gate-source voltage waveform of the NMOS Q1N of the switch unit 12 by arrow 1, the voltage waveform of the first capacitor C1 by arrow 2, and the current waveform of the first capacitor C1 by arrow 4. The abscissa is time, and a large scale is 10 ms. For the gate-source voltage waveform of the NMOS Q1N of the switch unit 12, the ordinate of the ordinate is the voltage, and a large scale is 2.5V. For the voltage waveform of the first capacitor C1, the ordinate axis is voltage, and a large scale is 2V. For the current waveform of the first capacitor C1, the ordinate axis is current, and a large scale is 5A.
As can be seen from FIG. 7, by the embodiment of the present invention, the gate-source voltage of the NMOS transistor Q1N of the switch unit 12 reaches full conduction for 40ms (the middle plateau accounts for more than 95% of the total switch conduction time). The charging time of the first capacitor C1 is effectively prolonged (i.e. the voltage rising slope of the first capacitor C1 is controlled), and the peak value of the surge current is suppressed to be 13.3A at most.
According to the embodiment of the invention, the circuit for suppressing the surge current can be fed back to the feedback control unit by taking the voltage of the first capacitor or the voltage difference between the first end and the second end of the switch unit as the feedback signal. The feedback control unit controls the switch unit to be turned on and off according to the feedback signal and the reference signal generated by the reference signal generating unit, and adjusts the charging time of the first capacitor, so as to achieve the effect of inhibiting the surge current.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (3)
1. A circuit for suppressing an inrush current, comprising:
the switch unit is provided with a first end, a second end and a third end, wherein the first end of the switch unit is used for being coupled to a voltage source, and the second end of the switch unit is used for being coupled to a first capacitor;
a feedback control unit having a feedback signal input terminal, a reference signal input terminal and an output terminal, the output terminal of the feedback control unit being coupled to the third terminal of the switch unit;
a voltage coupling unit having an input port and an output port, wherein the input port of the voltage coupling unit is coupled to the second terminal of the switch unit, and the output port of the voltage coupling unit is coupled to the feedback signal input terminal of the feedback control unit; and
a reference signal generating unit coupled to the reference signal input terminal of the feedback control unit;
wherein the switch unit comprises an NMOS transistor having a drain, a source and a gate, the drain of the NMOS transistor is coupled to the voltage source, the source of the NMOS transistor is coupled to the first capacitor, and the gate of the NMOS transistor is coupled to the output of the feedback control unit; and
the feedback control unit includes:
a PNP bipolar transistor, wherein an emitter of the PNP bipolar transistor is coupled to a driving voltage source, a collector of the PNP bipolar transistor is coupled to the third terminal of the switch unit through a second resistor, and a base of the PNP bipolar transistor is coupled to a first terminal of a third resistor; and
a collector of the NPN bipolar transistor is coupled to a second end of the third resistor, an emitter of the NPN bipolar transistor is coupled to the output port of the voltage coupling unit, and a base of the NPN bipolar transistor is coupled to the reference signal generating unit.
2. The circuit for suppressing an inrush current as claimed in claim 1, wherein the reference signal generating unit comprises:
a second capacitor, a first end of the second capacitor is grounded, and a second end of the second capacitor is coupled to the reference signal input end of the feedback control unit; and
a first resistor, a first end of which is coupled to the driving voltage source, and a second end of which is coupled to the second end of the second capacitor.
3. The circuit for suppressing an inrush current as claimed in claim 1, wherein the reference signal generating unit comprises:
a second capacitor, a first end of the second capacitor is grounded, and a second end of the second capacitor is coupled to the reference signal input end of the feedback control unit; and
a current source coupled to the second terminal of the second capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711025371.5A CN109728570B (en) | 2017-10-27 | 2017-10-27 | Circuit for suppressing surge current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711025371.5A CN109728570B (en) | 2017-10-27 | 2017-10-27 | Circuit for suppressing surge current |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109728570A CN109728570A (en) | 2019-05-07 |
| CN109728570B true CN109728570B (en) | 2020-06-12 |
Family
ID=66291961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711025371.5A Active CN109728570B (en) | 2017-10-27 | 2017-10-27 | Circuit for suppressing surge current |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109728570B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011109788A (en) * | 2009-11-17 | 2011-06-02 | Cosel Co Ltd | Rush current limiting circuit |
| CN104767378A (en) * | 2014-01-07 | 2015-07-08 | 株式会社东芝 | Power source circuit |
| CN107027334A (en) * | 2015-12-01 | 2017-08-08 | 富士电机株式会社 | Surge current prevents circuit |
-
2017
- 2017-10-27 CN CN201711025371.5A patent/CN109728570B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011109788A (en) * | 2009-11-17 | 2011-06-02 | Cosel Co Ltd | Rush current limiting circuit |
| CN104767378A (en) * | 2014-01-07 | 2015-07-08 | 株式会社东芝 | Power source circuit |
| CN107027334A (en) * | 2015-12-01 | 2017-08-08 | 富士电机株式会社 | Surge current prevents circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109728570A (en) | 2019-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203166467U (en) | Overvoltage protection circuit | |
| US8704578B2 (en) | Protection circuit | |
| CN205453114U (en) | Power supply surge inhibitor with prevent joining conversely function | |
| WO2018006769A1 (en) | Hysteresis power supply circuit | |
| WO2013071758A1 (en) | Power input load power-on slow starter | |
| CN107528298B (en) | Protection circuit of electronic load and electronic load | |
| TWI571031B (en) | Protection device, system and method for maintaining steady output on gate driver terminal | |
| CN113328734A (en) | Fast blocking switch | |
| CN211123821U (en) | Linear voltage stabilizing circuit applied to ammeter and terminal | |
| JP5588370B2 (en) | Output circuit, temperature switch IC, and battery pack | |
| CN203800576U (en) | Protection circuit of overcurrent and under current for MOS transistor output | |
| CN101582628A (en) | High-voltage starting circuit with constant current control | |
| JP2013021883A (en) | Power-supply reverse-connection protection circuit | |
| CN109728570B (en) | Circuit for suppressing surge current | |
| CN110601512A (en) | Discrete high-side driving circuit system | |
| CN107394749B (en) | Protective circuit | |
| CN105515357B (en) | A kind of DCDC current-limiting circuits | |
| TWI568118B (en) | Simple under voltage protection device | |
| CN110798199A (en) | MOS tube driving circuit | |
| CN210578242U (en) | Power supply slow-start circuit | |
| JP2014021634A (en) | Rush current suppression circuit | |
| CN204030941U (en) | A kind of protective circuit and voltage stabilizing circuit | |
| CN214798853U (en) | Capacitive load power-supply-preventing reverse connection driving control circuit | |
| CN215601021U (en) | Overvoltage protection circuit | |
| CN211744034U (en) | Overvoltage protection circuit arrangement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |