CN109728070A - A kind of MOS electrostatic protection trench device and its manufacturing method - Google Patents
A kind of MOS electrostatic protection trench device and its manufacturing method Download PDFInfo
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Abstract
The present invention provides a kind of MOS electrostatic protection trench device and its manufacturing method, and The present invention reduces one layer of photoetching processes, the difference in height of electrostatic protection structure part and substrate are optimized, so as to optimize subsequent photoetching window considerations；Using the selective etch of silicon nitride and silica, to form the slot type structure of electrostatic protection；This method preparation MOS electrostatic preventing structure simple process, difficulty is small, cost is relatively low.
Description
Technical field
The present invention relates to the technical field of semiconductor devices, more particularly to a kind of MOS electrostatic protection trench device and its
Manufacturing method.
Background technique
In manufacturing process and final system application process, integrated circuit is likely to occur static discharge
(Electrostatics Discharge, ESD) phenomenon.ESD event would generally cause the electric discharge of high voltage potential (general thousands of
Volt) and lead to high current (several amperes) pulse of short-term (general 100ns), this will destroy crisp present in the contemporary integrated circuits
Weak device causes the disabler of system.Thus, it is essential for carrying out electrostatic protection for integrated circuit.
MOS device is a kind of important electrostatic protection device, is widely used in integrated circuit.
In the prior art, in MOS electrostatic preventing structure frequently with silicon oxide layer deposited on substrate as barrier layer, then
Using the barrier layer on photoetching, etching removal active region, groove is formed on active region, then carry out polycrystalline and deposit to be formed
MOS electrostatic preventing structure.This method is due to first using silicon oxide layer deposited as barrier layer, and then dry etching removes active area
The silica barrier layer on domain, thus there are overetch phenomenons, so that the electrostatic protection structure thickness of subsequent preparation increases
(currently about 8000 angstroms), thus, the difference in height of substrate and electrostatic preventing structure part increases, and is subsequently formed light to increase
Carve the difficulty of window considerations；The larger, higher cost using this method preparation MOS electrostatic preventing structure complex process, difficulty.Cause
This, provides that a kind of simple process, difficulty be small, lower-cost method preparation MOS electrostatic preventing structure is those skilled in the art
The project for needing to solve.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of MOS electrostatic protection groove devices
Part and its manufacturing method, for solve to prepare in the prior art MOS electrostatic preventing structure complex process, difficulty be larger, cost compared with
High problem.
In order to achieve the above objects and other related objects, the present invention provides a kind of manufacture of MOS electrostatic protection trench device
Method, the manufacturing method the following steps are included:
A substrate is provided, the substrate includes drain region and dielectric layer；The dielectric layer have the first face and with it is described
Corresponding second face in first face；First face of dielectric layer is incorporated into the drain region；The dielectric layer is laterally divided into
Active region and electrostatic protection region；
Several grooves are formed in the dielectric layer of the active region, and form the first polysilicon in the trench
Layer；
It sequentially forms silicon nitride layer and the second polysilicon layer from bottom to top on second face of dielectric layer, and removes and be located at
The silicon nitride layer of the active region and second polysilicon layer；
Electrostatic protection structure is made based on second polysilicon layer for being located at the electrostatic protection region, and institute will be located at
The silicon nitride layer in electrostatic protection region is stated as barrier layer.
Preferably, forming first polysilicon layer in the trench further includes before in the groove and being given an account of
The step of gate dielectric layer is formed on the second face of matter layer.
It preferably, further include giving birth in the groove and on the second face of the dielectric layer before forming the gate dielectric layer
Long sacrificial oxide layer then removes the step of sacrificial oxide layer.
Preferably, the method that removal is located at the silicon nitride layer of the active region includes wet etching.
It preferably, further include the step that body area, source region and body contact zone are formed in the dielectric layer of the active region
Suddenly.
Preferably, the first doped region is formed in second polysilicon layer while forming the body area；In shape
At forming the second doped region while the source region in second polysilicon layer, first doped region and described the
The doping type of two doped regions is opposite.
It preferably, further include in second face of dielectric layer and the electrostatic protection structure upper surface further include from bottom to top
The step of sequentially forming insulating medium layer and metal layer.
The present invention also provides a kind of MOS electrostatic protection trench device, the MOS electrostatic protection trench device includes:
Substrate, the substrate include drain region and dielectric layer；The dielectric layer have the first face and with first face
Corresponding second face；First face of dielectric layer is incorporated into the drain region；The dielectric layer is laterally divided into active area
Domain and electrostatic protection region；
Several grooves include the first polysilicon layer in the groove in the dielectric layer of the active region；
Silicon nitride layer, positioned at second face of the dielectric layer in the electrostatic protection region；
Electrostatic protection structure is located above the silicon nitride layer.
Preferably, also there is epitaxial layer between the first face of the drain region and the dielectric layer.
The dielectric layer of the active region is preferably located at from the dielectric layer first towards the dielectric layer second
Face successively includes drift region, body area and source region, further includes body contact zone in the body area.
Preferably, second face of dielectric layer and the electrostatic protection structure upper surface further include insulating medium layer and metal
Layer, the metal layer are divided into mutually independent source body contact metal layer and gate contact metal layer.
Preferably, the source body contact metal layer and gate contact metal layer by contact hole respectively with the body contact zone
And the electrostatic protection structure is connected.
Preferably, the electrostatic protection structure includes the first doped region and the second doped region, first doped region
Domain is opposite with the doping type of second doped region.
Preferably, the thickness range of the electrostatic protection structure is 3000~6000 angstroms.
As described above, MOS electrostatic protection trench device of the invention and its manufacturing method, have the advantages that this
Invention reduces one layer of photoetching process, optimizes the difference in height of electrostatic protection structure part and substrate, subsequent so as to optimize
Photoetching window considerations；Using the selective etch of silicon nitride and silica, to form the slot type structure of electrostatic protection；It should
Method preparation MOS electrostatic preventing structure simple process, difficulty is small, cost is relatively low.
Detailed description of the invention
Fig. 1~Figure 15 is shown as the present invention and implements the structure sectional view that specific process step is presented, in which:
Fig. 1 is shown as substrate cross-sectional view.
Fig. 2 is shown as formed as the cross-sectional view after hard mask window.
Fig. 3 is shown as etching and forms the cross-sectional view after groove.
Fig. 4 is shown as the cross-sectional view after growth sacrificial oxide layer.
Fig. 5 is shown as the cross-sectional view after growth gate dielectric layer.
Fig. 6 is shown as the cross-sectional view after the first polysilicon layer of deposit.
Fig. 7 is shown as forming the cross-sectional view after the first polysilicon layer in the trench.
Fig. 8 is shown as the cross-sectional view after deposit silicon nitride layer.
Fig. 9 is shown as the cross-sectional view after the second polysilicon layer of deposit.
Figure 10 is shown as the cross-sectional view after etching the second polysilicon layer of active region.
Figure 11 is shown as the cross-sectional view after etching active region silicon nitride layer.
Figure 12 is shown as forming body area, source region, body contact zone in active region；Electrostatic protection is formed in electrostatic protection region
The cross-sectional view of structure.
Figure 13 is shown as formed as the cross-sectional view after insulating medium layer.
Figure 14 is shown as formed as the cross-sectional view after contact hole.
Figure 15 is shown as the cross-sectional view after deposited metal, wherein Figure 15 is also displayed as MOS electrostatic protection ditch of the invention
The structural schematic diagram of slot device.
Component label instructions
I active region
II electrostatic protection region
101 drain regions
102 epitaxial layers
103 dielectric layers
104 hard mask layers
105 hard mask windows
106 grooves
107 sacrificial oxide layers
108 gate dielectric layers
109 first polysilicon layers
200 silicon nitride layers
201 second polysilicon layers
202 first doped regions
203 second doped regions
204 body areas
205 source regions
206 drift regions
207 body contact zones
208 insulating medium layers
209 contact holes
300 metal layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 1 Figure 15.It should be noted that diagram provided in the present embodiment only illustrates this hair in a schematic way
Bright basic conception, only shown in schema then with related component in the present invention rather than component count when according to actual implementation,
Shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its component
Being laid out kenel may also be increasingly complex.
Embodiment one
As shown in Fig. 1 to Figure 15, the present invention provides a kind of manufacturing method of MOS electrostatic protection trench device, the manufacture
Method the following steps are included:
Step 1) is first carried out, as shown in Figure 1, providing a substrate, the substrate includes drain region 101 and dielectric layer
103；The dielectric layer 103 has the first face and the second face corresponding with first face；103 first face of the dielectric layer knot
Together in the drain region 101；The dielectric layer 103 is laterally divided into active region I and electrostatic protection region II.
As an example, the substrate be IV race's semiconductor material or III-V group semi-conductor material, including but not limited to silicon,
Germanium silicon, gallium nitride or GaAs etc., in the present embodiment, the material of the substrate are preferably cheap silicon materials.
As an example, also there is epitaxial layer 102 between 103 first face of the drain region 101 and the dielectric layer, it is described outer
Prolong layer 102 as buffer area.In the present embodiment, the epitaxial layer 102 is the first conduction type.
As an example, the doping concentration of the drain region 101, epitaxial layer 102 and dielectric layer 103 successively reduces, wherein
The drain region 101 is the first conduction type of heavy doping, and the dielectric layer 103 is that the first conduction type is lightly doped.
In the present embodiment, first conduction type and the second conduction type transoid conduction type each other.Described first
Conduction type is N-type conduction type, and second conduction type is P-type conduction type.It in another embodiment can be by described
One conduction type replaces with P-type conduction type, and second conduction type replaces with N-type conduction type, and however, it is not limited to this.
In the present embodiment, the drain region 101 is N++ type, and the epitaxial layer 102 is N+ type, the epitaxial layer 103
For N-type.Wherein, n-type doping ion is any one in P or As or two kinds of combinations, in the present embodiment, the n-type doping
Ion is P.
It should be noted that the presence of the dielectric layer 103 of N-type is the breakdown voltage in order to increase pre- making devices；
Further, there is also the epitaxial layers 102 of N+ type to be used as buffer area in the present embodiment, and the purpose is to avoid described in N++ type
Drain region 101 transits directly to the dielectric layer 103 of N-type and the reduction of the breakdown voltage that leads to pre- making devices.
Then step 2) is executed, as shown in Fig. 2, depositing hard exposure mask 104 in 103 second face of dielectric layer and carrying out to it
Photoetching is etched through and exposes 103 second face of dielectric layer, to form hard mask window 105；Deposit the hard exposure mask 104
Method include chemical vapor deposition or physical vapour deposition (PVD), preferably use chemical vapor deposition in the present embodiment.To described
Hard exposure mask 104 carries out photoetching, etching refers to the coating photoresist (not shown) on the hard exposure mask 104 and exposes, develops to it,
Hard exposure mask 104 then described the part for not covering photoresist is etched to form the hard mask window 105, finally removes photoresist.
Due to the content that photoetching, etch process are well known to those skilled in the art, details are not described herein.
As an example, the material of the hard exposure mask 104 includes one of silicon nitride and silica.Pass through the hard exposure mask
Window 105 is etched the dielectric layer 103, to be formed several regularly arranged in the dielectric layer 103 and be parallel to each other
Groove 106, as shown in Figure 3.The etch process is dry etching, wherein the dry etching includes at least plasma
Etching or reactive ion etching etch the substrate using reactive ion etching in the present embodiment.
Then step 3) is executed, as shown in figure 5, forming gate dielectric layer 108, the gate dielectric layer in the groove 106
108 cover 106 inner wall of groove and 103 second face of the dielectric layer.Formed the gate dielectric layer 108 using oxidation growth or
The method of deposition.
As an example, as shown in figure 4, further including in the dielectric layer 103 second before forming the gate dielectric layer 108
The step of growth sacrificial oxide layer 107 then removes sacrificial oxide layer 107 in face and the groove 106, described in removing
The defect and impurity in 103 second face of dielectric layer, 106 bottom of 106 side wall of groove and groove.Wherein, the sacrificial oxide layer 107 and
The material of the gate dielectric layer 108 includes one of silica and silicon oxynitride.In the present embodiment, the sacrificial oxide layer
107 preferably silica, the gate dielectric layers 108 are preferably silica.
Then step 4) is executed, as shown in fig. 6, depositing the first polysilicon layer 109 on the gate dielectric layer 108, wherein
First polysilicon layer 109 fills the groove 106 and is covered in 108 upper surface of gate dielectric layer.As an example, described
First polysilicon layer 109 is doped polysilicon, to reduce the resistance of first polysilicon layer 109, wherein a kind of doping
Method is to be doped while depositing the first polysilicon layer 109, and another method is to deposit first polycrystalline
Ion implanting and annealing process are carried out to it again after silicon layer 109.In the present embodiment, the first polysilicon layer of preferred deposition 109
It is doped simultaneously.The specific impurity of first polysilicon layer 109 is according to the different demands of device specifically made in advance
Depending on.Then, as shown in fig. 7, etching the first polysilicon layer 109 of 108 upper surface of gate dielectric layer, expose the gate medium
Layer 108.The etch process is dry etching or wet etching, wherein the dry etching includes at least plasma etching
Or reactive ion etching；The etching solution that the wet etching uses includes the mixed solution of nitric acid or nitric acid and hydrofluoric acid,
And water or acetic acid dilution can be used in wet etching to reduce etch-rate, to control etched thickness.In this implementation
In example, etches first polysilicon layer 109 and use reactive ion etching.
Then step 5) is executed, as shown in figure 8, the deposited silicon nitride layer 200 on the gate dielectric layer 108.The nitridation
Silicon layer 200 covers the upper surface of the gate dielectric layer 108 and first polysilicon layer 109 in the groove 106.
Then step 6) is executed, as shown in figure 9, depositing the second polysilicon layer 201 on the silicon nitride layer 200.As
Example, second polysilicon layer 201 is doped conductive layer, to reduce the resistance of second polysilicon layer 201,
In, a kind of doping method is to be doped while deposit the second polysilicon layer 201, and another method is to deposit institute
Ion implanting and annealing process are carried out to it again after stating the second polysilicon layer 201.
Then step 7) is executed, as shown in Figure 10, is removed first through the first etching described in being located in the active region I
Second polysilicon layer 201, as shown in figure 11, then the silicon nitride layer through the second etching removal in the active region I
200, expose 108 top of gate dielectric layer.
As an example, described first is etched to dry etching；Described second is etched to wet etching.The dry etching packet
Plasma etching or reactive ion etching are included, to remove second polysilicon layer 201 being located in the active region I.
The etching solution that the wet etching uses includes phosphoric acid solution, and the phosphoric acid solution has selectivity to silicon nitride and silica
Therefore etching when the gate dielectric layer 108 is using silica material, when being etched, can effectively etch the silicon nitride
Layer 200 is etched without being formed to 108 upper surface of gate dielectric layer.Using this method, on the one hand reduce one layer of photoetching work
Skill；On the other hand the difference in height of second polysilicon layer 201 and 108 upper surface of gate dielectric layer is optimized；So as to
Optimize subsequent photoetching window considerations, while optimizing the subsequent difference in height for preparing electrostatic protection structure part and substrate.This implementation
In example, the thickness range of the electrostatic protection structure is 3000~6000 angstroms, better than electrostatic protection structure described in the prior art
Thickness (about 8000 angstroms).
In the present embodiment, first engraving method is reactive ion etching, and second engraving method is using phosphorus
The wet etching of acid solution.
Then step 8) is executed, as shown in figure 12, forms the in the dielectric layer 103 positioned at the active region I
The body area 204 of two conduction types and the source region 205 of the first conduction type；It is conductive that second is formed in second polysilicon 201
First doped region 202 of type and the second doped region 203 of the first conduction type, first doped region 202 and institute
The alternately connection, regularly arranged and be parallel to each other of the second doped region 203 is stated, to form electrostatic protection structure.Positioned at the body
The dielectric layer 103 of 204 lower section of area is drift region 206, and the groove 106 stretches to the drift region 206, and the groove
106 body areas 204 adjacent thereto and source region 205 are in contact.
As an example, the step of forming the body area 204, source region 205 and electrostatic protection structure in the step 8) includes:
It is injected by first time ion doping, forms the body area 204 with the second conduction type and first doped region
202；It injects to form the source region 205 and second doped region with the first conduction type by second of ion doping
203.The Doped ions for forming the body area 204 and first doped region 202 include B, BF, BF2Or it is any one in In
Kind combines, and in the present embodiment, forming preferred Doped ions when the body area 204 and first doped region 202 is B；
The Doped ions for forming the source region 205 and first doped region 203 include any one or combination in P or As, this
In embodiment, forming preferred Doped ions when the source region 205 and second doped region 203 is P.
Then step 9) is executed, forms the body contact zone 207 of the second conduction type in the body area 204.Described in formation
The specific steps of body contact zone 207 include: using photoetching, etching, ion implanting and annealing.As shown in figure 12, described active
The surface spin coating photoresist of gate dielectric layer 108 described in the I of region is then exposed development to the photoresist, forms pre-implant
The photoresist window of the body contact zone 207 then carries out P++ type ion implanting, removal to the region for not covering the photoresist
The photoresist and high annealing connect body described in the corresponding formation of body area 204 P+ type of photoresist window in active region I
Area 207 is touched, 207 concentration of body contact zone can be adjusted by P++ type ion implanting.Wherein, the ion of the P++ type injection
For B, BF, BF2Or any one or combination in In, it is B that ion is preferably injected in the present embodiment one.
Then step 10) is executed to be formed in the active region I and the electrostatic protection region II as shown in figure 13
Insulating medium layer 208.Wherein, the material of the insulating medium layer 208 includes one in silica, silicon oxynitride or silicon nitride
Kind.
As an example, the body area 204, source region can formed by forming the insulating medium layer 208 in the step 10)
205, it is made before electrostatic protection structure and body contact zone 207.
As an example, the body area 204, source region can formed by forming the insulating medium layer 208 in the step 10)
205, it is made after electrostatic protection structure and body contact zone 207.
In the present embodiment, it forms the insulating medium layer 208 and is forming the body area 204, source region 205, electrostatic protection
It is made after structure and body contact zone 207.
Then step 11) is executed, as shown in figure 14, etches the insulating medium layer 208, forms the exposure body contact zone
The contact hole 209 of 207 upper surfaces and the contact hole 209 of 203 upper surface of the second doped region.Form the contact hole 209
Method the prior art can be used, details are not described herein again.
Then step 12) is executed, as shown in figure 15, the structure upper surface deposited metal obtained after the step 11)
Layer 300 then uses photoetching, etch process, obtains positioned at the source body contact metal layer of the active region I and positioned at described quiet
The gate contact metal layer of electric zone of protection II.Wherein, the source body contact metal layer directly with the source region 205 and the body
207 Ohmic contact of contact zone, and the source body contact metal layer passes through in the insulating medium layer 208 and the groove 106
First polysilicon layer 109 is dielectrically separated from；The gate contact metal layer passes through the institute positioned at the electrostatic protection region II
Contact hole 209 is stated to connect with 203 ohm of second doped region with the first conduction type in the electrostatic protection structure
Touching.
The present invention reduces one layer of photoetching processes, optimize the difference in height of electrostatic protection structure part and substrate, so as to
To optimize subsequent photoetching window considerations；Using the selective etch of silicon nitride and silica, to form the ditch of electrostatic protection
Trench structure；This method preparation MOS electrostatic preventing structure simple process, difficulty is small, cost is relatively low.
Embodiment two
As shown in figure 15, the present invention also provides a kind of MOS electrostatic protection trench device, the MOS electrostatic protection groove devices
Part includes:
Substrate, the substrate include drain region 101 and dielectric layer 103；The dielectric layer 103 have the first face and with institute
State corresponding second face in the first face；103 first face of dielectric layer is incorporated into the drain region 101；The dielectric layer 103
Laterally it is divided into active region I and electrostatic protection region II；
Several grooves 106 include first in the groove 106 in the dielectric layer 103 of the active region I
Polysilicon layer 109；
Silicon nitride layer 200, positioned at 103 second face of the dielectric layer of the electrostatic protection region II；
Electrostatic protection structure is located at 200 top of silicon nitride layer.
As an example, also having epitaxial layer 102 between 103 first face of the drain region 101 and the dielectric layer.It is described
Epitaxial layer 102 is used as buffer area.In the present embodiment, the epitaxial layer 102 is the first conduction type.
As an example, the doping concentration of the drain region 101, epitaxial layer 102 and dielectric layer 103 successively reduces, wherein
The drain region 101 is the first conduction type of heavy doping, and the dielectric layer 103 is that the first conduction type is lightly doped.
In the present embodiment, first conduction type and second conduction type transoid conduction type each other.It is described
First conduction type is N-type conduction type, and second conduction type is P-type conduction type.It in another embodiment can be by institute
It states the first conduction type and replaces with P-type conduction type, second conduction type replaces with N-type conduction type, but does not limit to
In this.
In the present embodiment, the drain region 101 is N++ type, and the epitaxial layer 102 is N+ type, the epitaxial layer 103
For N-type.Wherein, n-type doping ion is any one in P or As or two kinds of combinations, in the present embodiment, the n-type doping
Ion is P.
It should be noted that the presence of the dielectric layer 103 of N-type is the breakdown voltage in order to increase pre- making devices；
Further, in the present embodiment there is also N+ type the epitaxial layer 102 be used as buffer area, the purpose is to avoid the institute of N++ type
It states drain region 101 and transits directly to the dielectric layer 103 of N-type and the reduction of the breakdown voltage that leads to pre- making devices.
As an example, interior and described 103 second face of dielectric layer of the groove 106 has gate dielectric layer 108, the gate medium
Layer 108 covers 106 inner wall of groove and 103 second face of the dielectric layer.
As an example, being deposited with the first polysilicon layer 109 on the gate dielectric layer 108, wherein first polysilicon
109 filling of the layer groove 106 is simultaneously covered in 108 upper surface of gate dielectric layer.As an example, first polysilicon layer
109 be doped polysilicon, to reduce the resistance of first polysilicon layer 109.
As an example, positioned at the active region I the dielectric layer 103 from the dielectric layer 103 first towards described
103 second face of dielectric layer successively includes drift region 206, body area 204 and source region 205, further includes body contact zone in the body area 204
207。
As an example, the electrostatic protection structure includes the first doped region 202 and the second doped region 203.
As an example, the body area 204, the first doped region 202 and the body contact zone 207 are the second conduction type,
The source region 205 and second doped region 203 are the first conduction type.First doped region 202 and described second
The alternately connection, regularly arranged and be parallel to each other of doped region 203, to form the electrostatic protection structure.The drift region 206
For the dielectric layer 103 of 204 lower section of body area, the groove 106 stretches to the drift region 206, and the groove 106
Body area 204 and source region 205 adjacent thereto is in contact.
As an example, the Doped ions in the body area 204, the first doped region 202 and the body contact zone 207 include B,
BF、BF2Or any one or combination in In, in the present embodiment, the body area 204, the first doped region 202 and the body are connect
Touching the Doped ions that area 207 uses is preferably B；The Doped ions packet that the source region 205 and second doped region 203 use
Include any one or the combination in P or As, in the present embodiment, what the source region 205 and second doped region 203 used mixes
Heteroion is preferably P.
As an example, 103 second face of dielectric layer and the electrostatic protection structure upper surface further include insulating medium layer
208 and metal layer 300, the insulating medium layer 208 cover table on 103 second face of dielectric layer and the electrostatic protection structure
Face, the metal layer 300 are divided into mutually independent source body contact metal layer and gate contact metal layer.
As an example, the source body contact metal layer and gate contact metal layer by contact hole 209 respectively with the body
Contact zone and the electrostatic protection structure are connected.
As an example, the source body contact metal layer by the contact hole 209 directly with the source region 205 and the body
207 Ohmic contact of contact zone, and the source body contact metal layer passes through in the insulating medium layer 208 and the groove 106
First polysilicon layer 109 is dielectrically separated from；The gate contact metal layer passes through the institute positioned at the electrostatic protection region II
Contact hole 209 is stated to connect with 203 ohm of second doped region with the first conduction type in the electrostatic protection structure
Touching.
As an example, the material of the insulating medium layer 208 includes one in silica, silicon oxynitride or silicon nitride
Kind.
As an example, the thickness range of the electrostatic protection structure is 3000~6000 angstroms.
The present invention, as barrier layer, is reduced the thickness of electrostatic protection structure, optimizes electrostatic protection using silicon nitride layer
The difference in height of structure division and substrate, so that subsequent preparation MOS electrostatic preventing structure difficulty reduces.
In conclusion MOS electrostatic protection trench device of the present invention and its manufacturing method, reduce one layer of photoetching process, it is excellent
The difference in height of electrostatic protection structure part and substrate is changed, so as to optimize subsequent photoetching window considerations；It is lost using wet process
It carves, by etchant to the selective etch of silicon nitride and silica, to form the slot type structure of electrostatic protection；This method
Preparation MOS electrostatic preventing structure simple process, difficulty is small, cost is relatively low, so, the present invention effectively overcomes in the prior art
Various shortcoming and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (14)
1. a kind of manufacturing method of MOS electrostatic protection trench device, which is characterized in that the manufacturing method the following steps are included:
A substrate is provided, the substrate includes drain region and dielectric layer；The dielectric layer has the first face and with described first
Corresponding second face in face；First face of dielectric layer is incorporated into the drain region；The dielectric layer is laterally divided into active
Region and electrostatic protection region；
Several grooves are formed in the dielectric layer of the active region, and form the first polysilicon layer in the trench；
It sequentially forms silicon nitride layer and the second polysilicon layer from bottom to top on second face of dielectric layer, and removes positioned at described
The silicon nitride layer of active region and second polysilicon layer；
Electrostatic protection structure is made based on second polysilicon layer for being located at the electrostatic protection region, and will be located at described quiet
The silicon nitride layer of electric zone of protection is as barrier layer.
2. the manufacturing method of MOS electrostatic protection trench device according to claim 1, it is characterised in that: in the groove
It further include in the groove and forming gate dielectric layer on the second face of the dielectric layer before middle formation first polysilicon layer
The step of.
3. the manufacturing method of MOS electrostatic protection trench device according to claim 2, it is characterised in that: described in formation
It further include growing in the groove and on the second face of the dielectric layer described in sacrificial oxide layer then removes before gate dielectric layer
The step of sacrificial oxide layer.
4. the manufacturing method of MOS electrostatic protection trench device according to claim 1, it is characterised in that: removal is located at institute
The method for stating the silicon nitride layer of active region includes wet etching.
5. the manufacturing method of MOS electrostatic protection trench device according to claim 1, it is characterised in that: further include in institute
State the step of body area, source region and body contact zone are formed in the dielectric layer of active region.
6. the manufacturing method of MOS electrostatic protection trench device according to claim 5, it is characterised in that: described in formation
The first doped region is formed in second polysilicon layer while body area；Described second while forming the source region
The second doped region is formed in polysilicon layer, first doped region is opposite with the doping type of second doped region.
7. the manufacturing method of MOS electrostatic protection trench device according to claim 5, it is characterised in that: further include in institute
It states the second face of dielectric layer and the electrostatic protection structure upper surface and from bottom to top sequentially forms the step of insulating medium layer and metal layer
Suddenly.
8. a kind of MOS electrostatic protection trench device, which is characterized in that the MOS electrostatic protection trench device includes:
Substrate, the substrate include drain region and dielectric layer；The dielectric layer has the first face and opposite with first face
The second face answered；First face of dielectric layer is incorporated into the drain region；The dielectric layer be laterally divided into active region and
Electrostatic protection region；
Several grooves include the first polysilicon layer in the groove in the dielectric layer of the active region；
Silicon nitride layer, positioned at second face of the dielectric layer in the electrostatic protection region；
Electrostatic protection structure is located above the silicon nitride layer.
9. MOS electrostatic protection trench device according to claim 8, it is characterised in that: the drain region with given an account of
Also there is epitaxial layer between the first face of matter layer.
10. MOS electrostatic protection trench device according to claim 8, it is characterised in that: positioned at the institute of the active region
It successively includes drift region, body area and source region, the body towards second face of dielectric layer that dielectric layer, which is stated, from the dielectric layer first
It further include body contact zone in area.
11. MOS electrostatic protection trench device according to claim 10, it is characterised in that: second face of dielectric layer and
The electrostatic protection structure upper surface further includes insulating medium layer and metal layer, and the metal layer is divided into mutually independent source body
Contact metal layer and gate contact metal layer.
12. MOS electrostatic protection trench device according to claim 11, it is characterised in that: the source body contact metal layer
And gate contact metal layer is connected with the body contact zone and the electrostatic protection structure respectively by contact hole.
13. MOS electrostatic protection trench device according to claim 8, it is characterised in that: the electrostatic protection structure includes
First doped region and the second doped region, first doped region are opposite with the doping type of second doped region.
14. MOS electrostatic protection trench device according to claim 8, it is characterised in that: the thickness of the electrostatic protection structure
Spending range is 3000~6000 angstroms.
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