CN109714031B - Rail-to-rail high-performance comparator - Google Patents
Rail-to-rail high-performance comparator Download PDFInfo
- Publication number
- CN109714031B CN109714031B CN201811507731.XA CN201811507731A CN109714031B CN 109714031 B CN109714031 B CN 109714031B CN 201811507731 A CN201811507731 A CN 201811507731A CN 109714031 B CN109714031 B CN 109714031B
- Authority
- CN
- China
- Prior art keywords
- transistor
- differential amplification
- amplification unit
- drain
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a rail-to-rail high-performance comparator, which comprises a first primary differential amplification unit, a second primary differential amplification unit, an integration conversion unit and a rear-stage differential amplification unit, wherein the input end of the first primary differential amplification unit is connected with the input end of the second primary differential amplification unit so as to receive an external signal to be compared and perform primary amplification processing, the first primary differential amplification unit is controlled by an N-type switching tube, and the second primary differential amplification unit is controlled by a P-type switching tube; the integration conversion unit integrates the primary amplified signals output by the first primary differential amplification unit and the second primary differential amplification unit; the post-stage differential amplification unit compares, amplifies and outputs the integrated signal; the design improves the common mode rejection ratio through multi-stage amplification, reduces the deviation caused by asymmetry, achieves good symmetry and amplification linearity consistency, and simultaneously integrates and superposes the integrated conversion unit to offset the deviation in primary differential amplification, so that the finally output comparison signal is stable.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a comparator circuit.
Background
A conventional comparator, particularly a CMOS differential comparator, as shown in fig. 1, is composed of a P-channel transistor MOS1', a P-channel transistor MOS2', an N-channel transistor MOS3', and an N-channel transistor MOS4'; the grid of the transistor MOS1' receives an input signal of one, the grid of the transistor MOS2' receives another input signal, the source of the transistor MOS1' and the source of the transistor MOS2' are both connected with a constant current source, the drain of the transistor MOS1' is respectively connected with the grid and the drain of the transistor MOS3' and the grid of the transistor MOS4', the source of the transistor MOS3' is grounded, the source of the transistor MOS4' is grounded, and the drain of the transistor MOS2' is connected with the drain of the transistor MOS4' and outputs;
since the circuit structure of the CMOS differential comparator is asymmetric, even when the same signal is input from both ends of the gate of the transistor MOS1 'and the gate of the transistor MOS2', respectively, the two output signals have large deviation, the common mode rejection ratio is low, which causes inaccuracy of the signal output by the comparator, and the linearity is poor, in order to solve the problem, the applicant tries to adopt a circuit structure of multi-stage differential amplification, however, although the common mode rejection ratio is improved to a certain extent, the waveform of a general input signal has a high end portion and a low end portion relatively, when primary amplification is performed, the signal is generally input to a differential amplification circuit controlled by an N-type switch tube or a P-type switch tube, due to the characteristics of the switch tube, the amplified signal has a certain deviation, which causes the high end portion of the finally output signal to be more normal and the low end portion to be more normal and the high end portion to be more normal, for example, when a differential amplification circuit using an N-channel MOS tube as a control tube is used, as shown in fig. 2, the amplification characteristics of the N-channel MOS tube, the output signal is reflected in the waveform and the high end portion and the amplitude portion is not good but the low end portion is not affected by the linearity difference, and then the first-stage amplification performance is not affected by the first-stage differential amplification.
Further, in the process of amplifying the signal, the signal fluctuates regardless of rising or falling, and in the process of amplifying, the fluctuation is easily amplified, and finally, the output signal has large jitter and poor effect.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a comparator capable of achieving rail-to-rail consistency of high-end amplitude and low-end amplitude of an output signal, good symmetry, and improving a common mode rejection ratio through a multi-stage amplification structure.
The technical scheme adopted by the invention is as follows:
a rail-to-rail high performance comparator comprising:
the input end of the first primary differential amplification unit is connected with the input end of the second primary differential amplification unit to receive an external input signal and perform primary amplification processing, the first primary differential amplification unit is controlled by an N-type switching tube, and meanwhile, the second primary differential amplification unit is controlled by a P-type switching tube;
the integration conversion unit is respectively connected with the output end of the first primary differential amplification unit and the output end of the second primary differential amplification unit so as to integrate primary amplified signals output by the first primary differential amplification unit and the second primary differential amplification unit;
and the rear-stage differential amplification unit is connected with the output end of the integrated conversion unit and compares, amplifies and outputs the integrated signal.
The delay processing unit is respectively connected with the output end of the first primary differential amplification unit and/or the output end of the second primary differential amplification unit so as to delay the signals output by the first primary differential amplification unit and the second primary differential amplification unit after primary amplification.
The first primary differential amplification unit comprises an N-channel transistor MOS10, an N-channel transistor MOS11, a P-channel transistor MOS5 and a P-channel transistor MOS6;
the source of the transistor MOS10 is connected to the source of the transistor MOS11 and an external current source, respectively;
the drain electrode of the transistor MOS10 is respectively connected with the drain electrode of the transistor MOS5, the grid electrode of the transistor MOS5, the hysteresis processing unit and the integrated conversion unit;
the drain electrode of the transistor MOS11 is respectively connected with the drain electrode of the transistor MOS6, the grid electrode of the transistor MOS6, the hysteresis processing unit and the integrated conversion unit;
the source electrode of the transistor MOS5 and the source electrode of the transistor MOS6 are both connected with an external power supply;
the gate of the transistor MOS10 and the gate of the transistor MOS11 receive external signals to be compared, respectively.
The second primary differential amplifying unit comprises a P-channel transistor MOS9, a P-channel transistor MOS12, an N-channel transistor MOS15 and an N-channel transistor MOS16;
the source of the transistor MOS9 is connected to the source of the transistor MOS12 and an external current source, respectively;
the drain electrode of the transistor MOS9 is respectively connected with the drain electrode of the transistor MOS15, the grid electrode of the transistor MOS15, the hysteresis processing unit and the integrated conversion unit;
the drain of the transistor MOS12 is connected to the drain of the transistor MOS16, the gate of the transistor MOS16, the hysteresis processing unit, and the integration conversion unit, respectively;
the source of the transistor MOS15 and the source of the transistor MOS16 are both grounded;
the gate of the transistor MOS9 is connected to the gate of the transistor MOS 10; the gate of the transistor MOS12 is connected to the gate of the transistor MOS 11.
The integrated conversion unit comprises a transistor MOS3 with a P channel and a transistor MOS8 with a P channel;
the grid electrode of the transistor MOS3 is connected with the grid electrode of the transistor MOS 5;
the gate of the transistor MOS8 is connected with the gate of the transistor MOS6;
the source electrode of the transistor MOS3 and the source electrode of the transistor MOS8 are both connected with an external power supply;
the drain electrode of the transistor MOS3 is respectively connected with the drain electrode of the transistor MOS16 and one input end of the post-stage differential amplification unit;
the drain of the transistor MOS8 is connected to the drain of the transistor MOS15 and the other input terminal of the subsequent stage differential amplifying unit, respectively.
The hysteresis processing unit comprises a transistor MOS4 with a P channel, a transistor MOS7 with a P channel, a transistor MOS14 with an N channel and a transistor MOS17 with an N channel;
the gate of the transistor MOS4 is connected to the gate of the transistor MOS5 and the drain of the transistor MOS7, respectively;
the gate of the transistor MOS7 is connected to the gate of the transistor MOS6 and the drain of the transistor MOS4, respectively;
the source electrode of the transistor MOS4 and the source electrode of the transistor MOS7 are both connected with an external power supply;
the gate of the transistor MOS17 is connected to the gate of the transistor MOS16 and the drain of the transistor MOS14, respectively;
the gate of the transistor MOS14 is connected to the gate of the transistor MOS15 and the drain of the transistor MOS17, respectively;
the source of the transistor MOS14 and the source of the transistor MOS17 are grounded.
The post-stage differential amplification unit comprises a transistor MOS1 with a P channel, a transistor MOS2 with a P channel, a transistor MOS13 with an N channel and a transistor MOS18 with an N channel;
the gate of the transistor MOS13 is connected to the drain of the transistor MOS8;
the drain electrode of the transistor MOS13 is respectively connected with the drain electrode of the transistor MOS1, the grid electrode of the transistor MOS1 and the grid electrode of the transistor MOS 2;
the gate of the transistor MOS18 is connected to the drain of the transistor MOS 3;
the source of the transistor MOS13 and the source of the transistor MOS18 are both grounded;
the source electrode of the transistor MOS1 and the source electrode of the transistor MOS2 are connected with an external power supply;
the drain of the transistor MOS2 is connected to the drain of the transistor MOS18 and outputs a comparison amplification signal.
The device also comprises a phase inverter U1, wherein the input end of the phase inverter U1 is connected with the output end of the post-stage differential amplification unit.
The first primary differential amplification unit is composed of an NPN type triode.
The second primary differential amplification unit is composed of a PNP type triode.
The invention has the beneficial effects that:
the comparator inputs signals to be compared into a first primary differential amplification unit and a second primary differential amplification unit, the first primary differential amplification unit is controlled by an N-type switching tube, according to the characteristics of a differential amplification circuit controlled by the N-type switching tube, a better amplification effect is achieved on the high end side of the output amplification signals, a certain degree of deviation exists on the low end side, the second primary differential amplification unit is controlled by a P-type switching tube, the output effect is just opposite to that of the first primary differential amplification unit, the integration conversion unit receives the signals amplified by the first primary differential amplification unit and the second primary differential amplification unit, the two signals are ingeniously superposed and integrated, the complementary cancellation effect is achieved, the deviation in primary amplification is prevented from flowing into the next stage amplification unit, the amplitudes of the signals integrated by the integration conversion unit on the high end side and the low end side are kept consistent, the balanced symmetrical amplification effect consistent from rail to rail is achieved, meanwhile, the output signals are amplified by the rear stage differential amplification unit once again, the design improves the suppression ratio by multi-stage amplification, the amplitudes of the signals integrated conversion unit are integrated, the amplitude is kept consistent on the high end side and the common mode amplification, the common mode amplification circuit is reduced, and the common mode signal is finally output through the simple and the stable conversion.
Furthermore, the hysteresis processing unit is used for performing hysteresis processing on the signals output by the first primary differential amplification unit and the second primary differential amplification unit, so that the fluctuation of the input signal is prevented from being amplified in the amplification unit, the signal stability is ensured, and the anti-noise performance is strong.
Drawings
The following description will further describe embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a conventional differential amplifier circuit.
Fig. 2 is a waveform diagram of an output of a differential amplifier circuit controlled by the input of a P-type switch tube.
Fig. 3 is a circuit schematic of the comparator of the present invention.
Detailed Description
As shown in fig. 3, a rail-to-rail high performance comparator comprises:
the input end of the first primary differential amplification unit 1 is connected with the input end of the second primary differential amplification unit 2 to receive external input signals and perform primary amplification processing, the first primary differential amplification unit 1 is controlled by an N-type switching tube, and the second primary differential amplification unit 2 is controlled by a P-type switching tube;
an integration conversion unit 3, which is respectively connected to the output terminal of the first primary differential amplification unit 1 and the output terminal of the second primary differential amplification unit 2 to integrate the primary amplified signals output by the first primary differential amplification unit 1 and the second primary differential amplification unit 2;
and the rear-stage differential amplification unit 4 is connected with the output end of the integrated conversion unit 3 and compares, amplifies and outputs the integrated signal.
According to the design, a signal to be compared is input into a first primary differential amplification unit 1 and a second primary differential amplification unit 2, the first primary differential amplification unit 1 is controlled by an N-type switching tube, according to the characteristics of a differential amplification circuit controlled by the N-type switching tube, a good amplification effect is achieved on the high-end side of the output amplification signal, a certain degree of deviation exists on the low-end side, as shown in fig. 2, the amplitude of the low-end side is narrow, the second primary differential amplification unit 2 is controlled by a P-type switching tube, the output effect is just opposite to that of the first primary differential amplification unit 1, the amplitude of the low-end side of the signal output by the second primary differential amplification unit 2 controlled by the P-type switching tube is narrow, and the high-end side is generally normal.
Because the first primary differential amplification unit 1 and the second primary differential amplification unit 2 input signals to be compared with the input end, according to the amplification characteristics of the differential amplification circuit, no matter under N-tube control or P-tube control, the output signal periods are basically identical, and the integration conversion unit receives the signals amplified by the first primary differential amplification unit 1 and the second primary differential amplification unit 2, the two signals are ingeniously overlapped and integrated, namely, the two signals are overlapped at the high end side and overlapped at the low end side, so that complementation is ingeniously realized by a simple circuit, the effect of offsetting the two deviations by the integrated signals is achieved, the deviation generated in primary amplification is prevented from flowing into the next stage amplification unit, the amplitude values of the high end side and the low end side of the signals integrated by the integration conversion unit 3 are kept consistent, the balanced symmetrical amplification effect of rail-to-integration rail consistency is achieved, meanwhile, the output signals are amplified by the post-stage differential amplification unit 4 again, the common mode rejection ratio is improved by multi-stage amplification, the deviation caused by the conventional differential amplification circuit is reduced, good symmetrical amplification effect is achieved, and the simple output deviation of the integrated conversion unit is finally offset by the low energy consumption of the integrated conversion unit 3, and the simple comparison circuit.
The delay processing unit 5 is respectively connected with the output end of the first primary differential amplification unit 1 and/or the output end of the second primary differential amplification unit 2 to delay the signals output by the first primary differential amplification unit 1 and the second primary differential amplification unit 2 after primary amplification.
The signals output by the first primary differential amplifying unit 1 and the second primary differential amplifying unit 2 are subjected to hysteresis processing by the hysteresis processing unit 5, so that the fluctuation of the input signals is prevented from being amplified in the amplifying units, the stability of the signals is ensured, and the anti-noise performance is strong.
The design is accompanied by a hysteresis function, so that a perfect and stable signal is finally output, the anti-noise anti-interference capability is strong, the circuit is simple, the energy consumption is low, and the design can be widely applied to various electronic products, particularly integrated circuit chip electronic products.
In the present design, the first primary differential amplifying unit 1 may be formed by an NPN type transistor, and the second primary differential amplifying unit 2 may be formed by a PNP type transistor, and as a preferred embodiment, the present design uses an N-channel MOS transistor to control the first primary differential amplifying unit 1, and a P-channel MOS transistor is used as a load side of the first primary differential amplifying unit 1, and similarly, a P-channel MOS transistor is used to control the second primary differential amplifying unit 2, and an N-channel MOS transistor is used as a load side of the second primary differential amplifying unit 2, and of course, in terms of a specific circuit arrangement manner and a specific selection of elements, a selection and a modification may be performed in a conventional specification, as long as the arrangement is performed according to the concept and principle of the present design, and the protection range of the present design is included.
The first primary differential amplifying unit 1 includes an N-channel transistor MOS10, an N-channel transistor MOS11, a P-channel transistor MOS5, and a P-channel transistor MOS6;
the source of the transistor MOS10 is connected to the source of the transistor MOS11 and an external current source, respectively;
the drain of the transistor MOS10 is connected to the drain of the transistor MOS5, the gate of the transistor MOS5, the hysteresis processing unit 5, and the integration conversion unit 3, respectively;
the drain of the transistor MOS11 is connected to the drain of the transistor MOS6, the gate of the transistor MOS6, the hysteresis processing unit 5, and the integral conversion unit 3, respectively;
the source electrode of the transistor MOS5 and the source electrode of the transistor MOS6 are both connected with an external power supply;
the gate of the transistor MOS10 and the gate of the transistor MOS11 receive external signals to be compared, respectively.
The second primary differential amplifying unit 2 includes a P-channel transistor MOS9, a P-channel transistor MOS12, an N-channel transistor MOS15, and an N-channel transistor MOS16;
the source of the transistor MOS9 is connected to the source of the transistor MOS12 and an external current source, respectively;
the drain of the transistor MOS9 is respectively connected with the drain of the transistor MOS15, the gate of the transistor MOS15, the hysteresis processing unit 5 and the integrated conversion unit 3;
the drain of the transistor MOS12 is connected to the drain of the transistor MOS16, the gate of the transistor MOS16, the hysteresis processing unit 5, and the integral conversion unit 3, respectively;
the source of the transistor MOS15 and the source of the transistor MOS16 are both grounded;
the gate of the transistor MOS9 is connected with the gate of the transistor MOS 10; the gate of the transistor MOS12 is connected to the gate of the transistor MOS 11.
The integrated conversion unit 3 comprises a transistor MOS3 with a P channel and a transistor MOS8 with a P channel;
the grid electrode of the transistor MOS3 is connected with the grid electrode of the transistor MOS 5;
the grid electrode of the transistor MOS8 is connected with the grid electrode of the transistor MOS6;
the source electrode of the transistor MOS3 and the source electrode of the transistor MOS8 are both connected with an external power supply;
the drain of the transistor MOS3 is connected to the drain of the transistor MOS16 and one input terminal of the post-stage differential amplifying unit 4;
the drain of the transistor MOS8 is connected to the drain of the transistor MOS15 and the other input terminal of the subsequent stage differential amplifying unit 4, respectively.
The hysteresis processing unit comprises a P-channel transistor MOS4, a P-channel transistor MOS7, an N-channel transistor MOS14 and an N-channel transistor MOS17;
the gate of the transistor MOS4 is connected to the gate of the transistor MOS5 and the drain of the transistor MOS7, respectively;
the gate of the transistor MOS7 is connected to the gate of the transistor MOS6 and the drain of the transistor MOS4, respectively;
the source electrode of the transistor MOS4 and the source electrode of the transistor MOS7 are both connected with an external power supply;
the gate of the transistor MOS17 is connected to the gate of the transistor MOS16 and the drain of the transistor MOS14, respectively;
the gate of the transistor MOS14 is connected to the gate of the transistor MOS15 and the drain of the transistor MOS17, respectively;
the source of the transistor MOS14 and the source of the transistor MOS17 are grounded.
The post-stage differential amplification unit comprises a transistor MOS1 with a P channel, a transistor MOS2 with a P channel, a transistor MOS13 with an N channel and a transistor MOS18 with an N channel;
the gate of the transistor MOS13 is connected to the drain of the transistor MOS8;
the drain of the transistor MOS13 is respectively connected with the drain of the transistor MOS1, the gate of the transistor MOS1 and the gate of the transistor MOS 2;
the gate of the transistor MOS18 is connected to the drain of the transistor MOS 3;
the source of the transistor MOS13 and the source of the transistor MOS18 are both grounded;
the source electrode of the transistor MOS1 and the source electrode of the transistor MOS2 are connected with an external power supply;
the drain of the transistor MOS2 is connected to the drain of the transistor MOS18 and outputs a comparison amplification signal.
The working flow of the circuit is that signals are input at one input end VinA and the other input end VinB of the first primary differential amplifier circuit 1 and the second primary differential amplifier circuit 2, and then the signals VinA and the signals VinB are used for illustration, and when a common-mode signal is input, the amplification amount is 0; when a differential mode signal is input, vinA is larger than VinB, the conduction ratio of MOS10 in the first primary differential amplifying unit 1 is higher than that of MOS11, the current flowing through MOS5 is larger than that of MOS6, the conduction ratio of MOS6 and MOS8 is the same as that of MOS3 and MOS5, the conduction ratio of MOS9 is smaller than that of MOS12, MOS15 and MOS14 are the same as that of MOS17 and MOS16, the same conduction effect is achieved, the amplified signal of the first primary differential amplifying unit 1 is simultaneously sent to the integrated converting unit, the conduction ratio of MOS9 in the second primary differential amplifying unit 2 is smaller than that of MOS12, MOS15 and MOS14 are the same as that of MOS16, the current flowing through MOS3 is superposed on MOS17 and MOS16, the current flowing through MOS8 is superposed on MOS15 and MOS14, so that superposition and integration complementation are achieved, the effect of offsetting the deviation of the signals after integration is achieved, and simultaneously, MOS17, MOS16 and MOS18 are the same as that of MOS16, the signal is output to one input end of the post-stage differential amplifying circuit, the MOS14, the MOS15 and the MOS13 share a gate, the signal is output to the other input end of the post-stage differential amplifying circuit 4, and at this time, the signal corresponding to one input end is higher than the signal of the other input end, the output signal of the post-stage differential amplifying circuit 4 is negative, similarly, when VinA is smaller than VinB, the output signal of the post-stage differential amplifying circuit 4 is positive, and since the input signal fluctuates, taking MOS7 as an example, when VinA fluctuates, the current flowing through the MOS10 changes, and the current at MOS7 compensates the drain of the MOS10, so that the current flowing through the MOS5 is not affected, and the hysteresis processing of the hysteresis processing unit 5 is realized, and the hysteresis processing principle of the MOS4, the MOS14 and the MOS17 is the same as that of the MOS 7.
Further, the circuit also comprises an inverter U1, wherein the input end of the inverter U1 is connected with the output end of the post-stage differential amplification unit, the output signal is inverted through the inverter U1, and when the adjustment is carried out to enable the signal input by the VinA end to be higher than the VinB end, the output comparison signal is positive.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and any technical means that can achieve the object of the present invention by basically the same means is within the scope of the present invention.
Claims (6)
1. A rail-to-rail high performance comparator, comprising:
the input end of the first primary differential amplification unit is connected with the input end of the second primary differential amplification unit to receive an external input signal and perform primary amplification processing, the first primary differential amplification unit is controlled by an N-type switching tube, and meanwhile, the second primary differential amplification unit is controlled by a P-type switching tube;
the integration conversion unit is respectively connected with the output end of the first primary differential amplification unit and the output end of the second primary differential amplification unit so as to integrate primary amplified signals output by the first primary differential amplification unit and the second primary differential amplification unit;
the rear-stage differential amplification unit is connected with the output end of the integrated conversion unit and compares, amplifies and outputs the integrated signal;
the hysteresis processing unit is respectively connected with the output end of the first primary differential amplification unit and/or the output end of the second primary differential amplification unit so as to perform hysteresis processing on the primary amplified signals output by the first primary differential amplification unit and the second primary differential amplification unit;
the first primary differential amplification unit comprises an N-channel transistor MOS10, an N-channel transistor MOS11, a P-channel transistor MOS5 and a P-channel transistor MOS6;
the source of the transistor MOS10 is connected to the source of the transistor MOS11 and an external current source, respectively;
the drain electrode of the transistor MOS10 is respectively connected with the drain electrode of the transistor MOS5, the grid electrode of the transistor MOS5, the hysteresis processing unit and the integrated conversion unit;
the drain of the transistor MOS11 is connected to the drain of the transistor MOS6, the gate of the transistor MOS6, the hysteresis processing unit, and the integration conversion unit, respectively;
the source electrode of the transistor MOS5 and the source electrode of the transistor MOS6 are both connected with an external power supply;
the grid of the transistor MOS10 and the grid of the transistor MOS11 respectively receive external signals to be compared;
the second primary differential amplification unit comprises a P-channel transistor MOS9, a P-channel transistor MOS12, an N-channel transistor MOS15 and an N-channel transistor MOS16;
the source of the transistor MOS9 is respectively connected with the source of the transistor MOS12 and an external current source;
the drain electrode of the transistor MOS9 is respectively connected with the drain electrode of the transistor MOS15, the grid electrode of the transistor MOS15, the hysteresis processing unit and the integrated conversion unit;
the drain of the transistor MOS12 is respectively connected with the drain of the transistor MOS16, the gate of the transistor MOS16, the hysteresis processing unit and the integrated conversion unit;
the source of the transistor MOS15 and the source of the transistor MOS16 are both grounded;
the gate of the transistor MOS9 is connected to the gate of the transistor MOS 10; the gate of the transistor MOS12 is connected to the gate of the transistor MOS 11;
the integrated conversion unit comprises a transistor MOS3 with a P channel and a transistor MOS8 with a P channel;
the grid electrode of the transistor MOS3 is connected with the grid electrode of the transistor MOS 5;
the gate of the transistor MOS8 is connected with the gate of the transistor MOS6;
the source electrode of the transistor MOS3 and the source electrode of the transistor MOS8 are both connected with an external power supply;
the drain electrode of the transistor MOS3 is respectively connected with the drain electrode of the transistor MOS16 and one input end of the post-stage differential amplification unit;
the drain of the transistor MOS8 is connected to the drain of the transistor MOS15 and the other input terminal of the subsequent stage differential amplification unit, respectively.
2. A rail-to-rail high performance comparator as claimed in claim 1, wherein: the hysteresis processing unit comprises a transistor MOS4 with a P channel, a transistor MOS7 with a P channel, a transistor MOS14 with an N channel and a transistor MOS17 with an N channel;
the gate of the transistor MOS4 is connected to the gate of the transistor MOS5 and the drain of the transistor MOS7, respectively;
the gate of the transistor MOS7 is connected to the gate of the transistor MOS6 and the drain of the transistor MOS4, respectively;
the source electrode of the transistor MOS4 and the source electrode of the transistor MOS7 are both connected with an external power supply;
the gate of the transistor MOS17 is connected to the gate of the transistor MOS16 and the drain of the transistor MOS14, respectively;
the gate of the transistor MOS14 is connected to the gate of the transistor MOS15 and the drain of the transistor MOS17, respectively;
the source of the transistor MOS14 and the source of the transistor MOS17 are grounded.
3. A rail-to-rail high performance comparator as claimed in claim 2, wherein: the post-stage differential amplification unit comprises a transistor MOS1 with a P channel, a transistor MOS2 with a P channel, a transistor MOS13 with an N channel and a transistor MOS18 with an N channel;
the gate of the transistor MOS13 is connected to the drain of the transistor MOS8;
the drain electrode of the transistor MOS13 is respectively connected with the drain electrode of the transistor MOS1, the grid electrode of the transistor MOS1 and the grid electrode of the transistor MOS 2;
the gate of the transistor MOS18 is connected to the drain of the transistor MOS 3;
the source of the transistor MOS13 and the source of the transistor MOS18 are both grounded;
the source electrode of the transistor MOS1 and the source electrode of the transistor MOS2 are connected with an external power supply;
the drain of the transistor MOS2 is connected to the drain of the transistor MOS18 and outputs a comparison amplification signal.
4. A rail-to-rail high performance comparator as claimed in claim 1, wherein: the device also comprises a phase inverter U1, wherein the input end of the phase inverter U1 is connected with the output end of the post-stage differential amplification unit.
5. A rail-to-rail high performance comparator as claimed in claim 1, wherein: the first primary differential amplification unit is composed of an NPN type triode.
6. A rail-to-rail high performance comparator as claimed in claim 1, wherein: the second primary differential amplification unit is composed of a PNP type triode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811507731.XA CN109714031B (en) | 2018-12-11 | 2018-12-11 | Rail-to-rail high-performance comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811507731.XA CN109714031B (en) | 2018-12-11 | 2018-12-11 | Rail-to-rail high-performance comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109714031A CN109714031A (en) | 2019-05-03 |
| CN109714031B true CN109714031B (en) | 2023-03-17 |
Family
ID=66256339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811507731.XA Active CN109714031B (en) | 2018-12-11 | 2018-12-11 | Rail-to-rail high-performance comparator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109714031B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1274171A1 (en) * | 2001-07-05 | 2003-01-08 | Telefonaktiebolaget L M Ericsson (Publ) | Differential line receiver |
| CN1845452A (en) * | 2005-04-07 | 2006-10-11 | 恩益禧电子股份有限公司 | Operational amplifier with less offset |
| CN101170299A (en) * | 2006-10-27 | 2008-04-30 | 恩益禧电子股份有限公司 | Operational amplifier and display device |
| CN101557216A (en) * | 2009-03-05 | 2009-10-14 | 深圳市民展科技开发有限公司 | Comparator and D-class audio power amplifier comprising comparator |
| CN101645693A (en) * | 2008-08-05 | 2010-02-10 | 恩益禧电子股份有限公司 | Class AB amplifier circuit and display apparatus |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
-
2018
- 2018-12-11 CN CN201811507731.XA patent/CN109714031B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1274171A1 (en) * | 2001-07-05 | 2003-01-08 | Telefonaktiebolaget L M Ericsson (Publ) | Differential line receiver |
| CN1845452A (en) * | 2005-04-07 | 2006-10-11 | 恩益禧电子股份有限公司 | Operational amplifier with less offset |
| CN101170299A (en) * | 2006-10-27 | 2008-04-30 | 恩益禧电子股份有限公司 | Operational amplifier and display device |
| CN101645693A (en) * | 2008-08-05 | 2010-02-10 | 恩益禧电子股份有限公司 | Class AB amplifier circuit and display apparatus |
| CN101557216A (en) * | 2009-03-05 | 2009-10-14 | 深圳市民展科技开发有限公司 | Comparator and D-class audio power amplifier comprising comparator |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109714031A (en) | 2019-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101459412B (en) | Full scale input-output operational amplifier | |
| CN102111115B (en) | Op-amp sharing with input and output reset | |
| CN106849938B (en) | Input buffer circuit | |
| US8446178B2 (en) | Comparator and analog-to-digital | |
| US10367454B2 (en) | Trans-impedance amplifier | |
| US20180287567A1 (en) | Differential amplification device | |
| CN109714031B (en) | Rail-to-rail high-performance comparator | |
| KR101070118B1 (en) | Analog circuit with improved response speed feature | |
| CN102570989A (en) | Operational amplifier | |
| US10171040B1 (en) | Trans-impedance amplifier | |
| CN114884491A (en) | Comparator circuit, chip and electronic equipment | |
| CN111030613B (en) | Radio frequency signal processing circuit and radio frequency front end unit | |
| CN208924195U (en) | A kind of class ab ammplifier made an uproar based on operational amplifier controlling of sampling bottom | |
| CN201966873U (en) | Point of intersect moves down the circuit | |
| US10146245B2 (en) | I-V converting module | |
| CN102064777B (en) | Amplification circuit | |
| WO2016161277A1 (en) | Balanced differential transimpedance amplifier with single ended input and balancing method | |
| CN214315206U (en) | Comparator and CAN communication chip | |
| CN104506151A (en) | An operational amplifier for medical electronics | |
| CN105991101B (en) | A kind of supply self adaptation operational amplifier | |
| Vij et al. | An operational amplifier with recycling folded Cascode topology and adaptive biaisng | |
| CN109347446A (en) | A kind of class ab ammplifier made an uproar based on operational amplifier controlling of sampling bottom | |
| CN116633342B (en) | Conversion circuit from CML (complementary metal oxide semiconductor) to CMOS (complementary metal oxide semiconductor) level with optimized duty ratio | |
| Vij et al. | A highly adaptive operational amplifier with recycling folded cascode topology | |
| CN211089598U (en) | class-D power amplifier oscillation circuit and class-D power amplifier oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |