CN109710277B - Burning method and system for onboard SPI Flash memory - Google Patents
Burning method and system for onboard SPI Flash memory Download PDFInfo
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Abstract
The invention is suitable for the field of electricity, and provides a programming method and a system for an onboard SPI Flash memory. The programming method comprises the following steps: the upper computer provided with the J-LINK driver program for driving the EJTAG debugging unit runs the J-LINK driver program, and downloads the system program to the memory chip through the EJTAG debugging interface and the embedded processor; the upper computer enables the embedded processor to run the system program downloaded into the memory chip through the EJTAG debugging interface, and when data are completely copied to the SPI Flash memory from the memory chip, the programming of the onboard SPI Flash memory is completed. Therefore, after the SPI Flash memory is fixedly connected to the circuit board, if a program needs to be programmed, the embedded processor can be controlled from the outside through a J-LINK driving program to complete programming of the onboard SPI Flash memory by directly utilizing an EJTAG debugging interface of the embedded processor on the circuit board, and a simple and convenient means is provided for subsequent equipment upgrading and maintenance.
Description
Technical Field
The invention relates to the field of electricity, in particular to a programming method and a system of an onboard SPI Flash memory.
Background
In an on-vehicle practical application scheme, in order to resist shock or save the size of an integrated circuit board, an SPI (Serial Peripheral Interface) Flash memory with a smaller Package size, such as an SOP (Small Outline Package) and a TSSOP (Thin reduced SOP Package), is often selected, and is generally called an SPI Flash memory, and is soldered on the integrated circuit board, and may be called an on-board SPI Flash memory.
For an on-board SPI Flash memory, in the prior art, a burner is generally used to burn a bare chip of the SPI Flash memory (the SPI Flash memory before burning has no executable program), and then the bare chip is uniformly soldered to an integrated circuit board, the bare chip is uniformly upgraded on the integrated circuit board by an SD card, or the system is upgraded on-line by the SD card after being normally started.
Once faults such as error erasing or upgrading failure occur in development or test, the system cannot be normally started, the method for maintaining can only blow off a welded onboard SPI Flash memory by using a special heating air gun, then burn programs by using a burner, and finally weld the onboard SPI Flash memory back to the original position again. Therefore, the method has high maintenance cost and great technical difficulty in maintenance.
Disclosure of Invention
The invention aims to provide a programming method and a system of an onboard SPI Flash memory, and aims to solve the problems of high maintenance cost and high technical difficulty of maintenance in the prior art.
In a first aspect, the present invention provides a programming method for an onboard SPI Flash memory, the programming method comprising:
the upper computer provided with the J-LINK driver program for driving the EJTAG debugging unit runs the J-LINK driver program, and downloads the system program to the memory chip through the EJTAG debugging interface and the embedded processor;
the upper computer enables the embedded processor to run the system program downloaded into the memory chip through the EJTAG debugging interface, and when data are completely copied to the SPI Flash memory from the memory chip, the programming of the onboard SPI Flash memory is completed.
The invention provides a programming system of an onboard SPI Flash memory, which comprises an embedded processor, an EJTAG debugging interface, a memory chip and an upper computer, wherein the embedded processor comprises an EJTAG debugging unit, a memory controller, an SPI controller and an SRAM which are connected through a bus;
the upper computer provided with the J-LINK driver program for driving the EJTAG debugging unit runs the J-LINK driver program, and downloads the system program to the memory chip through the EJTAG debugging interface and the embedded processor;
the upper computer enables the embedded processor to run the system program downloaded into the memory chip through the EJTAG debugging interface, and when data are completely copied to the SPI Flash memory from the memory chip, the programming of the onboard SPI Flash memory is completed.
In the invention, the upper computer enables the embedded processor to run the system program downloaded into the memory chip through the EJTAG debugging interface, thereby automatically completing the programming of the onboard SPI Flash memory. Therefore, after the SPI Flash memory is fixedly connected to the circuit board, if a program needs to be programmed, the program does not need to be disassembled or fixed sealing glue is removed by hot melting through a professional heating air gun, the programming of the onboard SPI Flash memory can be completed by directly utilizing an EJTAG debugging interface of the embedded processor on the circuit board and controlling the embedded processor from the outside through a J-LINK driving program, and a simple and convenient means is provided for subsequent equipment upgrading and maintenance.
Drawings
Fig. 1 is a schematic diagram of a programming system of an on-board SPI Flash memory according to an embodiment of the present invention.
Fig. 2 is a flowchart of a programming method of an on-board SPI Flash memory according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 1, a programming system of an onboard SPI Flash memory according to an embodiment of the present invention includes an embedded processor 1, an EJTAG debug interface 2, a memory chip 3, and an upper computer 4, where the embedded processor 1 includes an EJTAG (Enhanced Joint Test Action Group) debug unit 11, a memory controller 12, an SPI controller 13, and an SRAM14, the EJTAG debug unit 11 is connected to the EJTAG debug interface 2, the memory controller 12 is connected to the memory chip 3, the EJTAG debug interface 2 is further connected to the upper computer 4, the SPI controller 13 is connected to the SPI Flash memory welded to an integrated circuit board, and a J-LINK driver for driving the EJTAG debug unit is installed in the upper computer 4.
The memory chip 3 may be a DDR (Double Data Rate) memory chip, such as a DDR1 memory chip, a DDR2 memory chip, a DDR3 memory chip, and the like. The J-LINK driver can be any version of J-LINK driver, such as a J-LINK V4.90 driver, a J-LINK V6.20 driver, and the like.
The programming method of the onboard SPI Flash memory provided by the embodiment of the invention comprises the following steps:
s101, an upper computer provided with a J-LINK driver program for driving an EJTAG debugging unit runs the J-LINK driver program, and downloads a system program to a memory chip through an EJTAG debugging interface and an embedded processor;
s102, enabling the embedded processor to run the system program downloaded into the memory chip by the upper computer through the EJTAG debugging interface, and completing the programming of the onboard SPIFlash memory when data is completely copied to the SPI Flash memory from the memory chip.
In the embodiment of the present invention, S101 may specifically include the following steps:
s1011, the upper computer provided with the J-LINK driver for driving the EJTAG debugging unit runs the J-LINK driver, and resets the embedded processor through the EJTAG debugging interface;
s1012, the upper computer hangs up the embedded processor through an EJTAG debugging interface;
s1013, the upper computer downloads a system boot program to an SRAM (Static Random-Access Memory) of the embedded processor through the EJTAG debugging interface; the system boot program can be stored from the SRAM initial address;
s1014, setting a PC pointer of the embedded processor by the upper computer through an EJTAG debugging interface; the method specifically comprises the following steps: the upper computer sets a PC pointer of the embedded processor as an SRAM starting address through an EJTAG debugging interface;
s1015, enabling the embedded processor to run the system boot program downloaded to the SRAM through the EJTAG debugging interface by the upper computer;
s1016, after the system boot program runs, the upper computer hangs up the embedded processor through an EJTAG debugging interface;
s1017, setting the embedded processor to be in an ARM running state by the upper computer through an EJTAG debugging interface; specifically, the state of an embedded processor is set by an upper computer through an EJTAG debugging interface and is changed from a THUMB state to an ARM running state; in the ARM architecture, the system can work in three different states, namely an ARM state, a Thumb-2 state and a debugging state.
S1018, downloading a system program to the memory chip by the upper computer through the EJTAG debugging interface and the embedded processor; specifically, the system program may be stored from a start address of the memory chip.
In the embodiment of the present invention, S102 may specifically include the following steps:
s1021, the upper computer sets a J-LINK system upgrading identifier in the SRAM of the embedded processor through an EJTAG debugging interface; specifically, the spare address after 4K in the SRAM writes "spidrite" (0x 530 x 500 x 490 x 570 x 520 x 490 x 540 x45) as the system upgrade flag;
s1022, the upper computer sets a PC pointer of the embedded processor through an EJTAG debugging interface; the method specifically comprises the following steps: the upper computer sets a PC pointer of the embedded processor as a memory starting address through an EJTAG debugging interface;
s1023, the upper computer sets a system program operation breakpoint through an EJTAG debugging interface; the method specifically comprises the following steps: the upper computer sets a system program operation breakpoint in front of the SPI Flash memory by copying data in the memory chip through an EJTAG debugging interface;
s1024, enabling the embedded processor to run the system program downloaded into the memory chip by the upper computer through the EJTAG debugging interface;
s1025, after the system program runs to a breakpoint, the upper computer hangs up the embedded processor through an EJTAG debugging interface;
s1026, the upper computer downloads a system program containing a system program information frame header into the memory chip through an EJTAG debugging interface; the method specifically comprises the following steps: the upper computer downloads the system program containing the system program information frame header to the memory chip through the EJTAG debugging interface again to automatically upgrade the initial copy address, and the difference between the system program downloaded to the memory chip at this time and the system program downloaded to the memory chip in S1018 is only that the system program information frame header is added;
s1027, enabling the embedded processor to continue to run the system program in the memory chip by the upper computer through an EJTAG debugging interface, enabling the system to enter an automatic upgrading state at the moment, and copying data from the memory chip to the SPIFlash memory; the method specifically comprises the following steps: the memory controller controls the processing data to start copying data from the initial copy address of the memory chip for automatic upgrading and writes the data into the SPI Flash memory through the SPI controller;
s1028, when the data are completely copied to the SPI Flash memory from the initial copy address of the automatic upgrading of the memory chip, the programming of the onboard SPI Flash memory is completed.
In the invention, the upper computer enables the embedded processor to run the system program downloaded into the memory chip through the EJTAG debugging interface, thereby automatically completing the programming of the onboard SPI Flash memory. Therefore, after the SPI Flash memory is fixedly connected to the circuit board, if a program needs to be programmed, the program does not need to be detached or fixed sealing glue is removed by hot melting through a professional heating air gun, the programming of the onboard SPI Flash memory can be completed by directly utilizing an EJTAG debugging interface of the embedded processor on the circuit board and controlling the embedded processor from the outside through a J-LINK driving program, and a simple and convenient means is provided for subsequent equipment upgrading and maintenance.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable storage medium, and the storage medium may include: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A programming method of an on-board SPI Flash memory is characterized by comprising the following steps:
the upper computer provided with the J-LINK driver program for driving the EJTAG debugging unit runs the J-LINK driver program, and downloads the system program to the memory chip through the EJTAG debugging interface and the embedded processor;
the upper computer sets a J-LINK system upgrading identification in the SRAM of the embedded processor through an EJTAG debugging interface;
the upper computer sets an embedded processor PC pointer through an EJTAG debugging interface;
the upper computer sets a system program operation breakpoint through an EJTAG debugging interface;
enabling the embedded processor to run a system program downloaded into the memory chip by the upper computer through an EJTAG debugging interface;
after the system program runs to a breakpoint, the upper computer hangs up the embedded processor through an EJTAG debugging interface;
the upper computer downloads a system program containing a system program information frame header into the memory chip through an EJTAG debugging interface;
enabling the embedded processor to continue operating the system program in the memory chip by the upper computer through the EJTAG debugging interface, enabling the system to enter an automatic upgrading state at the moment, and copying data from the memory chip to the SPI Flash memory;
and when the data is completely copied to the SPI Flash memory from the initial copy address of the automatic upgrading of the memory chip, the programming of the onboard SPI Flash memory is finished.
2. The programming method of claim 1, wherein the running of the J-LINK driver by the upper computer having the J-LINK driver installed therein for driving the EJTAG debug unit, the downloading of the system program to the memory chip via the EJTAG debug interface and the embedded processor specifically comprises:
the upper computer provided with the J-LINK driver program for driving the EJTAG debugging unit runs the J-LINK driver program, and resets the embedded processor through the EJTAG debugging interface;
the upper computer suspends the embedded processor through an EJTAG debugging interface;
the upper computer downloads a system bootstrap program to an SRAM of the embedded processor through an EJTAG debugging interface;
the upper computer sets a PC pointer of the embedded processor through an EJTAG debugging interface;
enabling the embedded processor to run a system boot program downloaded into the SRAM by the upper computer through an EJTAG debugging interface;
after the system boot program runs, the upper computer hangs up the embedded processor through the EJTAG debugging interface;
the upper computer sets the embedded processor to be in an ARM running state through an EJTAG debugging interface;
and the upper computer downloads the system program to the memory chip through the EJTAG debugging interface and the embedded processor.
3. The programming method of claim 2, wherein the host computer downloads the system boot program into the SRAM of the embedded processor through the EJTAG debug interface, and in particular stores the system boot program starting from the SRAM start address.
4. The programming method of claim 2, wherein the setting, by the upper computer through the EJTAG debug interface, of the PC pointer of the embedded processor is specifically: and the upper computer sets a PC pointer of the embedded processor as an SRAM starting address through an EJTAG debugging interface.
5. The programming method of claim 2, wherein the host computer sets the embedded processor to the ARM operating state through the EJTAG debug interface, and in particular, the host computer sets the state of the embedded processor through the EJTAG debug interface to change the state of the embedded processor from the THUMB state to the ARM operating state.
6. The programming method of claim 2, wherein the host computer downloads the system program into the memory chip through the EJTAG debug interface and the embedded processor, and stores the system program from a start address of the memory chip.
7. The programming method of claim 1, wherein the setting of the PC pointer of the embedded processor by the upper computer through the EJTAG debug interface is specifically: the upper computer sets a PC pointer of the embedded processor as a memory starting address through an EJTAG debugging interface.
8. The programming method of claim 1, wherein the setting of the system program running breakpoint by the upper computer through the EJTAG debug interface is specifically: and the upper computer sets the system program operation breakpoint in front of the SPI Flash memory by copying the data in the memory chip through the EJTAG debugging interface.
9. A programming system of an onboard SPI Flash memory is characterized by comprising an embedded processor, an EJTAG debugging interface, a memory chip and an upper computer, wherein the embedded processor comprises an EJTAG debugging unit, a memory controller, an SPI controller and an SRAM which are connected through a bus;
the upper computer provided with the J-LINK driver program for driving the EJTAG debugging unit runs the J-LINK driver program, and downloads the system program to the memory chip through the EJTAG debugging interface and the embedded processor;
the upper computer sets a J-LINK system upgrading identification in the SRAM of the embedded processor through an EJTAG debugging interface;
the upper computer sets an embedded processor PC pointer through an EJTAG debugging interface;
the upper computer sets a system program operation breakpoint through an EJTAG debugging interface;
enabling the embedded processor to run a system program downloaded into the memory chip by the upper computer through an EJTAG debugging interface;
after the system program runs to a breakpoint, the upper computer hangs up the embedded processor through an EJTAG debugging interface;
the upper computer downloads a system program containing a system program information frame header into the memory chip through an EJTAG debugging interface;
enabling the embedded processor to continue operating the system program in the memory chip by the upper computer through the EJTAG debugging interface, enabling the system to enter an automatic upgrading state at the moment, and copying data from the memory chip to the SPI Flash memory;
and when the data is completely copied to the SPI Flash memory from the initial copy address of the automatic upgrading of the memory chip, the programming of the onboard SPI Flash memory is finished.
10. The write system of claim 9, wherein the memory chip is a DDR memory chip.
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| CN201811571474.6A CN109710277B (en) | 2018-12-21 | 2018-12-21 | Burning method and system for onboard SPI Flash memory |
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| CN116594700B (en) * | 2023-07-17 | 2023-12-12 | 合肥康芯威存储技术有限公司 | Method and device for cloning eMMC chip, electronic equipment and storage medium |
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