CN109698183A - A kind of manufacturing method, the electronic device of semiconductor devices and semiconductor devices - Google Patents
A kind of manufacturing method, the electronic device of semiconductor devices and semiconductor devices Download PDFInfo
- Publication number
- CN109698183A CN109698183A CN201710994881.7A CN201710994881A CN109698183A CN 109698183 A CN109698183 A CN 109698183A CN 201710994881 A CN201710994881 A CN 201710994881A CN 109698183 A CN109698183 A CN 109698183A
- Authority
- CN
- China
- Prior art keywords
- metal layer
- layer
- pad
- opening
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 378
- 229910052751 metal Inorganic materials 0.000 claims abstract description 219
- 239000002184 metal Substances 0.000 claims abstract description 219
- 238000002161 passivation Methods 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000011229 interlayer Substances 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000011469 building brick Substances 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 31
- 239000000463 material Substances 0.000 description 21
- 238000002955 isolation Methods 0.000 description 12
- 239000012212 insulator Substances 0.000 description 10
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- -1 SiGe Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 241000755093 Gaidropsarus vulgaris Species 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides manufacturing method, the electronic device of a kind of semiconductor devices and semiconductor devices, and the semiconductor devices includes: semiconductor substrate；Secondary metal layer at top and metal layer at top in the semiconductor substrate；Interlayer dielectric layer between the secondary metal layer at top and metal layer at top is formed with conductive through hole in the interlayer dielectric layer, to be electrically connected the secondary metal layer at top and metal layer at top；Pad on the metal layer at top；And the passivation layer of the covering pad, the passivation layer have the opening of pad described in exposed portion；Wherein, the conductive through hole is formed in the region other than the opening vertical lower.The manufacturing method of semiconductor device according to the invention and semiconductor devices reduces the semiconductor devices risk that pad and metal layer at top are peeled off in bonding process, increases the stability of pad structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to the manufacture of a kind of semiconductor devices and semiconductor devices
Method, electronic device.
Background technique
The encapsulation of semiconductor chip connects a chip to chip package by forming the pad of circuit conducting on chip
External original part.Currently, semiconductor field mostly uses wire bonding to lead the pad being connected with metal layer at top with external circuit
It is logical.In lead key closing process, through-hole array positioned at metal layer at top bottom is generallyd use by metal layer at top and time top
Metal layer is connected, and the interconnection layer of one side metal layer at top and lower part is electrically connected, on the other hand to anchor pad.
However, pad is located at metal layer at top and time top under the action of lead strain during lead key closing process
Tend to occur be broken at the tie point between through-hole array and the secondary metal layer at top between portion's metal layer, cause pad and
The deformation of top-level metallic falls off.
For this purpose, the present invention provides the manufacturing method of a kind of semiconductor devices and semiconductor devices, to solve existing skill
The problems in art.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention provides a kind of semiconductor devices, comprising:
Semiconductor substrate；
Secondary metal layer at top and metal layer at top in the semiconductor substrate；
Interlayer dielectric layer between the secondary metal layer at top and metal layer at top is formed in the interlayer dielectric layer
There is conductive through hole, to be electrically connected the secondary metal layer at top and metal layer at top；
Pad on the metal layer at top；And
The passivation layer of the pad is covered, the passivation layer has the opening of pad described in exposed portion；
Wherein, the conductive through hole is formed in the region other than the opening vertical lower, to be electrically connected described top
Portion's metal layer and metal layer at top.
Illustratively, the interlayer dielectric layer is silicon dioxide layer.
Illustratively, the secondary metal layer at top and the metal layer at top are plate structure.
Illustratively, the secondary metal layer at top and the metal layer at top are located at the vertical lower of the pad, described
The projection of opening in vertical direction is located in the metal layer at top and the secondary metal layer at top.
Illustratively, the conductive through hole is formed in the surrounding in the opening upright projection region.
It illustratively, further include another passivation layer between the passivation layer and metal layer at top, it is described another blunt
Change another opening that layer has metal layer at top described in exposed portion, the pad fills another opening and part covers
Another passivation layer.
The present invention also provides a kind of manufacturing methods of semiconductor devices, comprising:
Semiconductor substrate is provided, forms time metal layer at top on the semiconductor substrate；
Interlayer dielectric layer is formed on the semiconductor substrate, and the interlayer dielectric layer covers the secondary metal layer at top；
Conductive through hole is formed in the interlayer dielectric layer；
Metal layer at top is formed on the interlayer dielectric layer；
Form pad on the semiconductor substrate, the pad be located at the top of the metal layer at top and with the top
The electrical connection of portion's metal layer；
Passivation layer is formed on the semiconductor substrate, and the passivation layer has the opening of pad described in exposed portion；
Wherein, the conductive through hole is formed in the region other than the opening vertical lower, to be electrically connected described top
Portion's metal layer and metal layer at top.
Illustratively, on the semiconductor substrate formed pad the step of include:
Another passivation layer for covering the metal layer at top, another passivation layer tool are formed on the semiconductor substrate
There is another opening of metal layer at top described in exposed portion；
Pad is formed on the semiconductor substrate, and the pad is filled another opening and partially covered described another
Passivation layer.
Illustratively, the interlayer dielectric layer is silicon dioxide layer.
Illustratively, the secondary metal layer at top and the metal layer at top are plate structure.
Illustratively, the secondary metal layer at top and the metal layer at top are located at the vertical lower of the pad, described
The projection of opening in vertical direction is located in the secondary metal layer at top.
Illustratively, the conductive through hole is formed in the surrounding in the opening upright projection region.
The present invention also provides a kind of electronic device, including semiconductor devices as described above and with the semiconductor device
The electronic building brick that part is connected
The manufacturing method of semiconductor device according to the invention and semiconductor devices, by being arranged conductive through hole in exposure
Region other than the opening upright projection of pad so that be located at top layer metallic layer bottom, be open view field conductive through hole by
Dielectric layer material is replaced, to absorb the stress in bonding process in wire bonding process dielectric layer material, reduces key
The stress being transmitted in time metal layer at top during closing peels off to reduce pad and time metal layer at top in bonding process
Risk, increase the stability of pad structure.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A shows a kind of schematic cross sectional views of current pad structure；
Figure 1B shows the perspective view of top through-hole and opening in metal layer at top in pad structure shown in Figure 1A；
Fig. 2A shows the schematic cross sectional views of pad structure according to an embodiment of the present invention；
Fig. 2 B shows the perspective view of conductive through hole and opening in metal layer at top in pad structure shown in Fig. 2A；
Fig. 3 shows the step flow chart of the production method of semiconductor devices according to an embodiment of the present invention；
Fig. 4 shows the structural schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, it is of the present invention to illustrate
The manufacturing method of semiconductor devices and semiconductor devices.Obviously, execution of the invention is not limited to the technology people of semiconductor field
The specific details that member is familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiments.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singular
It is intended to include plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or their combination.
During lead key closing process, pad metal is under the action of lead strain, the through-hole array and described time
It tends to occur be broken at tie point between metal layer at top, cause the deformation of pad and top-level metallic or falls off.A kind of typical case
Pad (pad) design be double solid panels (TM, TM-1) designs and copper wire bonding.Illustratively, as shown in FIG. 1A and 1B,
This semiconductor devices includes semiconductor substrate 100, is formed with device layer (not shown) in the semiconductor substrate 100；It is formed
The formation being electrically connected between device layer time metal layer at top 101 and metal layer at top 103 on a semiconductor substrate 100；It is secondary
It is also formed with interlayer dielectric layer 102 between metal layer at top 101 and metal layer at top 103, is formed with and leads in interlayer dielectric layer 102
Electric through-hole 107, conductive through hole 107 is secondary metal layer at top 101 and metal layer at top 103 to be electrically connected.Secondary top-gold
Belonging to layer 101 and metal layer at top 103 is solid plate structure, and metal layer at top 103 as shown in fig. 1b can be square
The various suitable shapes such as shape, circle, hexagon.The area ratio pad 105 of secondary metal layer at top 101 and metal layer at top 103
Area it is big.The first passivation layer 104 of covering metal layer at top 103 is formed in metal layer at top, in the first passivation layer 104
It is formed with the quasi- opening for forming welding disking area of exposure, pad 105 is formed in said opening and 104 surface of the first passivation layer is leaned on
On the part of the nearly opening, the second passivation layer 106, shape in the second passivation layer 106 are formed on first passivation layer 104
At the opening 108 for having the exposure pad 105.
However, this pad structure time metal layer at top 101 and the conductive through hole that is formed among interlayer dielectric layer 102
Adhesion strength (namely adhesion strength between secondary metal layer at top (TM-1) and conductive through hole) between 107 is more fragile, subsequent
Since stress is subject to the risk of pad peeling, i.e. 108 upright projection of Figure 1A split shed in package lead bonding process
It splits between the secondary metal layer at top 101 and conductive through hole 107 in region (as shown in dotted line in Figure 1A), so that the top-gold of top
Belong to layer 103 and pad 105 peels off or deformation.
The technical issues of in order to solve in the prior art, the present invention provides a kind of semiconductor devices, comprising:
Semiconductor substrate；
Secondary metal layer at top and metal layer at top in the semiconductor substrate；
Interlayer dielectric layer between the secondary metal layer at top and metal layer at top is formed in the interlayer dielectric layer
There is conductive through hole；
Pad on the metal layer at top；And
The passivation layer of the pad is covered, the passivation layer has the opening of pad described in exposed portion；
Wherein, the conductive through hole is formed in the region other than the opening vertical lower, to be electrically connected described top
Portion's metal layer and metal layer at top.
The manufacturing method of semiconductor device according to the invention and semiconductor devices, by being arranged conductive through hole in exposure
Region other than the opening upright projection of pad so that be located at top layer metallic layer bottom, be open view field conductive through hole by
Dielectric layer material is replaced, to absorb the stress in bonding process in wire bonding process dielectric layer material, reduces key
The stress being transmitted to during closing in time metal layer at top, to reduce the wind that time metal layer at top is peeled off in bonding process
Danger, increases the stability of pad structure.
Referring now to Fig. 2A -2B, a kind of semiconductor devices proposed of the invention is illustrated, Fig. 2A shows
The schematic cross sectional views of pad structure according to an embodiment of the present invention are gone out；Fig. 2 B shows pad structure shown in Fig. 2A
The perspective view of middle conductive through hole and opening in metal layer at top.
Referring initially to Fig. 2A, semiconductor devices includes: semiconductor substrate 200, and the semiconductor substrate 200 can be by not
The wafers such as the monocrystalline silicon of doping, the monocrystalline silicon mixed with impurity, silicon-on-insulator (SOI) are formed by semiconductor technology with multiple
The wafer in device function area.The conductive tie layers of device function area electrical connection are formed in semiconductor substrate 200, the conduction is even
Connecing layer includes time metal layer at top (TM-1) 201 and metal layer at top (TM) 203, the secondary metal layer at top and metal layer at top
It can be the metal of any electric action, illustratively, using Al or Cu etc..
The semiconductor devices further includes the layer being formed between the secondary metal layer at top 201 and metal layer at top 203
Between dielectric layer 202, the conductive through hole 207 of the interlayer dielectric layer 202 is formed through in the interlayer dielectric layer 202, to
It is electrically connected the secondary metal layer at top 201 and the metal layer at top 203.
The semiconductor devices further includes the first passivation layer 204 being formed in metal layer at top 203, first passivation
The first opening 208 is formed in layer 204.First layer of passivation material can be the material of any dielectric isolation, such as aoxidize
Silicon, silicon nitride etc..First aperture 208 is to fill bonding pad material to form pad.
The semiconductor devices further includes pad 205, and the pad 205 is filled in first opening 208 and partially covered
Cover first passivation layer 204.The pad can be pad metal material layer commonly used in the art, such as aluminium or the common gold of copper
Belong to.The pad 205 fills in first opening 208 and partially covers first passivation layer 204, so that pad 205 wraps
Include the main part being located in first opening 208 and the extension positioned at 204 surface of the first passivation layer, the main part
It is connected to each other with the extension.The main part being located in first opening is set by pad and is located at first passivation
The structure of the extension of layer surface is the stability in order to guarantee the pad structure in bonding process.
The semiconductor devices further includes the second passivation layer 206, and second passivation layer 206 is formed in first passivation
On layer 204, and there is the second opening 209 of the exposure pad 205.Second passivation layer can use various suitable media
Material, such as oxide, nitride or nitrogen oxides etc..
It is to be appreciated that the present invention is that signal is illustrated pad structure with the first passivation layer, pad, the second passivation layer
Film layer form be only exemplary, it is any formed pad structure film layer form, such as only comprising pad and part covering weldering
The passivation layer of disk and the opening with exposed portion pad is suitable for the present invention.
Wherein, conductive through hole 207 is located at the region other than second opening, 209 vertical lowers.In secondary metal layer at top
Setting is located at the interlayer without conductivity through-hole structure in the upright projection region of exposure bonding pad opening between metal layer at top
(region other than the vertical lower of the second opening is arranged in) in conductive through hole by dielectric layer, so that wire bonding process intermediary
Matter layer material absorbs the stress in bonding process, reduces bonding and is transmitted in time metal layer at top last time metal layer at top in the process
Stress increase the stability of pad structure to reduce in bonding process the risk that time metal layer at top is peeled off.It is described
Interlayer dielectric layer can be any layer of dielectric material for playing dielectric isolation.Illustratively, the interlayer dielectric layer is dioxy
SiClx layer.Silica is set by interlayer dielectric layer, the metal material used relative to secondary metal layer at top and metal layer at top
Material, such as copper have bigger hardness, so that the absorption of tensile stress is imitated during bonding process intermediary conductive film para-linkage
Fruit is bigger, is further reduced stress transfer to secondary metal layer at top (secondary metal layer at top), further increases the stability of pad.
Illustratively, the secondary metal layer at top and the metal layer at top are plate structure.As shown in Figure 2 B, secondary top
Metal layer 201 and metal layer at top 203 are disposed as plate structure, so that pad and metal layer at top have biggish contact surface
Product, secondary metal layer at top play a supporting role to metal layer at top and pad, enhance the stability of pad structure.
Illustratively, the secondary metal layer at top and the metal layer at top are located at the vertical lower of the pad, described
The projection of opening in vertical direction is located in the metal layer at top and the secondary metal layer at top.As shown in Figure 2 A and 2B,
The secondary metal layer at top 201 and the metal layer at top 203 are located at the vertical lower of the pad 205, the secondary top-gold
Belong to layer 201 and metal layer at top 203 is formed in the area (i.e. surface area or the projected area in horizontal plane) of metal layer at top 203
Greater than the area of pad 205, as shown in Figure 2 B, the projection of the opening 209 in vertical direction is located at 203 He of metal layer at top
In secondary metal layer at top 201.To which the conductive through hole 207 may be formed at the four of the vertical lower region of the pad 205
Week, i.e., as shown in Figure 2 B, the second 209 vertical lower regions of opening form conductive through hole 207 from rear.Conductive through hole is arranged
Surrounding in pad vertical lower region, on the one hand can be in the case where not changing existing double solid dish structures (as shown in FIG. 1A and 1B)
On the other hand the electric conductivity and stability of pad structure only pass through logical operation tool (such as in pad structure design process
LOTA, Logic operation table application) it can determine standard size and technique, reduce process shifts
Risk.
It is to be appreciated that being shown in the present embodiment with time metal layer at top and metal layer at top are arranged in conductive tie layers
It is only to show that routinely those skilled in the art, which can according to need, to be selected, under secondary metal layer at top that example, which is illustrated,
One or more layers conductive tie layers for having electrical connection properties is arranged in side or other regions.Simultaneously it is to be appreciated that this implementation
Secondary metal layer at top and metal layer at top are designed to that the region positioned at pad vertical lower is only exemplary in example, it is any
It will be designed to medium isolation between secondary metal layer at top and metal layer at top and the formation of conductive through hole connection is replaced to be suitable for
The present invention.
Also, it is understood that only showing the shape and structure of pad corresponding region in Fig. 2A and Fig. 2 B.In addition, top
Between portion's metal layer and secondary metal layer at top and between secondary metal layer at top, metal layer at top and other interconnection lines, top is logical
It is isolated between hole by dielectric layer, that is, be isolated between the secondary metal layer at top and the metal layer at top by dielectric layer, institute
It states top through-hole and passes through the dielectric layer, the dielectric layer is not shown for brevity in figure.
The manufacturing method of semiconductor device according to the invention and semiconductor devices, by being arranged conductive through hole in exposure
Region other than the opening upright projection of pad so that be located at top layer metallic layer bottom, be open view field conductive through hole by
Dielectric layer material is replaced, to absorb the stress in bonding process in wire bonding process dielectric layer material, reduces key
The stress being transmitted in time metal layer at top during closing peels off to reduce pad and time metal layer at top in bonding process
Risk, increase the stability of pad structure.
The present invention also provides a kind of manufacturing methods of semiconductor devices, below by the system to semiconductor devices of the invention
The method of making is further described.
Firstly, providing semiconductor substrate, time metal layer at top is formed on the semiconductor substrate.
Semiconductor substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC, SiGeC,
Perhaps other III/V compound semiconductors further include multilayered structure that these semiconductors are constituted etc. or are by InAs, GaAs, InP
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator are laminated on insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Could be formed with device in semiconductor substrate, for example, NMOS and/or
PMOS etc..Equally, conductive member can also be formed in semiconductor substrate, conductive member can be the grid of transistor, source electrode
Or drain electrode, it is also possible to the metal interconnection structure, etc. being electrically connected with transistor.In addition, in the semiconductor substrate can be with shape
At there is isolation structure, the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
As an example, in the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
Being formed on the semiconductor substrate includes time metal layer at top conductive interconnection layer.Shape on the semiconductor substrate
It can be made by interconnection structure forming method commonly used in the art at the method for the conductive interconnection layer comprising secondary metal layer at top,
Such as big cordovan scholar method or double big cordovan scholar methods are formed.The secondary metal layer at top illustratively uses copper to make.It needs to manage
It solves, is selected in the present embodiment in the forming process in conductive tie layers, those skilled in the art be can according to need
It selects, below secondary metal layer at top or one or more layers conductive tie layers for having electrical connection properties is arranged in other regions.
Then, interlayer dielectric layer is formed on the semiconductor substrate, forms conductive through hole in the interlayer dielectric layer.
Metallic copper is illustratively filled in the top through-hole.The interlayer dielectric layer can be any Jie for playing dielectric isolation
The material bed of material.Illustratively, the interlayer dielectric layer is silicon dioxide layer.Silica is set by interlayer dielectric layer, relatively
In the metal material that secondary metal layer at top and metal layer at top use, such as copper, there is bigger hardness, so that being bonded
The assimilation effect of tensile stress is bigger during Cheng Zhongjie conductive film para-linkage, is further reduced stress transfer to secondary metal layer at top
(secondary metal layer at top), further increases the stability of pad.The step of conductive through hole is formed in the interlayer dielectric layer can
To be made of interconnection architecture forming method commonly used in the art, such as big cordovan scholar method or double big cordovan scholar methods are formed.Institute
State the vertical lower that conductive through hole is formed in the secondary metal layer at top top, pad exposed region across the interlayer dielectric layer
Region in addition.
Then, metal layer at top is formed on the interlayer dielectric layer.Illustratively, the metal layer at top is located at institute
State the region being located at below the quasi- pad formed in the metal layer at top in semiconductor substrate.The metal layer at top passes through institute
Conductive through hole is stated to be electrically connected with the secondary metal layer at top.Metal layer at top can be formed by interconnection structure commonly used in the art
Method production, such as big cordovan scholar method or double big cordovan scholar methods are formed.The metal layer at top illustratively uses copper to make.
Then, pad is formed on the semiconductor substrate, is electrically connected at the top of the pad and the metal layer at top.Show
Example property, the step of formation pad includes: and is formed to cover the top on the semiconductor substrate on the semiconductor substrate
First passivation layer of portion's metal layer, first passivation layer have the first opening of the part exposure metal layer at top；Institute
It states and forms pad in semiconductor substrate, the pad fills another opening and partially covers first passivation layer.
First passivation layer can be using various suitable dielectric materials, such as oxide, nitride or nitrogen oxides etc..Show
Example property, in the present embodiment, the first passivation layer uses silica.First passivation layer can by PVD (physical vapour deposition (PVD)),
CVD (chemical vapor deposition), ALD (atomic layer deposition) etc., and after having deposited the first passivation layer, pass through chemical wet etching etc.
Patterning process forms the first opening of exposed lower metal layer, so that the pad being subsequently formed is electrically connected with lower metal layer.
Pad can be made by method commonly used in the art, illustratively, formed pad the step of include:
Form the metal layer that filling described first was open and covered first passivation layer；The graphical metal layer is with shape
At pad.
Metal layer can be with common metals such as aluminium or copper, and are formed by the methods of sputtering, PVD, CVD.Illustratively, at this
In embodiment, metal layer uses aluminium.
Illustratively, the pad fills the described first metal layer for being open and covering first passivation layer, thus shape
At the pad include positioned at it is described first opening in main part and positioned at the extension of first passivation layer surface.Gold
Belong to graphically completing by photoetching commonly used in the art, etching technics for layer, details are not described herein.By outside pad main part
Week setting extension can increase the binding ability of pad.The main part being located in first opening and position are set by pad
In the stability that the structure of the extension of first passivation layer surface is to guarantee the pad structure in bonding process.
Then, the second passivation layer is formed on the semiconductor substrate, and second passivation layer has the exposure pad
Second opening.
Second passivation layer can be using various suitable dielectric materials, such as oxide, nitride or nitrogen oxides etc..
Illustratively, in the present embodiment, the second passivation layer uses silica.Second passivation layer can pass through PVD (physics
Vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition) etc. pass through and after having deposited the second passivation layer
The patterning process such as chemical wet etching form the second opening of exposed pad ontology, so as to subsequent encapsulation.
Illustratively, the secondary metal layer at top and the metal layer at top are plate structure.As shown in Figure 2 A and 2 B,
Secondary metal layer at top 201 and metal layer at top 203 are disposed as plate structure, so that pad has biggish connect with metal layer at top
Contacting surface product, secondary metal layer at top play a supporting role to metal layer at top and pad, enhance the stability of pad structure.
Illustratively, the secondary metal layer at top and the metal layer at top are located at the vertical lower of the pad, exposure
The projection of the opening of the pad in vertical direction is located in the metal layer at top and the secondary metal layer at top.Such as Fig. 2A
With shown in 2B, the secondary metal layer at top 201 and the metal layer at top 203 are located at the vertical lower of the pad 205, described
Secondary metal layer at top 201 and metal layer at top 203 are formed in area (the i.e. surface area or in horizontal plane of metal layer at top 203
Projected area) it is greater than the area of pad 205, as shown in Figure 2 B, the projection of the opening 209 in vertical direction is located at top-gold
Belong on layer 203 and time metal layer at top 201.To incite somebody to action during forming interlayer dielectric layer 202 and conductive through hole 207
The conductive through hole 207 is formed in the surrounding in the vertical lower region of the pad 205, i.e., as shown in Figure 2 B, the second opening
209 vertical lower regions form conductive through hole 207 from rear.Conductive through hole is arranged in the surrounding in pad vertical lower region,
On the one hand can in the case where not changing existing double solid dish structures (as shown in FIG. 1A and 1B) pad structure electric conductivity and stabilization
Property, standard size and technique only on the other hand can determine by logic in pad structure design process, only removal exposure weldering
Conductive through hole corresponding to below the opening of disk, is replaced using dielectric layer material, and is located at the top except the opening of exposure pad
Portion's through-hole still uses the standard size of technique and design determination, can reduce process risk in this way, improves yield of devices.This
Outside, the design and change of more new process can pass through logical operation tool (such as LOTA, Logic operation table
Application it) determines, it is simple and convenient.
Fig. 3 shows the schematic flow chart of the manufacturing method of semiconductor device according to the invention, specifically include with
Lower step:
Step S1: providing semiconductor substrate, forms time metal layer at top on the semiconductor substrate；
Step S2: forming interlayer dielectric layer on the semiconductor substrate, is formed in the interlayer dielectric layer conductive logical
Hole；
Step S3: metal layer at top is formed on the interlayer dielectric layer；
Step S4: forming pad on the semiconductor substrate, forms pad, the pad on the semiconductor substrate
Positioned at the metal layer at top top and be electrically connected with the metal layer at top；
Step S5: forming passivation layer on the semiconductor substrate, and the passivation layer has pad described in exposed portion
Opening.
The manufacturing method of semiconductor device according to the invention and semiconductor devices, by being arranged conductive through hole in exposure
Region other than the opening upright projection of pad so that be located at top layer metallic layer bottom, be open view field conductive through hole by
Dielectric layer material is replaced, to absorb the stress in bonding process in wire bonding process dielectric layer material, reduces key
The stress being transmitted in time metal layer at top during closing peels off to reduce pad and time metal layer at top in bonding process
Risk, increase the stability of pad structure.
Of the invention also provides a kind of electronic device, including semiconductor devices and the electricity being connected with the semiconductor devices
Sub-component.Wherein, which includes semiconductor substrate；Secondary metal layer at top and top in the semiconductor substrate
Portion's metal layer；Interlayer dielectric layer between the secondary metal layer at top and metal layer at top, shape in the interlayer dielectric layer
At there is conductive through hole；Pad on the metal layer at top；And the passivation layer of the covering pad, the passivation layer
Opening with pad described in exposed portion；Wherein, the conductive through hole is formed in the region other than the opening vertical lower,
To be electrically connected the secondary metal layer at top and metal layer at top.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.In addition, may be used also in the semiconductor substrate
To be formed with isolation structure, the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure.As an example, in the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.
Wherein, Fig. 4 shows the example of mobile phone.The outside of mobile phone 400 is provided with including the display portion in shell 401
402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
The electronic device of the embodiment of the present invention is transmitted to during can reducing bonding by the semiconductor devices for being included
Stress in secondary metal layer at top last time metal layer at top, to reduce the wind that time metal layer at top is peeled off in bonding process
Danger, thus the electronic device equally have the advantages that it is similar.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Secondary metal layer at top and metal layer at top in the semiconductor substrate；
Interlayer dielectric layer between the secondary metal layer at top and metal layer at top is formed in the interlayer dielectric layer and leads
Electric through-hole, to be electrically connected the secondary metal layer at top and metal layer at top；
Pad on the metal layer at top；And
The passivation layer of the pad is covered, the passivation layer has the opening of pad described in exposed portion；
Wherein, the conductive through hole is formed in the region other than the opening vertical lower.
2. semiconductor devices according to claim 1, which is characterized in that the interlayer dielectric layer is silicon dioxide layer.
3. semiconductor devices according to claim 1, which is characterized in that the secondary metal layer at top and the top metal
Layer is plate structure.
4. semiconductor devices according to claim 3, which is characterized in that the secondary metal layer at top and the top metal
Layer is located at the vertical lower of the pad, and the projection of the opening in vertical direction is located at the metal layer at top and described time
In metal layer at top.
5. semiconductor devices according to claim 4, which is characterized in that the conductive through hole is formed in hanging down for the opening
The surrounding of straight view field.
6. semiconductor devices according to claim 1, which is characterized in that further include being located at the passivation layer and top metal
Another passivation layer between layer, another passivation layer have another opening of metal layer at top described in exposed portion, the weldering
Disk filling another opening and part cover another passivation layer.
7. a kind of manufacturing method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, forms time metal layer at top on the semiconductor substrate；
Interlayer dielectric layer is formed on the semiconductor substrate, and the interlayer dielectric layer covers the secondary metal layer at top；
Conductive through hole is formed in the interlayer dielectric layer；
Metal layer at top is formed on the interlayer dielectric layer；
Form pad on the semiconductor substrate, the pad be located at the top of the metal layer at top and with the top-gold
Belong to layer electrical connection；
Passivation layer is formed on the semiconductor substrate, and the passivation layer has the opening of pad described in exposed portion；
Wherein, the conductive through hole is formed in the region other than the opening vertical lower, to be electrically connected the secondary top-gold
Belong to layer and metal layer at top.
8. the method according to the description of claim 7 is characterized in that the step of forming pad on the semiconductor substrate is wrapped
It includes:
Another passivation layer for covering the metal layer at top is formed on the semiconductor substrate, and another passivation layer has dew
Another opening of the part metal layer at top out；
Pad is formed on the semiconductor substrate, and the pad fills another opening and partially covers another passivation
Layer.
9. the method according to the description of claim 7 is characterized in that the interlayer dielectric layer is silicon dioxide layer.
10. the method according to the description of claim 7 is characterized in that the secondary metal layer at top and the metal layer at top are
Plate structure.
11. method according to claim 10, which is characterized in that the secondary metal layer at top and the metal layer at top are located at
The vertical lower of the pad, the projection of the opening in vertical direction are located in the secondary metal layer at top.
12. method according to claim 11, which is characterized in that the conductive through hole is formed in the upright projection of the opening
The surrounding in region.
13. a kind of electronic device, which is characterized in that including the semiconductor devices as described in any one in claim 1-6
And the electronic building brick being connected with the semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710994881.7A CN109698183A (en) | 2017-10-23 | 2017-10-23 | A kind of manufacturing method, the electronic device of semiconductor devices and semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710994881.7A CN109698183A (en) | 2017-10-23 | 2017-10-23 | A kind of manufacturing method, the electronic device of semiconductor devices and semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109698183A true CN109698183A (en) | 2019-04-30 |
Family
ID=66225944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710994881.7A Pending CN109698183A (en) | 2017-10-23 | 2017-10-23 | A kind of manufacturing method, the electronic device of semiconductor devices and semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109698183A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310920A (en) * | 2019-07-03 | 2019-10-08 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and preparation method thereof |
| CN110931373A (en) * | 2019-12-11 | 2020-03-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7385297B1 (en) * | 2005-11-14 | 2008-06-10 | National Semiconductor Corporation | Under-bond pad structures for integrated circuit devices |
| US7632749B1 (en) * | 2004-04-13 | 2009-12-15 | Spansion Llc | Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer |
| US20100283149A1 (en) * | 2009-05-06 | 2010-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of forming a pad structure having enhanced reliability |
| CN103000611A (en) * | 2011-09-18 | 2013-03-27 | 南亚科技股份有限公司 | Bonding pad structure for semiconductor devices |
| CN103311202A (en) * | 2012-03-16 | 2013-09-18 | 台湾积体电路制造股份有限公司 | Wire bonding structures for integrated circuits |
-
2017
- 2017-10-23 CN CN201710994881.7A patent/CN109698183A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7632749B1 (en) * | 2004-04-13 | 2009-12-15 | Spansion Llc | Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer |
| US7385297B1 (en) * | 2005-11-14 | 2008-06-10 | National Semiconductor Corporation | Under-bond pad structures for integrated circuit devices |
| US20100283149A1 (en) * | 2009-05-06 | 2010-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of forming a pad structure having enhanced reliability |
| CN103000611A (en) * | 2011-09-18 | 2013-03-27 | 南亚科技股份有限公司 | Bonding pad structure for semiconductor devices |
| CN103311202A (en) * | 2012-03-16 | 2013-09-18 | 台湾积体电路制造股份有限公司 | Wire bonding structures for integrated circuits |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310920A (en) * | 2019-07-03 | 2019-10-08 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and preparation method thereof |
| CN110931373A (en) * | 2019-12-11 | 2020-03-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
| CN110931373B (en) * | 2019-12-11 | 2021-11-19 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20160141228A1 (en) | Device connection through a buried oxide layer in a silicon on insulator wafer | |
| US9443790B2 (en) | Semiconductor device | |
| CN105280610B (en) | 3DIC interconnection devices and forming method thereof | |
| US8847400B2 (en) | Semiconductor device, method for manufacturing the same, and data processing device | |
| US20100164062A1 (en) | Method of manufacturing through-silicon-via and through-silicon-via structure | |
| US10930619B2 (en) | Multi-wafer bonding structure and bonding method | |
| CN103824867B (en) | The method of electric connection wafer and the semiconductor equipment being manufactured with the method | |
| TWI757140B (en) | Semiconductor package with air gap and manufacturing method thereof | |
| CN110690165B (en) | Chip packaging method and packaging structure | |
| US20140353820A1 (en) | Semiconductor device and method for fabricating the same | |
| CN103137566A (en) | Method for forming an integrated circuit | |
| US20120032339A1 (en) | Integrated circuit structure with through via for heat evacuating | |
| CN109698183A (en) | A kind of manufacturing method, the electronic device of semiconductor devices and semiconductor devices | |
| CN107305840B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN104752322A (en) | Semiconductor device and manufacturing method thereof | |
| CN107919342B (en) | Method for forming redistribution bonding pad, semiconductor device and electronic device | |
| CN103081090A (en) | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods | |
| CN106032264B (en) | A kind of CMEMS devices and preparation method thereof, electronic installation | |
| CN108074823A (en) | A kind of semiconductor devices and preparation method thereof and electronic device | |
| TWI512923B (en) | Interposer and method of manufacture | |
| CN108346618B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN105789436B (en) | A kind of semiconductor devices and its manufacturing method, electronic device | |
| CN109712953A (en) | A kind of manufacturing method and semiconductor devices of semiconductor devices | |
| CN109273429A (en) | Semiconductor device | |
| CN109148401A (en) | A kind of semiconductor devices and preparation method thereof, electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190430 |