CN109698005A - The method for deleting of single gate nonvolatile memory - Google Patents

Abstract

The present invention discloses a kind of method for deleting of single gate nonvolatile memory, this non-voltile memory has single Floating gate structure, when carrying out erasing operation, it is that voltage is applied for drain electrode, and grid does not impose voltage, anti- layer is generated and controlled by drain voltage, to reduce the problem of erasing voltage is with promoting erasing speed, and can prevent over-erasure.

Description

The method for deleting of single gate nonvolatile memory

Technical field

The present invention relates to a kind of non-voltile memory (Non-Volatile Memory), can be used for especially with regard to one kind Oxide layer (oxide) thickness of high pressure manufacturing process is greater than 100 angstromsMemory element erasing single gate nonvolatile memory Method for deleting.

Background technique

Currently, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process technique have become special application integrated circuit (application specific integrated circuit, ASIC common manufacturing method).In today of computerized information product prosperity, the erasable programmable read-only memory of electronic type (Electrically Erasable Programmable Read Only Memory, EEPROM) is due to having electrical volume The non-voltile memory function of data is write and wipes, and data will not disappear after power supply is turned off, so being widely used in electricity On sub- product.

Non-voltile memory is programmable, changes the grid voltage of the transistor of memory to store charge, Or charge is not stored to leave the grid voltage of the transistor of former memory.Erasing operation is then that will be stored in non-voltile memory All charges remove so that all non-voltile memories return to the grid voltage of the transistor of former memory.Therefore, known non- It in the structure of volatile memory, other than the grid layer of transistor, need to increase by a conductive layer additionally separately to store charge, and be formed Bigrid (double-layer) structure then has more film deposition, etching and exposure development than general CMOS processing procedure on processing procedure And etc. so that increased costs, processing procedure are complicated, component yield decline, working hour improve, especially be used in it is embedded (Embedded) it is become apparent when EEPROM product.

In the method for deleting for being known for EEPROM component, the charge of storage is in fowler-Nuo get Han (Fowler- Nordheim transistor) is moved to remove from floating grid under the tunneling effect of tunnelling (abbreviation F-N tunnelling) technology, and voltage is past It is past to need to be greater than 10V, then since the structure of single grid EEMPROM memory is transistor substrate-floating grid-capacitor substrate, lead Direction can be applied according to electric field and be released into either direction by causing the charge of storage；Cause the excessive wiping of single grid EEPROM component Except problem becomes more serious.

Summary of the invention

In view of the above problems, the main purpose of the present invention is to provide a kind of erasing sides of single gate nonvolatile memory Method is greater than 100 angstroms in the oxidated layer thickness of high pressure manufacturing process using single Floating gate structureMemory element erasing list Gate nonvolatile memory；That voltage is applied for drain electrode in erasing, grid do not impose voltage, with by drain voltage come It generates and controls anti-layer, and then improve the efficiency of erasing, when erasure completion, then due to drain voltage reduces or source voltage increases Stop, over-erasure can be prevented, to solve the missing of background technique.

Therefore, in order to achieve the above object, the method for deleting of list gate nonvolatile memory disclosed in this invention, is applied to single Gate nonvolatile memory, this single gate nonvolatile memory includes P-type semiconductor substrate, transistor and capacitance structure, wherein Transistor and capacitance structure are set to P-type semiconductor substrate, and transistor is by the first conductive grid storehouse in the first dielectric layer table Face, the first dielectric layer are located on semiconductor base, and have the first ion doped region of two highly conductives to be located at the first conductive grid Source electrode and drain electrode are formed with two side of the first dielectric layer；Capacitance structure also forms a sandwich structure such as transistor, includes Second ion doped region, the second dielectric layer and the second conductive grid, and the of the second conductive grid of capacitance structure and transistor One conductive grid is isolated and is electrically connected, and forms single Floating gate of non-voltile memory.This single gate nonvolatile memory Method for deleting, including apply a voltage to drain electrode, and grid does not impose voltage, it is anti-to be generated and be controlled by drain voltage Layer, to reduce erasing voltage and increase erasing efficiency.

Wherein, the first ion doped region and the second ion doped region are N trap doped region, and capacitance structure can be N trap capacitor Or N trap capacitor.It is all to make non-voltile memory with different structure changes come the operation wiped in the way of of the invention, all Within the scope of this invention.

Specifically, the method for deleting of list gate nonvolatile memory disclosed in this invention, it can be for by P-type semiconductor The non-voltile memory that substrate, transistor and capacitance structure are constituted carries out erasingization process, in P-type semiconductor substrate, source electrode With apply basic voltage, source voltage and drain voltage in drain electrode respectively, and voltage is not imposed on the first ion doped region, and Drain voltage is greater than source voltage, and source voltage is greater than or equal to basic voltage, and basic voltage is ground connection.

Detailed description of the invention

It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be to institute in embodiment Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention Example, for those of ordinary skill in the art, without any creative labor, can also be according to these attached drawings Obtain other attached drawings.

Figure 1A is the cross-sectional view of single gate nonvolatile memory structure of the first embodiment of the present invention；

Figure 1B is the cross-sectional view of single gate nonvolatile memory structure of the second embodiment of the present invention；

Fig. 2A is the structural schematic diagram set in the first embodiment of the present invention there are four endpoint；

Fig. 2 B is the structural schematic diagram set in the second embodiment of the present invention there are four endpoint；And

Fig. 2 C is the equivalent circuit of Fig. 2A and Fig. 2 B structure.

Symbol description:

30 single gate nonvolatile memory structures

32 NMOS transistors

320 first dielectric layers

322 first conductive grids

324 source electrodes

324 ' drain electrodes

326 channels

34 N trap capacitors

340 N traps

342 second dielectric layers

344 second conductive grids

36 P-type silicon substrates

38 isolation structures

40 single Floating gates

50 single gate nonvolatile memory structures

52 NMOS transistors

520 first dielectric layers

522 first conductive grids

524 source electrodes

524 ' drain electrodes

526 channels

54 N trap capacitors

542 second dielectric layers

544 second conductive grids

56 P-type silicon substrates

58 isolation structures

60 single Floating gates.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

Figure 1A is the cross-sectional view of list gate nonvolatile memory structure provided by one embodiment of the invention, single grid Pole non-volatile internal memory structure 30 includes NMOS transistor (NMOSFET) 32 and N trap (N-well) capacitor 34, in P-type silicon substrate In 36；NMOS transistor 32 includes that the first dielectric layer 320 is located on 36 surface of P-type silicon substrate, and the first conductive grid 322 stacks on First dielectric layer, 320 top and two ion doped regions N+ are located in P-type silicon substrate 36, respectively as its source electrode 324 and Drain electrode 324 ' forms a channel 326 between source electrode 324 and drain electrode 324 '；N trap capacitor 34 includes the second ion doped region in p-type It is N trap 340 in silicon base 36, the second dielectric layer 342 is located on 340 surface of N trap and the second conductive grid 344 stacks on the Two dielectric layers, 342 top, carries out forming top plate-dielectric layer-bottom plate capacitance structure.First conductive grid of NMOS transistor 32 Second conductive grid 344 at the top of 322 and N trap capacitor 34 is electrically connected and with an isolation structure 38 isolation, and it is single floating to form one Connect the structure of grid (floating gate) 40.

This single gate nonvolatile memory structure 30 sets the structure there are four endpoint, as shown in Figure 2 A, four endpoints point Not Wei source electrode, drain electrode, control grid and substrate, and in applying a basic voltage Vsub, source in substrate, source electrode, drain electrode respectively Pole tension Vs, drain voltage Vd are then to apply control grid voltage Vc in the first ion doped region；Fig. 2 C is its equivalent circuit. The condition of the erasingization process of this single gate nonvolatile memory structure 30 is as follows:

A.Vsub is ground connection (=0)；And

B.Vs≤Vsub=0, and Vs < Vd.

Therefore Vd > Vs≤Vsub=0, and Vc is not impose voltage.

Then, Figure 1B is the section view of list gate nonvolatile memory structure provided by second embodiment of the invention Figure, single gate nonvolatile memory structure 50 includes NMOS transistor (NMOSFET) 52 and N trap capacitor 54, in P-type silicon substrate 56 In；NMOS transistor 52 includes that the first dielectric layer 520 is located on 56 surface of P-type silicon substrate, and the first conductive grid 522 stacks on this First dielectric layer, 520 top and two ion doped regions N+ are located in P-type silicon substrate 56, respectively as its source electrode 524 and leakage Pole 524 ' forms a channel 526 between source electrode 524 and drain electrode 524 '；N trap capacitor 54 includes the second ion doped region in P-type silicon In substrate 56, the second dielectric layer 542 is located on 56 surface of P-type silicon substrate and the second conductive grid 544 stacks on the second dielectric 542 top of layer, carries out forming top plate-dielectric layer-bottom plate capacitance structure.The first conductive grid 522 and N of NMOS transistor 52 Second conductive grid 544 at the top of trap capacitor 54 is electrically connected and with an isolation structure 58 isolation, forms a single Floating gate The structure of (floating gate) 60.

This single gate nonvolatile memory structure 50 sets the structure there are four endpoint, as shown in Figure 2 B, four endpoints point Not Wei source electrode, drain electrode, control grid and substrate, and in applying a basic voltage Vsub, source in substrate, source electrode, drain electrode respectively Pole tension Vs, drain voltage Vd are then to apply control grid voltage Vc in the first ion doped region；Fig. 2 C is its equivalent circuit. The condition of the erasingization process of this single gate nonvolatile memory structure 50 is as follows:

A.Vsub is ground connection (=0)；And

B.Vs≤Vsub=0, and Vs < Vd.

Therefore Vd > Vs≤Vsub=0, and Vc is not impose voltage.

The structure of above-mentioned Figure 1A is manufactured in P-type silicon wafer and is obtained, the isolation structure 38 by standard isolation module processing procedure Lai It completes；After forming basic isolation structure 38, the channel 326 of N trap 340 and NMOS transistor 32 is by ion implant come shape At；After the dielectric layer of grow up the first conductive grid 322 and the second conductive grid 344, then deposits and form polysilicon, and with Lithography, which is patterned, forms single Floating gate 40 for polysilicon；Then ion implant is carried out to form NMOS transistor 32 Source electrode 324, drain electrode 324 ' and the control electrodes such as grid.After metallization, many single gate nonvolatile memories are just completed The production of structure 30.

Using same process, list gate nonvolatile memory structure 50, makes in a P-type silicon wafer shown in above-mentioned Figure 1B It makes and obtains, isolation structure 58 is completed by standard isolation module processing procedure；After forming basic isolation structure 58, N trap capacitor 54 and the channel 526 of NMOS transistor 52 formed by ion implant；In growth the first conductive grid 522, the second conductive gate After the dielectric layer of pole 523, then deposition forms polysilicon, and is patterned with lithography, polysilicon is formed single floating Connect grid 60；Then, it is electric to form the source electrode 524 of NMOS transistor 52, drain electrode 524 ' and control grid etc. to carry out ion implant Pole.After metallization, the production of single gate nonvolatile memory structure 50 is just completed.

In the present invention, above-mentioned processing procedure refers to the manufacturing process of general CMOS.

In conclusion the present invention proposes a kind of method for deleting of single gate nonvolatile memory, it is non-volatile for single grid Property internal storage structure applies a voltage to drain electrode, and grid does not impose voltage, anti-layer is generated and controlled by drain voltage, can drop Low erasing voltage and promotion erasing speed, when erasure completion, drain voltage can decline because of channel opening or source voltage liter Height, and stop wiping, to reduce the voltage of erasingization, and solve the problems, such as over-erasure.

Used herein a specific example illustrates the principle and implementation of the invention, and above embodiments are said It is bright to be merely used to help understand method and its core concept of the invention；At the same time, for those skilled in the art, foundation Thought of the invention, there will be changes in the specific implementation manner and application range.In conclusion the content of the present specification is not It is interpreted as limitation of the present invention.

Claims (3)

1. a kind of method for deleting of list gate nonvolatile memory, which includes a P-type semiconductor substrate, a crystalline substance Body Guan Yuyi capacitance structure, the transistor and the capacitance structure are set to the P-type semiconductor substrate, which includes one first Conductive grid and multiple first ion doped regions, and each first ion doped region is distinguished in the two sides of first conductive grid Source electrode and drain electrode are formed, which includes one second ion doped region and one second conductive grid, and first conductive gate Pole and second conductive grid are electrically connected to form a single Floating gate, which includes, it is characterised in that:

Apply a basic voltage Vsub, source voltage Vs and one respectively in the P-type semiconductor substrate, the source electrode and the drain electrode Drain voltage Vd does not impose voltage on first ion doped region, and meets following condition:

Vd>Vs≧Vsub；And

Vsub is ground connection.

2. the method for deleting of list gate nonvolatile memory as described in claim 1, which is characterized in that each first ion Doped region and second ion doped region are N trap doped region, which is N trap capacitor or N trap capacitor.

3. the method for deleting of list gate nonvolatile memory as described in claim 1, which is characterized in that the transistor is golden oxygen Half field effect transistor (MOSFET).