CN109697084B - Fast access memory architecture for time division multiplexed pipelined processor - Google Patents
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Abstract
A fast access memory architecture for a time division multiplexed pipeline processor characterized by: the instruction of the processor is completed by N pipeline clock cycles, and each stage of pipeline parts of the pipeline execute the operation of different threads in the same pipeline clock cycle; all threads multiplexing the pipeline are divided into a plurality of thread groups according to the time law of cut-in of the threads into the pipeline, so that the threads in each thread group cannot appear on the pipeline at the same time, all threads of each thread group share the same or a plurality of quick access memories, and a feasible storage entity is a single-port static random access memory (SP-SRAM).
Description
Technical Field
The present invention relates to the field of processor architectures, and in particular to an organization of fine-grained multithreading registers and memory.
Background
In the current fine-grained multithread processor, the realization of a register generally uses a register file with fixed capacity, the invention can enable threads in the same group to share a quick access memory by grouping the threads according to time characteristics, the access memory can not only replace the register file, but also provide more functions, and the capacity and the bandwidth maximization efficiency use of the quick access memory can be realized by dynamically adjusting the size of each quick access memory.
Disclosure of Invention
A fast access memory architecture for a time division multiplexed pipeline processor characterized by: the instruction of the processor is completed by N pipeline clock cycles, and each stage of pipeline parts of the pipeline execute the operation of different threads in the same pipeline clock cycle; all threads multiplexing the pipeline are divided into a plurality of thread groups according to the time law of the threads switched into the pipeline, so that the threads in each thread group cannot appear on the pipeline at the same time, and all threads of each thread group share the same or a plurality of quick access memories.
A typical grouping method is: because the number of the pipeline stages of the processor is N, one instruction of one thread can be completed by N pipeline clock cycles, the maximum value of the instruction execution speed of any thread is 1/N of the pipeline clock, threads with the same remainder after the pipeline clock count value of the moment when the thread is switched into the pipeline is divided by N cannot simultaneously appear on the pipeline, and therefore the access of the threads to the quick access memory never simultaneously appears. The threads that never occur simultaneously on the pipeline are grouped together and they may share one or more memory stores.
The most direct application of the quick access memory is to replace a register file of a traditional processor, a pipeline component of the processor can directly read and write the quick access memory to complete all functions of a register of the processor, and threads can access all storage spaces of the quick access memory connected with a thread group to which the threads belong, so that the number of the registers can be flexibly distributed, and the threads in the same thread group can exchange information directly and quickly. Meanwhile, any part or all of the memory space of the quick access memory can only belong to one thread, can be shared by a plurality of threads, and can be one part or even all of the main memory address space.
By the method for improving the read-write clock of the quick access memory, for example, the quick access memory works in 2 times of a pipeline clock, so that a larger access bandwidth can be provided for threads, one thread can read and write more data in one pipeline clock, or the thread can be used by threads of 2 thread groups in one pipeline clock, and can also be accessed by other peripheral equipment.
Generally, a thread does not access the quick access memory in each pipeline component on the pipeline, so different thread groups can share one quick access memory through time division multiplexing, and the bandwidth of a read-write port of the quick access memory can be utilized by hundreds of percent under the best condition.
The instruction sets supported by threads within different thread groups may be different, for example: instructions supported by threads of a simple functional thread group only need to access the register 3 times, while threads of some complex thread groups need to access the register 8 times, so that the bandwidth requirements of the threads of each thread group on the register are different, different bandwidth or time slices for accessing the quick access memory by different thread groups can be given to different thread groups according to different bandwidth requirements, and one or more threads can monopolize the quick access memory when necessary.
The registers actually needed by each thread are different, so the capacity of the final quick access memory is different, and the final quick access memory formed by combining a plurality of small memories with the same or different capacities can utilize the memory more effectively.
When the required register capacity is smaller than the available sub-memory capacity, the thread temporary information storage area or the thread information exchange area or a cache (cache) or a main memory or other use memories can be used.
In general, the area and power consumption of a single-port memory are superior to those of a multi-port memory, and in the invention, the circuit area can be saved by using the single-port memory, particularly a Static Random Access Memory (SRAM) using a single port on the premise of meeting the access bandwidth.
Drawings
FIG. 1 is a basic block diagram of a quick access memory
FIG. 2 is a diagram of the structure of the quick access memory interclass multiplexing
FIG. 3 is a diagram of a fast access memory unbalanced time division multiplexing architecture
FIG. 4 is a fast access memory internal space partitioning structure
FIG. 5 is a block diagram of a fast access memory bank
FIG. 6 is a basic timing diagram of a fast access memory
FIG. 7 is a timing diagram of fast access memory inter-bank multiplexing
FIG. 8 is a timing diagram of fast access memory unbalanced time division multiplexing
Detailed Description
In general, in the following description, specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, it will be understood by those skilled in the art that the embodiments may be practiced without these specific details. In particular with regard to functional components such as pipelines and memories, multiplexers, etc., the methods of the embodiments are specific techniques chosen for illustrative purposes, and other well-known methods may be selected for these embodiments.
First embodiment
FIG. 1 illustrates a fast access memory architecture and operation of a processor, comprising:
an instruction 1 fetching unit 101 located in the 1 st stage pipeline and operating in a pipeline clock;
an instruction 2 component 102 in the stage 2 pipeline operating at the pipeline clock;
a decode 1 unit 103 in the 3 rd stage pipeline, operating at the pipeline clock;
a decode 2 unit 104 in the 4 th stage pipeline, operating at the pipeline clock;
an execution 1 unit 105 in the 5 th stage pipeline, operating at the pipeline clock;
an execution 2 component 106 in the 6 th stage pipeline, operating at the pipeline clock;
a write back 1 component 107 in the 7 th stage pipeline, operating at the pipeline clock;
a write back 2 component 108 in the 8 th stage pipeline, operating at the pipeline clock;
the fast access memory 0 component 109 is a single port Static Random Access Memory (SRAM) operating at the pipeline clock frequency and coupled to the pipeline through the mux selector 117;
the fast access memory 1 component 110 is a single port Static Random Access Memory (SRAM) operating at the pipeline clock frequency and coupled to the pipeline through the mux selector 117;
the fast access memory 2 component 111 is a single port Static Random Access Memory (SRAM) operating at the pipeline clock frequency and coupled to the pipeline through the mux selector 117;
the fast access memory 3 component 112 is a single port Static Random Access Memory (SRAM) operating at the pipeline clock frequency and coupled to the pipeline through a mux selector 117;
the fast access memory 4 component 113 is a single port Static Random Access Memory (SRAM) operating at the pipeline clock frequency and coupled to the pipeline through a mux selector 117;
the fast access memory 5 component 114 is a single port Static Random Access Memory (SRAM) operating at the pipeline clock frequency and coupled to the pipeline through a mux selector 117;
the fast access memory 6 component 115 is a single port Static Random Access Memory (SRAM) operating at the pipeline clock frequency and coupled to the pipeline through the mux selector 117;
the fast access memory 7 component 116 is a single port Static Random Access Memory (SRAM) operating at the pipeline clock frequency and coupled to the pipeline through a mux selector 117.
The pipeline accesses the fast access memory at and only in decode 1 unit 103 at stage 3 pipeline, decode 2 unit 104 at stage 4 pipeline, write back 1 unit 107 at stage 7 pipeline, and write back 2 unit 108 at stage 8 pipeline. The pipeline component locates the particular fast access memory by the thread group to which the currently running thread belongs and then reads and writes the selected fast access memory by the mux selector 117.
Fig. 2 is a timing chart corresponding to the first embodiment. For the fast access memory 0 unit 109, the operating sequence on the pipeline clock is that the 1 st cycle is idle, the 2 nd cycle is idle, the 3 rd cycle is accessed by the thread group 0, the 4 th cycle is accessed by the thread group 0, the 5 th cycle is idle, the 6 th cycle is idle, the 7 th cycle is accessed by the thread group 0, and the 8 th cycle is accessed by the thread group 0. The rest of the fast access memory is similar to the figure.
Second embodiment
FIG. 2 illustrates a fast access memory thread group multiplexing architecture and form of operation for a processor, comprising:
an instruction 1 fetch unit 201 in the 1 st stage pipeline, operating at the pipeline clock;
an instruction 2 fetch unit 202 in the stage 2 pipeline, operating at the pipeline clock;
a decode 1 unit 203 in the 3 rd stage pipeline, operating at the pipeline clock;
a decode 2 unit 204 in the 4 th stage pipeline, operating at the pipeline clock;
an execution 2 unit 206 in the 6 th stage pipeline, operating at the pipeline clock;
a write back 1 component 207 in the 7 th stage pipeline, operating at the pipeline clock;
a write back 2 component 208 in the 8 th stage pipeline, operating at the pipeline clock;
the fast access memory 0 unit 209 is a single port memory operating at the pipeline clock frequency and connected to the pipeline through the mux selector 213;
the fast access memory 1 unit 210 is a single port memory operating at the pipeline clock frequency and connected to the pipeline through the multiplexer selector 213;
the fast access memory 2 component 211 is a single port memory operating at the pipeline clock frequency and connected to the pipeline through the mux selector 213;
the fast access memory 3 component 212 is a single port memory operating at the pipeline clock frequency and is coupled to the pipeline through a multiplexer selector 213.
The pipeline accesses the fast access memory at and only in decode 1 unit 203 at stage 3 pipeline, decode 2 unit 204 at stage 4 pipeline, write back 1 unit 207 at stage 7 pipeline, and write back 2 unit 208 at stage 8 pipeline. The pipeline component locates the particular fast access memory by the thread group to which the currently running thread belongs, and then reads and writes the selected fast access memory by the mux selector 213. The pipeline component locates the particular fast access memory by the thread group to which the currently running thread belongs, and then reads and writes the selected fast access memory by the mux selector 213.
In the embodiment, two thread groups which are not conflicted with each other are selected, and the same quick access memory is subjected to time division multiplexing to the two register groups, so that the bandwidth utilization rate of the quick access memory reaches 100%.
Fig. 7 is a timing chart corresponding to the second embodiment. For the fast access memory 0 component 109, its operating state on the pipeline clock is that cycle 1 is accessed by thread group 2, cycle 2 is accessed by thread group 2, cycle 3 is accessed by thread group 0, cycle 4 is accessed by thread group 0, cycle 5 is accessed by thread group 2, cycle 6 is accessed by thread group 2, cycle 7 is accessed by thread group 0, and cycle 8 is accessed by thread group 0. The rest of the fast access memory is similar to the figure. In this embodiment, the bandwidth of the fast access memory is completely exhausted, but by doubling the read-write clock of the fast access memory, more bandwidth can be developed, and these access capabilities can be used for other peripherals, and in addition, the fast access memory can be opened as a common system memory space for all thread groups to access.
Third embodiment
FIG. 3 illustrates an unbalanced time division multiplexing architecture between groups of fast access memory threads of a processor, comprising:
an instruction 1 fetch unit 301 in the 1 st stage pipeline, operating at the pipeline clock;
an instruction 2 component 302 in the stage 2 pipeline operating at the pipeline clock;
decode 1 unit 303, located in the 3 rd stage pipeline, operating at the pipeline clock;
a decode 2 unit 304 in the 4 th stage pipeline, operating at the pipeline clock;
an execution 2 component 306 in the 6 th stage pipeline, operating at the pipeline clock;
a write-back 1 section 307 in the 7 th stage pipeline, operating at the pipeline clock;
a write back 2 component 308 at stage 8 pipeline, operating at the pipeline clock;
the fast access memory 0 unit 309 is a single port memory operating at the pipeline clock frequency, connected to the pipeline through the mux selector 313;
the fast access memory 1 component 310 is a single port memory operating at the pipeline clock frequency and coupled to the pipeline through the mux selector 313;
the fast access memory 2 unit 311 is a single port memory operating at the pipeline clock frequency and connected to the pipeline through the multiplexer 313;
the fast access memory 3 component 312 is a single port memory operating at the pipeline clock frequency and coupled to the pipeline through the mux selector 313.
Because the thread groups support different instruction sets, for thread group 2, the pipeline may access the fast access memory at decode 1 component 303 at the 3 rd stage pipeline, decode 2 component 304 at the 4 th stage pipeline, execute 1 component 305 at the 5 th stage pipeline, write back 1 component 307 at the 7 th stage pipeline, and write back 2 component 308 at the 8 th stage pipeline. For thread group 4 threads, the pipeline accesses fast access memory only in decode 1 component 303 in the 3 rd stage pipeline, decode 2 component 304 in the 4 th stage pipeline, and write back 2 component 308 in the 8 th stage pipeline. For the remaining thread groups, the fast access memory is accessed only by decode 1 unit 303 in the 3 rd stage pipeline, decode 2 unit 304 in the 4 th stage pipeline, write back 1 unit 307 in the 7 th stage pipeline, and write back 2 unit 308 in the 8 th stage pipeline. The pipeline component locates the particular fast access memory by the thread group to which the currently running thread belongs, and then reads and writes the selected fast access memory by the mux selector 213.
Fig. 8 is a timing chart corresponding to the second embodiment. For the fast access memory 2 component 311, the operating state on the pipeline clock is that cycle 1 is accessed by thread group 2, cycle 2 is accessed by thread group 2, cycle 3 is accessed by thread group 2, cycle 4 is accessed by thread group 4, cycle 5 is accessed by thread group 2, cycle 6 is accessed by thread group 2, cycle 7 is accessed by thread group 4, and cycle 8 is accessed by thread group 2.
For the fast access memory 0 unit 309, its operating state on the pipeline clock is that cycle 1 is accessed by thread group 6, cycle 2 is accessed by thread group 6, cycle 3 is accessed by thread group 0, cycle 4 is accessed by thread group 0, cycle 5 is accessed by thread group 6, cycle 6 is accessed by thread group 6, cycle 7 is accessed by thread group 0, and cycle 8 is accessed by thread group 0. The rest of the fast access memory is similar to the figure.
Fourth embodiment
FIG. 4 illustrates fast access memory internal space partitioning for a processor.
The quick access memory 0 unit 401 has a memory capacity of 512 bytes, and is sequentially divided into 32 bytes dedicated to the thread 0, 64 bytes dedicated to the thread 1, 128 bytes shared by all threads, 128 bytes of main memory, and 64 bytes dedicated to the thread 2 as needed. The fast access memory has an external bandwidth for access by the remaining thread groups, and 128 bytes of main memory located in the fast access memory can be accessed by all threads to the memory space.
The fast access memory 1 unit 402 has a memory capacity of 32 bytes, and is divided into 32 bytes exclusively for the thread 3 in order as necessary.
The quick access memory 2 unit 403 has a memory capacity of 64 bytes, and is sequentially divided into 32 bytes for thread 4 and 32 bytes for thread 5 as necessary.
The quick access memory 3 unit 404 has a memory capacity of 128 bytes, and is sequentially divided into 32 bytes dedicated to the thread 6, 32 bytes dedicated to the thread 7, 48 bytes shared by the thread 6 and the thread 7, and 16 bytes of main memory as necessary. The quick access memory has no external bandwidth for accessing other thread groups, the main memory 16 bytes in the quick access memory can only be accessed by the threads in the thread group allocated to the quick access memory, and other threads cannot access the memory space, so that the memory data can be protected.
It should be noted that the thread within a thread group has access to all of its allocated space in the fast access memory, even if the space is not allocated to the thread, so the space owned by the thread is exclusively shared in the logical domain, and is not physically restricted, so that the registers of a particular thread are only a set of data that can be stored anywhere in the fast access memory on the processor.
Fifth embodiment
Fig. 5 is a diagram of a quick access memory combination. The fast access memory is now just a virtual conceptual memory, the entities of which are not specifically present but are assembled from specific physical memory as needed.
The quick access memory 0 unit 501 is a 7K byte logic memory composed of a 1K byte single port memory, a 2K byte single port memory, and a 4K byte single port memory.
The fast access memory 1 component 502 is a 3K byte logical memory that is a combination of a 1K byte single port memory and a 2K byte single port memory.
The fast access memory 2 component 503 is a 2K byte logical memory that is a combination of one 1K byte single port memory and another 1K byte single port memory.
The fast access memory 3 component 504 is a 2K byte logical memory directly generated from a 2K byte single port memory.
All physical memories are connected to the multiplexer 505 and to the pipeline through the multiplexer 505, so that each fast access memory is dynamically configurable by dynamically adjusting the data path of the multiplexer 505
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel designs disclosed herein.
Claims (59)
1. A fast access memory usage method for a time division multiplexed pipelined processor, characterized by: the processor uses an N-stage pipeline, and each stage of pipeline parts of the pipeline execute the operation of different threads in the same pipeline clock cycle; all threads multiplexing the pipeline are divided into a plurality of thread groups according to the time law of the threads switched into the pipeline, the threads in each thread group cannot appear on the pipeline at the same time, and all threads in each thread group share the same or a plurality of quick access memories.
2. The method of claim 1, further comprising: the clock period of the fast access memory is the same as or an integer multiple of the pipeline clock period.
3. The method of claim 1, further comprising: any part of the memory space or the whole memory space of the quick access memory can belong to only one thread, can be shared by a plurality of threads, and can also belong to one part of the main memory.
4. The method of claim 2, further comprising: any part of the memory space or the whole memory space of the quick access memory can belong to only one thread, can be shared by a plurality of threads, and can also belong to one part of the main memory.
5. The method of claim 1, further comprising: the thread can access part of the memory space of the quick access memory allocated by the thread group to which the thread belongs, and can also access the whole memory space of the quick access memory allocated by the thread group to which the thread belongs.
6. The method of claim 2, further comprising: the thread can access part of the memory space of the quick access memory allocated by the thread group to which the thread belongs, and can also access the whole memory space of the quick access memory allocated by the thread group to which the thread belongs.
7. The method of claim 3, further comprising: the thread can access part of the memory space of the quick access memory allocated by the thread group to which the thread belongs, and can also access the whole memory space of the quick access memory allocated by the thread group to which the thread belongs.
8. The method of claim 4, further comprising: the thread can access part of the memory space of the quick access memory allocated by the thread group to which the thread belongs, and can also access the whole memory space of the quick access memory allocated by the thread group to which the thread belongs.
9. The method of claim 1, further comprising: the time law of thread cut-in pipeline is that the remainder of the count value of pipeline clock divided by N is the same when thread cut-in pipeline.
10. The method of claim 2, further comprising: the time law of thread cut-in pipeline is that the remainder of the count value of pipeline clock divided by N is the same when thread cut-in pipeline.
11. The method of claim 3, further comprising: the time law of thread cut-in pipeline is that the remainder of the count value of pipeline clock divided by N is the same when thread cut-in pipeline.
12. The method of claim 4, further comprising: the time law of thread cut-in pipeline is that the remainder of the count value of pipeline clock divided by N is the same when thread cut-in pipeline.
13. The method of claim 1, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
14. The method of claim 2, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
15. The method of claim 3, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
16. The method of claim 4, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
17. The method of claim 5, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
18. The method of claim 6, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
19. The method of claim 7, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
20. The method of claim 8, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
21. The method as recited in claim 12, further comprising: the storage entity of the fast access memory is a single-ported static random access memory (SP-SRAM).
22. The method of claim 1, wherein the threads of different thread groups share fast access memory by time division multiplexing.
23. The method of claim 2, wherein the threads of different thread groups share fast access memory by time division multiplexing.
24. The method of claim 3, wherein the threads of different thread groups share fast access memory by time division multiplexing.
25. The method of claim 4, wherein the threads of different thread groups share fast access memory by time division multiplexing.
26. The method of claim 5, wherein the threads of different thread groups share fast access memory by time division multiplexing.
27. The method of claim 8, wherein the threads of different thread groups share fast access memory by time division multiplexing.
28. The method of claim 12, wherein the threads of different thread groups share fast access memory by time division multiplexing.
29. The method as recited in claim 22, further comprising: the number of access slots for time-division multiplexing of fast access memory by threads of different thread groups may be the same or different.
30. The method as recited in claim 23, further comprising: the number of access slots for time-division multiplexing of fast access memory by threads of different thread groups may be the same or different.
31. The method as recited in claim 24, further comprising: the number of access slots for time-division multiplexing of fast access memory by threads of different thread groups may be the same or different.
32. The method of claim 25, further comprising: the number of access slots for time-division multiplexing of fast access memory by threads of different thread groups may be the same or different.
33. The method of claim 26, further comprising: the number of access slots for time-division multiplexing of fast access memory by threads of different thread groups may be the same or different.
34. The method of claim 27, further comprising: the number of access slots for time-division multiplexing of fast access memory by threads of different thread groups may be the same or different.
35. The method as recited in claim 28, further comprising: the number of access slots for time-division multiplexing of fast access memory by threads of different thread groups may be the same or different.
36. The method of claim 1, further comprising: the fast access memory can be formed by combining a plurality of sub-memories with the same or different capacities according to the actual capacity requirement, and the capacities of the different fast access memories can be the same or different.
37. The method of claim 2, further comprising: the fast access memory can be formed by combining a plurality of sub-memories with the same or different capacities according to the actual capacity requirement, and the capacities of the different fast access memories can be the same or different.
38. The method of claim 3, further comprising: the fast access memory can be formed by combining a plurality of sub-memories with the same or different capacities according to the actual capacity requirement, and the capacities of the different fast access memories can be the same or different.
39. The method of claim 4, further comprising: the fast access memory can be formed by combining a plurality of sub-memories with the same or different capacities according to the actual capacity requirement, and the capacities of the different fast access memories can be the same or different.
40. The method of claim 8, further comprising: the fast access memory can be formed by combining a plurality of sub-memories with the same or different capacities according to the actual capacity requirement, and the capacities of the different fast access memories can be the same or different.
41. The method as recited in claim 12, further comprising: the fast access memory can be formed by combining a plurality of sub-memories with the same or different capacities according to the actual capacity requirement, and the capacities of the different fast access memories can be the same or different.
42. The method as recited in claim 28, further comprising: the fast access memory can be formed by combining a plurality of sub-memories with the same or different capacities according to the actual capacity requirement, and the capacities of the different fast access memories can be the same or different.
43. The method of claim 30, further comprising: the fast access memory can be formed by combining a plurality of sub-memories with the same or different capacities according to the actual capacity requirement, and the capacities of the different fast access memories can be the same or different.
44. The method of claim 1, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
45. The method of claim 2, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
46. The method of claim 3, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
47. The method of claim 4, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
48. The method of claim 5, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
49. The method of claim 6, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
50. The method of claim 7, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
51. The method of claim 8, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
52. The method as recited in claim 22, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
53. The method as recited in claim 23, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
54. The method as recited in claim 24, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
55. The method of claim 25, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
56. The method of claim 26, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
57. The method of claim 27, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
58. The method as recited in claim 28, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
59. The method of claim 30, further comprising: when the actual needs of the entity memory used for combining the quick access memories exceed the actual needs, the entity memory can be transferred to a thread temporary information memory or a thread information exchange memory or a cache (cache) or a main memory or other purpose memories.
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