CN109683519A - A kind of FPGA implementation method of adaptive algorithm - Google Patents

A kind of FPGA implementation method of adaptive algorithm Download PDF

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Publication number
CN109683519A
CN109683519A CN201811568900.0A CN201811568900A CN109683519A CN 109683519 A CN109683519 A CN 109683519A CN 201811568900 A CN201811568900 A CN 201811568900A CN 109683519 A CN109683519 A CN 109683519A
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matrix
signal
vector
floating
implementation method
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裴杰
王沛尧
朱岱寅
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Nanjing University of Aeronautics and Astronautics
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Nanjing University of Aeronautics and Astronautics
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0426—Programming the control sequence

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Radio Transmission System (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Abstract

The present invention relates to a kind of FPGA implementation methods of adaptive algorithm, belong to digital signal processing technique field.This method comprises the following steps: 1, calculate the steering vector of the even linear array of four bays composition；2, calculate the autocorrelation matrix of incoming wave signal；3, calculate incoming wave signal autocorrelation inverse of a matrix matrix；4, calculate weight vector；5, weight vector is multiplied with the reception signal of four array elements, obtains output signal.The present invention can be realized adaptive-filtering, to realize the effect of adaptive array.

Description

A kind of FPGA implementation method of adaptive algorithm
Technical field
The present invention relates to a kind of FPGA of adaptive algorithm (field programmable gate array) implementation methods, belong to digital signal Processing technology field.
Background technique
Sef-adapting filter carries out operation by recursive algorithm, so that it is cannot to obtain related signal characteristic complete It is possible to complete filtering operation in the environment of knowledge.Under Stationary Random Environments, recursive algorithm restrains Mr. Yu after some successful iterations Optimal wiener solution in kind statistical significance；Under non-stationary environment, which improves a kind of tracking ability, because it can be with Track input data statistical property changes with time, as long as this variation is enough slowly.One as recursive algorithm application The parameter of a direct result, sef-adapting filter will be updated from an iteration to another an iteration whereby, filter parameter Become associated with the data.
Sef-adapting filter, which has, well runs under circumstances not known and tracks the ability that input statistic changes over time, So that sef-adapting filter becomes signal processing and automatically controls the powerful equipment of application field.It has been applied successfully to lead to The fields such as letter, radar, sonar.
The effect of four kinds of fundamental types of sef-adapting filter application is described as follows:
(1) it recognizes.In this kind of application for being related to identification, sef-adapting filter, which is used to provide one, in some sense can The linear model of enough best fitted unknown devices.
(2) inversion model.In the application of the second class, the effect of sef-adapting filter is to provide an inversion model, which can Best fitted unknown noise device in some sense.
(3) it predicts.Here, the effect of sef-adapting filter is one provided the current value of random signal in some sense It is a preferably to predict.
(4) interference is eliminated.In last a kind of application, sef-adapting filter is eliminated with optimum mode in some sense It include the unknown disturbances in baseband signal.
Arbitrary array element directional diagram, polarization and spacing work can be used in adaptive array.Its energy adjust automatically polarization, it is right The polarization decay of desired signal is minimum, maximum receiving direction can be adjusted to desired signal arrival bearing automatically, and by zero to tune To interference arrival bearing, therefore its anti-interference ability is splendid.
FPGA (Field Programmable Gate Array, field programmable gate array) is in PAL (Generic Array Logic, general array are patrolled by (Programmable Array Logic, programmable logic array), GAL Volume), develop on the basis of CPLD (Complex Programmable Logic Device, Complex Programmable Logic Devices) A kind of semi-custom circuit come, it not only compensates for the deficiency of custom circuit, while compared to pervious logical device, electricity Number amount greatly increases again.
It is compared, degree of parallelism and reality with traditional DSP (Digital signal processor, digital signal processor) When property is preferable, therefore FPGA is widely used in the fields such as High Speed Communication Interface Design, high-speed data acquisition, high-speed data processing.
Summary of the invention
The invention proposes a kind of FPGA implementation method of adaptive algorithm, combine hard inside adaptive algorithm and FPGA The advantage of part realizes the effect of adaptive array.
The present invention is to solve its technical problem to adopt the following technical scheme that
A kind of FPGA implementation method of adaptive algorithm, includes the following steps:
Step 1, the steering vector of the even linear array of four bays composition is calculated；
Step 2, the autocorrelation matrix of incoming wave signal is calculated；
Step 3, incoming wave signal autocorrelation inverse of a matrix matrix is calculated；
Step 4, weight vector is calculated；
Step 5, weight vector is multiplied with the reception signal of four array elements, obtains output signal.
Detailed process is as follows for the step 1:
The plural number of antenna is calculated by the position of the azimuth of antenna, pitch angle and each bay under same coordinate base Steering vector.
Detailed process is as follows for the step 2:
Quaternary antenna array, which is listed in after analog-to-digital conversion, Digital Down Convert, obtains signal plural number column vector, by the column vector It is multiplied to obtain the autocorrelation matrix of signal with its conjugate transposition.With continually entering for signal column vector, will acquire every time from Correlation matrix cycle accumulor, when accumulative frequency reaches setting value, by finally obtained autocorrelation matrix divided by accumulative frequency after Output.
Detailed process is as follows for the step 3:
For the quadravalence matrix exported in step 2, then the complementary minor for first asking its all seeks its adjoint matrix according to complementary minor Battle array and determinant finally will obtain the inverse matrix of the quadravalence matrix with divided by determinant.
Detailed process is as follows for the step 4:
The signal inverse matrix that the plural steering vector and step 3 obtained by step 1 obtains acquires the plural number power of bay Vector.
Detailed process is as follows for the step 5:
After carrying out conjugate transposition to the plural weight vector in step 4, it is answered with subsequent by the signal that down coversion obtains The multiplication of ordered series of numbers vector is simultaneously defeated.
Beneficial effects of the present invention are as follows:
The present invention realizes adaptive array using FPGA technology, according to the directional diagram that last simulation result is drawn, zero Sunken bosom can be more than that -80dB reaches -80.15dB, illustrate that antenna array is preferable to the inhibitory effect of interference signal；And useful Gain in sense illustrates that the main lobe of antenna array can effectively be directed at useful signal also close to maximum.Therefore, of the invention It so that antenna array received useful signal, inhibited interference signal, improve signal-to-noise ratio, reach the effect of adaptive array Fruit.
Detailed description of the invention
Fig. 1 is system block diagram of the invention.
Fig. 2 is that the FPGA that the conjugate transposition of several column vector sum itself is multiplied realizes block diagram.
Fig. 3 is that the FPGA of complex multiplication realizes block diagram.
Fig. 4 is the directional diagram that the weight vector that FPGA is acquired is drawn.
Fig. 5 is system flow chart of the invention.
Fig. 6 is that the FPGA of system realizes block diagram.
Specific embodiment
The invention is described in further details with reference to the accompanying drawing.
System block diagram of the invention is as shown in Figure 1.
In step 1, the steering vector of antenna array
Wherein steer indicates that the steering vector of antenna array, λ are incoming wave wavelength, and d is aperture length, and x is array element in reference axis In x coordinate, y is y-coordinate value of the array element in reference axis, and φ is antenna azimuth, and θ is the pitch angle of antenna, i.e., antenna with The angle of x/y plane.
Data and result are double-precision floating point forms in the present invention.When carrying out FPGA programming, for formula (1) multiplication, addition, division arithmetic in, call respectively floating multiplication plus, realize except IP kernel；And for the index in formula (1) Operation calls Cordic IP kernel to realize, sin and the cos output of Cordic core are the imaginary part and real part of steering vector.
In step 2, the incoming wave signal of antenna array is becoming plural column vector after analog-to-digital conversion, Digital Down Convert, Then
Rs=Rs+samplesampleH (2)
Rs is the plural autocorrelation matrix of incoming wave signal in formula, and sample is plural column vector, sampleHIt is sample Conjugate transposition.
Before first several column vector calculates, Rs zero, with the progress of sampling, incoming wave signal plural number column vector is continuous It updates, Rs is constantly cumulative, when cumulative number is equal to a setting value, by accumulation result divided by exporting after accumulative frequency, obtains The mean value of incoming wave signal autocorrelation matrix.
In FPGA programming, it is multiplied, leads to for the conjugate transposition for the several column vector sum itself being related in formula (2) It crosses and four floating-point multiplier cores, a floating-point adder core and a floating-point adder core is called to realize.It is assumed to be and asks sample·sampleHAs a result m row, the n-th column element b inmn, then two data input of floating-point multiplier 1 is respectively multiple Two data of the real part of the real part of m row element, line n element in ordered series of numbers vector sample, floating-point multiplier 2 input difference Two data for imaginary part, the imaginary part of line n element of m row element in plural column vector sample, floating-point multiplier 3 input The real part of the imaginary part of m row element in respectively plural column vector sample, line n element, two data of floating-point multiplier 4 Input is respectively the imaginary part of the real part of m row element, line n element in plural column vector sample, and the number of floating-point adder It is respectively the output of floating-point multiplier 1 and floating-point multiplier 2 according to input, the data input of floating-point subtracter is respectively floating-point multiplication The output of device 3 and floating-point multiplier 4, the output of such floating-point adder are bmnReal part, the output of floating-point subtracter is bmnImaginary part.Fig. 2 is that the FPGA that the conjugate transposition of several column vector sum itself is multiplied realizes block diagram.
In addition, calling different type Floating Point IP to carry out sequential operation, such as first floating-point multiplier core is called to be multiplied Method operation, since IP kernel is there are delay time, cannot be calculated first when recalling the results added of floating-point adder verification multiplication After the multiply-add value of one group of data, then next group of data are input to multiplier, the traffic latency time can be greatly increased in this way, answered The pending serial mode of institute is input to multiplier core by this, after the result of multiplier is input to adder, such ability It improves the processing speed of whole system, increase real-time.
In step 3, if the autocorrelation matrix of step 2 output is
Wherein a11, a12, a13, a14, a21..., a43, a44It is the element on autocorrelation matrix Rs corresponding position.
First acquire a11, a12, a13, a14, a21..., a43, a44Corresponding complementary minor A11, A12, A13, A14, A21..., A43, A44, then the determinant of Rs
| Rs |=a11·A11-a12·A12+a13·A13-a14·A14 (4)
The adjoint matrix of Rs
The then inverse matrix of autocorrelation matrix Rs
In FPGA programming, four floating-point multiplier cores, a floating-point adder core and a floating add are called Device core realizes complex float multiplication.Assuming that calculating PQ, then the two of floating-point multiplier 1 data are defeated for two plural numbers P, Q Enter the real part of the respectively real part of P, Q, two data input of floating-point multiplier 2 is respectively imaginary part, the imaginary part of Q of P, floating multiplication Two data input of musical instruments used in a Buddhist or Taoist mass 3 is respectively the imaginary part of the real part of P, Q, and two data input of floating-point multiplier 4 is respectively the void of P Portion, Q real part, and the data of floating-point subtracter input be respectively floating-point multiplier 1 and floating-point multiplier 2 output, floating addition The data input of musical instruments used in a Buddhist or Taoist mass is respectively the output of floating-point multiplier 3 and floating-point multiplier 4, and the output of such floating-point subtracter is The real part of PQ, the output of floating-point adder are the imaginary part of PQ.Fig. 3 is that the FPGA of complex multiplication realizes block diagram.
And for complex float division, then need to call four floating-point multiplier cores, a floating-point adder core, one it is floating Adder core and a Floating-point divider core are put to realize.Assuming that being calculated for two plural numbers P, QThen floating-point multiplier 1 The input of two data be respectively the real part of P, Q real part, two data input of floating-point multiplier 2 is respectively the imaginary part of P, Q Imaginary part, two data input of floating-point multiplier 3 is respectively the real part of the imaginary part of P, Q, and two data of floating-point multiplier 4 are defeated Enter the imaginary part of the respectively real part of P, Q, and the input of the data of floating-point adder is respectively floating-point multiplier 1 and floating-point multiplier 2 Output, floating-point subtracter data input be respectively floating-point multiplier 3 and floating-point multiplier 4 output, then by floating addition The output of musical instruments used in a Buddhist or Taoist mass, floating-point subtracter is deposited respectively, and floating-point multiplier and floating-point adder is recycled to calculate Q real and imaginary parts Quadratic sum finally utilizes Floating-point divider, and the output for the floating-point adder deposited before and the output of floating-point subtracter are distinguished It can be obtained divided by the quadratic sum of Q real and imaginary partsAs a result real and imaginary parts.
In step 4, the weight vector of antenna array
In formula: w is weight vector, Rs-1It is the inverse matrix of the autocorrelation matrix acquired in step 3, steer indicates antenna array Steering vector, steerHIt is the conjugate transposition of steer, abs indicates modulus value.
For the step, since dividend and divisor contain Rs in formula (7)-1Steer, therefore in FPGA programming Rs should first be calculated-1Steer is deposited as intermediate variable, is called after convenient.When realizing modulo operation, if For plural X, calculates abs (X), floating-point multiplier core, floating-point adder core and floating-point square root core should be called.First using floating Dot product musical instruments used in a Buddhist or Taoist mass and floating-point adder calculate the quadratic sum of X real and imaginary parts, then the quadratic sum of X real and imaginary parts are input to floating Square root core is put to get abs (X) result is arrived.
When antenna parameter is as shown in table 1, the directional diagram that the weight vector that operation FPGA program obtains is drawn is such as
Fig. 4.
Incoming wave wavelength (λ) 0.143m
Aperture length (d) 0.063m
The x-axis coordinate (x) of antenna array [0；1；0；1]
The x-axis coordinate (y) of antenna array [0；0；1；1]
Antenna elevation angle (θ) °
Antenna azimuth (φ) °
1 antenna parameter of table
In step 5, after the plural weight vector that step 4 is acquired carries out conjugate transposition, obtained with subsequent by down coversion Signal plural number column vector be multiplied, i.e. weighted sum finally exports.
In the step, floating-point multiplier, floating-point adder, floating-point subtracter is equally called to complete FPGA programming.
Fig. 5 is system flow chart of the invention.
In addition, the calculation amount of steering vector module is smaller relative to other modules such as autocorrelation matrix, do not need to repeat yet It calculates, therefore in the circulation of FPGA top state machine, it can be by steering vector module isolated operation, it is not necessary to guiding arrow first have been calculated Amount calculates autocorrelation matrix again, increases extra program runtime.
Fig. 6 is that the FPGA of system realizes block diagram.
The above is only some embodiments of the invention, it is noted that for the ordinary skill people of the art For member, without departing from the principle of the present invention, several improvement can also be made, these improvement should be regarded as guarantor of the invention Protect range.

Claims (6)

1. a kind of FPGA implementation method of adaptive algorithm, which comprises the steps of:
Step 1, the steering vector of the even linear array of four bays composition is calculated；
Step 2, the autocorrelation matrix of incoming wave signal is calculated；
Step 3, incoming wave signal autocorrelation inverse of a matrix matrix is calculated；
Step 4, weight vector is calculated；
Step 5, weight vector is multiplied with the reception signal of four array elements, obtains output signal.
2. a kind of FPGA implementation method of adaptive algorithm according to claim 1, it is characterised in that: the step 1 Detailed process is as follows:
The plural number guiding of antenna is calculated by the position of the azimuth of antenna, pitch angle and each bay under same coordinate base Vector.
3. a kind of FPGA implementation method of adaptive algorithm according to claim 1: the detailed process of the step 2 is such as Under:
Quaternary antenna array, which is listed in after analog-to-digital conversion, Digital Down Convert, obtains signal plural number column vector, by the column vector and its Conjugate transposition is multiplied to obtain the autocorrelation matrix of signal；With continually entering for signal column vector, the auto-correlation that will be acquired every time Matrix circular is cumulative, when accumulative frequency reaches setting value, by finally obtained autocorrelation matrix divided by exporting after accumulative frequency Quadravalence matrix.
4. a kind of FPGA implementation method of adaptive algorithm according to claim 3: the detailed process of the step 3 is such as Under:
For the quadravalence matrix exported in step 2, the complementary minor for first asking its all, then according to complementary minor ask its adjoint matrix and Determinant finally will obtain the inverse matrix of the quadravalence matrix with divided by determinant.
5. a kind of FPGA implementation method of adaptive algorithm according to claim 1: the detailed process of the step 4 is such as Under:
The signal inverse matrix that the plural steering vector and step 3 obtained by step 1 obtains acquires the plural weight vector of bay.
6. a kind of FPGA implementation method of adaptive algorithm according to claim 1: the detailed process of the step 5 is such as Under:
After carrying out conjugate transposition to the plural weight vector in step 4, by itself and the subsequent signal several column obtained by down coversion Vector is multiplied and exports.
CN201811568900.0A 2018-12-21 2018-12-21 A kind of FPGA implementation method of adaptive algorithm Pending CN109683519A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110598271A (en) * 2019-08-22 2019-12-20 中国电子科技集团公司第二十九研究所 System and method for realizing SLC (Single chip logic) function of 4 auxiliary antennas based on FPGA (field programmable Gate array)

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CN103116170A (en) * 2013-01-16 2013-05-22 武汉大学 Indoor testing system of antenna array based interference rejection module of global navigation satellite system (GNSS)
CN105227227A (en) * 2015-10-15 2016-01-06 宿州学院 A kind of intelligent antenna beam based on small echo forms system and method
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Publication number Priority date Publication date Assignee Title
CN110598271A (en) * 2019-08-22 2019-12-20 中国电子科技集团公司第二十九研究所 System and method for realizing SLC (Single chip logic) function of 4 auxiliary antennas based on FPGA (field programmable Gate array)
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