CN109657323B - Wavelet reconstruction accelerating circuit - Google Patents
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Abstract
The invention discloses a wavelet reconstruction accelerating circuit, which comprises m reconstruction units, wherein each reconstruction unit comprises a data input port, a data selection signal input port, a high-pass filtering parameter input port, a low-pass filtering parameter input port, a convolution data input port and an output port, the m reconstruction unit is an initial reconstruction unit, and the input data of the corresponding convolution data input port is 0; the 1 st reconstruction unit is a termination reconstruction unit, and the corresponding output port outputs the reconstruction data of the reconstruction acceleration circuit; the output port of the reconstruction unit is connected with the convolution data input port of the next reconstruction unit. The wavelet reconstruction accelerating circuit provided by the invention improves the calculation proportion of useful data calculation in the whole calculation, realizes the sharing of the multiplier and the adder through the control of parameters and data flow, further reduces the circuit area and effectively reduces the power consumption.
Description
Technical Field
The invention belongs to the field of digital circuits, and particularly relates to a wavelet reconstruction accelerating circuit.
Background
The basic idea of fourier transformation is to use a sine-cosine function to represent a function, so that a time domain signal is mapped onto the frequency domain, and frequency domain analysis of the signal is completed. The periodicity of the sine and cosine functions results in a fourier transform that does not represent the information of the signal well in the time domain. The accuracy of the frequency domain results in blurring of the time domain, which also results in blurring of the frequency domain. Wavelet transform, which represents a target signal using translation and expansion of a basis function, can represent information of the signal in both time and frequency domains, and therefore, has been attracting attention.
Wavelet transformation is commonly used in digital signal processing and image processing. The main steps are divided into two steps, namely decomposition and reconstruction of signals. During the decomposition of the signal, there are basic operations such as convolution and downsampling. The performance of the two basic operations determines the performance of the wavelet operation. In the design process of the wavelet calculation hardware accelerator, the factors such as the speed, the power consumption, the area and the like of circuit calculation are required to be considered at the same time, and the calculation flow and the calculation time sequence are properly arranged so as to obtain the optimal effect.
The reconstruction and decomposition processes of the wavelet transformation are opposite, the low-pass data and the high-pass data are respectively up-sampled, and the low-pass data and the high-pass data are added through corresponding high-pass reconstruction filters and low-pass reconstruction filters, so that corresponding results are finally calculated. The whole data reconstruction process can be understood as synthesizing new data from low-pass and high-pass data. If the data amounts of the high pass and the low pass are n, respectively, the synthesized data amount is 2n.
The basic flow of wavelet reconstruction is shown in fig. 1, data x1 (n) and x2 (n) are input, up-sampling is carried out on the two signals by 2 times, new data stream sequences conv1 (n) and conv2 (n) are generated through reconstruction filters corresponding to low frequency and high frequency, and the two data stream sequences are added to finish the data reconstruction of the first layer. The reconstruction method of the second layer is similar to that of the first layer, and is divided into several basic steps of up-sampling, filtering and adding. For different levels of wavelet reconstruction, there is one basic building block, as indicated by the area identified by the dashed line. Optimization of the repeat unit determines the overall performance of the circuit.
During the reconstruction process the up-sampling process is relatively simple, but the filter immediately following it will filter all the data. Since the up-sampled data stream is a sparse data stream adjacent to the effective data, there are a large number of multiplications and additions redundant in the filtering process. Therefore, it is necessary to further increase the computation density of useful data, share the relative computation amount, adjust the data structure, method and structure of wavelet reconstruction, complete the optimization of computation, and design a corresponding hardware acceleration circuit.
Disclosure of Invention
The invention aims to provide a wavelet reconstruction accelerating circuit, redundant data are not calculated any more due to up-sampling, the calculation proportion of useful data calculation in integral calculation is improved, meanwhile, through controlling parameters and data flow, the sharing of a multiplier and an adder is realized, the circuit area is further reduced, and the power consumption is effectively reduced.
In order to achieve the above purpose, the present invention adopts the following technical scheme: the wavelet reconstruction accelerating circuit comprises m reconstruction units, wherein each reconstruction unit comprises a data input port, a data selection signal input port, a high-pass filtering parameter input port, a low-pass filtering parameter input port, a convolution data input port and an output port, the data input port inputs data x (n), the data selection signal input port inputs a data selection signal sel, the m reconstruction unit is an initial reconstruction unit, and the input data of the corresponding convolution data input port is 0; the 1 st reconstruction unit is a termination reconstruction unit, and the corresponding output port outputs the reconstruction data of the reconstruction acceleration circuit; the low-pass filtering parameter input port inputs low-pass filtering parameters, and the high-pass filtering parameter input port inputs high-pass filtering parameters; the output port of the reconstruction unit is connected with the convolution data input port of the next reconstruction unit; m is the length of the wavelet base, and 2 is less than or equal to m.
Further, the reconstruction unit further comprises a multiplier, a first adder, a second adder, a first data selector, a second data selector, a third data selector, a first register and a second register, wherein the selection of the high-pass filtering parameter and the low-pass filtering parameter is completed in the first data selector, and the high-pass filtering parameter and the low-pass filtering parameter are multiplied with input data; the selection of the data and 0 in the first register at the last clock period is completed in the second data selector, and the addition result is stored in the first register, the selection of the addition result and 0 is completed in the third data selector, and the addition result is added again with the data of the data input port of the reconstruction unit, and the addition result is stored in the second register as the output data of the reconstruction unit.
Further, two selection ends of the first data selector are respectively connected with a high-pass filtering parameter and a low-pass filtering parameter, an output end of the first data selector is connected with a second input port of the multiplier, the input data x (n) is connected with a first input port of the multiplier, an output port of the multiplier is connected with a first input port of the first adder, an output port of the first adder is connected with an input port of a first register, an output port of the first register is simultaneously connected with one selection end of a second data selector and a third selector, the other selection ends of the second data selector and the third selector are connected with 0, an output port of the second data selector is connected with a second input port of the first adder, an output port of the third data selector is connected with a first input port of the second adder, a second input port of the second adder is a convolution data input port of the reconstruction unit, an output port of the second adder is connected with an input port of the second register, and an output port of the second adder is an output port of the reconstruction unit; the data selection signal sel is connected with the enabling input ends of the first data selector, the second data selector and the third data selector at the same time, wherein when 0 is selected in the second data selector, the third data selector selects the data output by the output end of the first register.
Further, the output port of the first register is connected to the first selection end of the second data selector and the second selection end of the third data selector at the same time, and the input data of the second selection end of the second data selector and the first selection end of the third data selector is 0.
Further, when the data selection signal sel is 0, the second data selector and the third data selector are controlled to both select the data connected to the first selection end, the first data selector selects the high-pass filtering parameter or the low-pass filtering parameter, the input data is the high-pass data or the low-pass data corresponding to the first data selector, and the data selection signal sel input into the reconstruction acceleration circuit for the first time is 1.
Further, when the data selection signal sel is 0, the second data selector and the third data selector are controlled to select the data connected to the second selection end thereof, the first data selector selects the high-pass filtering parameter or the low-pass filtering parameter, the input data is the high-pass data or the low-pass data corresponding to the first data selector, and the data selection signal sel input into the reconstruction acceleration circuit for the first time is 0.
Further, the output data corresponding to the input data x (n) is delayed by two clock cycles.
Further, the low-pass input data and the high-pass input data in the input data x (n) are staggered.
The beneficial effects of the invention are as follows: (1) The invention defines a new data input structure, and the low-pass and high-pass filtering results realize time-sharing multiplexing in the same data channel.
(2) Redundant data is not calculated any more due to up-sampling, the calculation proportion of useful data calculation in overall calculation is improved, meanwhile, through controlling parameters and data flow, sharing of a multiplier and an adder is achieved, the circuit area is further reduced, and power consumption is effectively reduced.
(3) The parameter positions are reasonable, and the data calculation delay is reduced, so that the overall delay of the circuit cannot be changed due to the expansion of the wavelet base.
(4) Along with the expansion of wavelet base dimension, the circuit shown in the patent can be effectively expanded, and has good adaptability to different lengths and different wavelet bases.
Drawings
Fig. 1 is a basic flow chart of a conventional wavelet reconstruction.
Fig. 2 is an overall diagram of a wavelet reconstruction acceleration circuit of the present invention.
Fig. 3 is a circuit diagram of the ith reconstruction unit.
Fig. 4 is a sequence of the input data.
Fig. 5 is a reconstruction circuit with a wavelet base length of 6 in an embodiment.
Fig. 6 is a timing diagram of a wavelet reconstruction acceleration circuit in an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.
As shown in figure 2, the wavelet reconstruction accelerating circuit comprises m reconstruction units, wherein the reconstruction units comprise a data input port, a data selection signal input port and a low-pass filterThe device comprises a parameter input port, a high-pass filtering parameter input port, a convolution data input port and an output port, wherein the data input port inputs data x (n), and the data selection signal input port inputs a data selection signal sel, wherein an mth reconstruction unit is a starting reconstruction unit, and the input data of the corresponding convolution data input port is 0; the 1 st reconstruction unit is a termination reconstruction unit, the corresponding output port outputs the reconstruction data of the reconstruction accelerating circuit, and the low-pass filter parameter input port of the 1 st reconstruction unit inputs the low-pass filter parameter a 1 The high-pass filtering parameter input port of the 1 st reconstruction unit inputs the high-pass filtering parameter b 1 The method comprises the steps of carrying out a first treatment on the surface of the The output port of the kth reconstruction unit is connected with the convolution data input port of the kth-1 reconstruction unit; the low-pass filter parameter input port of the kth reconstruction unit inputs the low-pass filter parameter a k The high-pass filtering parameter input port of the kth reconstruction unit inputs the high-pass filtering parameter b k Wherein k is the length of the wavelet base, m and k are integers, and m is more than or equal to 2 and less than or equal to m, and k is more than or equal to 1 and less than or equal to m
As shown in fig. 3, the ith reconstruction unit includes a multiplier, a first adder, a second adder, a first data selector mux1, a second data selector mux2, a third data selector mux3, and a first register R A And a second register R B It is assumed that the first data selector mux1, the second data selector mux2, and the third data selector mux3 are identical, and each has two selection terminals, namely, a first selection terminal and a second selection terminal, an enable input terminal, and an output port. The same data select signal sel controls the first data selector mux1, the second data selector mux2, and the third data selector mux3 to simultaneously select data whose first select terminal or second connection terminal is connected to the input.
In the invention, two selection ends of a first data selector are respectively connected with a high-pass filtering parameter and a low-pass filtering parameter, the output end of the first data selector is connected with a second input port of a multiplier, input data x (n) is connected with a first input port of the multiplier, the output port of the multiplier is connected with a first input port of a first adder, the output port of the first adder is connected with an input port of a first register, the output ports of the first register are simultaneously connected with one selection end of a second data selector and a third selector, the other selection ends of the second data selector and the third selector are connected with 0, the output port of the second data selector is connected with a second input port of the first adder, the second input port of the third data selector is connected with a first input port of the second adder, the second input port of the second adder is a convolution data input port of the reconstruction unit, the output port of the second adder is connected with an input port of the second register, and the output port of the second register is an output port of the reconstruction unit; the data selection signal sel is connected to enable inputs of the first, second and third data selectors simultaneously. Wherein, the relationship between the two selection ends of the second data selector and the third data selector in the present invention must satisfy: when 0 is selected in the second data selector, the third data selector selects the data output from the output terminal of the first register.
It is assumed that the output port of the first register is simultaneously connected to the first selection terminal of the second data selector and the second selection terminal of the third data selector, and the input data of the second selection terminal of the second data selector and the first selection terminal of the third data selector is 0. There are two cases: (1) When the data selection signal sel is 0, the second data selector and the third data selector are controlled to select the data connected with the first selection end, the first data selector selects the high-pass filtering parameter or the low-pass filtering parameter, the input data is the high-pass data or the low-pass data corresponding to the first data selector, and the data selection signal sel input into the reconstruction acceleration circuit for the first time is 1. (2) When the data selection signal sel is 0, the second data selector and the third data selector are controlled to select the data connected with the second selection end, the first data selector selects the high-pass filtering parameter or the low-pass filtering parameter, the input data is the high-pass data or the low-pass data corresponding to the first data selector, and the data selection signal sel input into the reconstruction acceleration circuit for the first time is 0. The following is described by way of example in fig. 3:
with continued reference to fig. 3, the high-pass filter parameter b i A first selection terminal connected to the first data selector mux1, low-passFilter parameter a i A second selection end connected with the first data selector mux1, an output end of the first data selector mux1 is connected with a second input port of the multiplier, input data x (n) is connected with a first input port of the multiplier, an output port of the multiplier is connected with a first input port of the first adder, and an output port of the first adder is connected with a first register R A Input port of the first register R A The output port of the second data selector mux2 is connected with the first selection end of the second data selector mux2 and the second selection end of the third data selector mux3 at the same time, the input data of the second selection end of the second data selector mux2 and the first selection end of the third data selector mux3 are 0, the output port of the second data selector mux2 is connected with the second input port of the first adder, the output port of the third data selector mux3 is connected with the first input port of the second adder, the second input port of the second adder is the convolution data input port c of the reconstruction unit i-1 The output port of the second adder is connected with the second register R B Input port of the second register R B Is the output port conv of the reconstruction unit i . Wherein the data selection signal sel is connected to the enable input terminals of the first data selector mux1, the second data selector mux2 and the third data selector mux3 at the same time, wherein i represents the i-th reconstruction unit, and 1.ltoreq.i.ltoreq.m.
With continued reference to fig. 3, sel=0 is used to select the first selection ends of the first data selector mux1, the second data selector mux2 and the third data selector mux3, sel=1 is used to select the second selection ends of the first data selector mux1, the second data selector mux2 and the third data selector mux3, that is, when sel=0, the first data selector mux1, the second data selector mux2 and the third data selector mux3 select the data corresponding to the first selection ends thereof, and when sel=1, the first data selector mux1, the second data selector mux2 and the third data selector mux3 select the data corresponding to the second selection ends thereof, as shown in fig. 3.
With continued reference to fig. 3, when the input data x (n) is low-pass data, the selection signal sel is 1, and the first data selector mux1 selects the low-pass filter parameter a i Multiplied by the input data x (n), and the multiplication result is stored in a first register R A At this time, the reconstruction unit convolves the data of the data input port with the first register R in the reconstruction unit A The stored data in the second register R is added, and the added result is stored in the second register R B And output on the next clock cycle. When the input data x (n) is high-pass data, the selection signal sel is 0, and the first data selector mux1 selects the high-pass filter parameter b i Multiplied by the input data x (n), the multiplication result is multiplied by a first register R A The data of the last clock cycle stored in (a) are added and the added result is stored in a first register R A At this time, the first register R A The data of the data input port is convolved by the reconstruction unit as output data of the reconstruction unit, and is output in the next clock cycle. It should be noted that, in the structure of fig. 3, the data selection signal sel in the first input reconstruction acceleration circuit is 1, and the corresponding first selector selects the low-pass filtering parameter, so that the data stream input to the circuit is the data stream starting with the low-pass data, as shown in fig. 4.
In the present invention, the bit widths of the multiplier, adder and register are changed with the bit widths of the input data, the bit widths of the parameters a, b and the calculation required precision. The data selection signal sel serves as a control signal to simultaneously control the data selection of the three data selectors. The selection of the parameters a, b is controlled in the first data selector, and the multiplication of the corresponding data and parameters is completed. And finishing the selection of the register data and 0 in the first register of the previous clock period in the second data selector, finishing the selection of whether the integration function is started in the time domain, and storing the calculation result in the first register. In the third data selector, the selection of whether the addition function of the calculation result of the previous stage and the calculation result of the current stage is started or not is completed by selecting 0 or the calculation result in the first register, and the selection is stored in the second register.
The circuit completes the sharing of the parameters and data by the multiplier and the adder. The classification processing and addition of the classification data are completed. A multiplier and two adders are consumed altogether, and even if a part of the data selection circuit is considered, the circuit area is greatly reduced compared with the scheme of the traditional multichannel calculation. The overall delay is 2 clock cycles from the data input to the final data output.
As shown in fig. 5, the input data are x1, x2, x3, x4 and … …, respectively, for a circuit with a wavelet base length of 6, wherein the odd-numbered data corresponds to the output of the low-pass filter and the even-numbered data corresponds to the output of the high-pass filter. The corresponding reconstruction filter coefficients are the low-pass filter parameters { a1, a2, a3, a4, a5, a6} and the high-pass filter parameters { b1, b2, b3, b4, b5, b6}, respectively. Wherein conv6 to conv2 are data outputs of the sixth reconstruction unit to the second reconstruction unit. Conv is the overall output. The specific operation of the circuit in the wavelet reconstruction process is shown in table 1, the final output data is shown in table 2, the corresponding timing chart is shown in fig. 6, wherein the values of a and b in fig. 6 refer to the numerical values in table 1. When the data selection signal sel=1, the a parameter is selected and multiplied by the input data and stored in the first register R A Is a kind of medium. At the same time, a first register R A Is selected and added to the previous convolution result and stored in a second register R B And output at the next clock cycle. When sel=0, the b parameter is selected, multiplied by the input data, and the multiplied result is registered with the first register R A Is added to the data stored in the first register R A Is a kind of medium. First register R A The data in (a) is not selected, and the convolution input of the previous stage is directly taken as the final result and output in the next clock cycle.
Table 1 specific calculation results of wavelet base with length 6 in data reconstruction process
TABLE 2 output data of wavelet base with length 6 in data reconstruction process
| | output |
| x1 | |
| 0 | |
| x2 | a1*x1+b1*x2 |
| x3 | a2*x2+b2*x2 |
| x4 | a3*x1+a1*x3+b3*x2+b1*x4 |
| x5 | a4*x1+a2*x3+b4*x2+b2*x4 |
| x6 | a5*x1+a3*x3+a1*x5+b5*x2+b3*x4+b1*x6 |
| x7 | a6*x1+a4*x3+a2*x5+b6*x2+b4*x4+b2*x6 |
| x8 | a5*x3+a3*x5+a1*x7+b5*x4+b3*x6+b1*x8 |
| x9 | a6*x3+a4*x5+a2*x7+b6*x3+b4*x6+b2*x8 |
| x10 | a5*x5+a3*x7+a1*x9+b5*x6+b3*x8+b1*x10 |
| x11 | a6*x5+a4*x7+a2*x9+b6*x6+b4*x8+b2*x10 |
| x12 | a5*x7+a3*x9+a1*x11+b5*x8+b3*x10+b1*x12 |
| x13 | a6*x7+a4*x9+a2*x11+b6*x8+b4*x10+b2*x12 |
| …… | …… |
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the structure and details of the invention which may be regarded as equivalents thereof are intended to be included within the scope of the invention as defined in the following claims.
Claims (8)
1. The wavelet reconstruction accelerating circuit is characterized by comprising m reconstruction units, wherein the reconstruction units comprise a data input port, a data selection signal input port, a high-pass filtering parameter input port, a low-pass filtering parameter input port, a convolution data input port and an output port, the data input port inputs data x (n), the data selection signal input port inputs a data selection signal sel, the m reconstruction unit is an initial reconstruction unit, and the input data of the corresponding convolution data input port is 0; the 1 st reconstruction unit is a termination reconstruction unit, and the corresponding output port outputs the reconstruction data of the reconstruction acceleration circuit; the low-pass filtering parameter input port inputs low-pass filtering parameters, and the high-pass filtering parameter input port inputs high-pass filtering parameters; the output port of the reconstruction unit is connected with the convolution data input port of the next reconstruction unit; m is the length of the wavelet base, and 2 is less than or equal to m.
2. The wavelet reconstruction acceleration circuit of claim 1, wherein said reconstruction unit further comprises a multiplier, a first adder, a second adder, a first data selector, a second data selector, a third data selector, a first register, and a second register, wherein the selection of the high-pass filtering parameter and the low-pass filtering parameter is accomplished in the first data selector, and multiplied with the input data; the selection of the data and 0 in the first register at the last clock period is completed in the second data selector, and the addition result is stored in the first register, the selection of the addition result and 0 is completed in the third data selector, and the addition result is added again with the data of the data input port of the reconstruction unit, and the addition result is stored in the second register as the output data of the reconstruction unit.
3. The wavelet reconstruction acceleration circuit of claim 2, wherein two selection ends of the first data selector are respectively connected with a high-pass filtering parameter and a low-pass filtering parameter, an output end of the first data selector is connected with a second input port of the multiplier, the input data x (n) is connected with a first input port of the multiplier, an output port of the multiplier is connected with a first input port of the first adder, an output port of the first adder is connected with an input port of a first register, an output port of the first register is simultaneously connected with one selection end of a second data selector and a third selector, the other selection ends of the second data selector and the third selector are connected with 0, an output port of the second data selector is connected with a second input port of the first adder, an output port of the second adder is a convolution data input port of the reconstruction unit, and an output port of the second adder is connected with an output port of the second register; the data selection signal sel is connected with the enabling input ends of the first data selector, the second data selector and the third data selector at the same time, wherein when 0 is selected in the second data selector, the third data selector selects the data output by the output end of the first register.
4. A wavelet reconstruction acceleration circuit according to claim 3, wherein the output port of said first register is connected to both the first selection terminal of the second data selector and the second selection terminal of the third data selector, and the input data of the second selection terminal of the second data selector and the first selection terminal of the third data selector is 0.
5. The wavelet reconstruction acceleration circuit of claim 4, wherein when said data selection signal sel is 0, said second data selector and said third data selector are controlled to each select the data connected to the first selection terminal, said first data selector selects either the high-pass filter parameter or the low-pass filter parameter, said input data is either the high-pass data or the low-pass data corresponding to said first data selector, and said data selection signal sel inputted into said reconstruction acceleration circuit for the first time is 1.
6. The wavelet reconstruction acceleration circuit of claim 4, wherein when said data selection signal sel is 0, said second data selector and third data selector are controlled to select the data connected to their second selection terminals, said first data selector selects either a high-pass filter parameter or a low-pass filter parameter, said input data is either high-pass data or low-pass data corresponding to said first data selector, and said data selection signal sel inputted into said reconstruction acceleration circuit for the first time is 0.
7. A wavelet reconstruction acceleration circuit according to claim 2 wherein said output data corresponding to said input data x (n) is delayed by two clock cycles.
8. A wavelet reconstruction acceleration circuit according to claim 1, wherein the low-pass input data and the high-pass input data in said input data x (n) are staggered.
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