CN109655667A - The test method and device of silicon chip edge resistance after etching - Google Patents
The test method and device of silicon chip edge resistance after etching Download PDFInfo
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- CN109655667A CN109655667A CN201811536491.6A CN201811536491A CN109655667A CN 109655667 A CN109655667 A CN 109655667A CN 201811536491 A CN201811536491 A CN 201811536491A CN 109655667 A CN109655667 A CN 109655667A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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Abstract
The test method and device of silicon chip edge resistance after a kind of etching provided in an embodiment of the present invention, this method inputs default electric signal by the test point of the front surface of silicon wafer after etching, and the electric signal of output is obtained in the test point of the back surface away from front surface, to calculate the edge resistance of silicon wafer after etching according to the electric signal for presetting electric signal and output.The test method and device of silicon chip edge resistance after a kind of etching provided in an embodiment of the present invention, can test the silicon wafer after all etchings, improve the accuracy of testing efficiency and test data, and then improve production efficiency and product yield.
Description
Technical field
The present embodiments relate to a kind of tests of silicon chip edge electricity group behind Data Detection Technology field more particularly to etching
Method and device.
Background technique
Solar battery is the device that electric energy is directly converted optical energy by photoelectric effect.Wherein, solar battery root
It can be divided into according to material therefor difference: silicon solar cell, multicomponent compound film solar battery, polymer multi-layer modified electrode
Type solar battery, nano-crystalline solar battery, organic solar batteries, plastic solar cell, wherein silicon solar cell
It is that current development is most mature, occupies leading position in the application.
Currently, silicon solar cell includes crystal silicon solar energy battery and non-crystal silicon solar cell.Wherein, crystalline silicon is too
Positive energy battery can be divided into monocrystalline silicon battery and polycrystal silicon cell again.The step of preparation process of crystal silicon solar energy battery includes: clear
It washes, making herbs into wool, diffusion, etching edge, plated film, printing, sintering, cell slice test etc..However, etching is crystal silicon solar energy battery
An important procedure in production process, this is because the conduction type of the peripheral surface of silicon wafer changes in diffusion process,
By the PN junction of etching removal silicon chip edge and the phosphorosilicate glass layer on cleaning silicon chip surface, silicon wafer front surface and back table can be avoided
Short circuit occurs when face is powered.To verify the effect etched, in the prior art, by manually taking out silicon from discharging end in the set time
Piece tests silicon wafer using ammeter, to determine whether silicon wafer is qualified.
But by way of manually piece being taken to inspect silicon wafer by random samples, monitoring data amount is few, and there are missed detection risks.Meanwhile
It manually takes piece to will cause wafer contamination, be crushed, the silicon wafer for the test for carrying out silicon chip edge resistance is caused to be required to carry out place of doing over again
Reason, to increase manufacturing cost
Summary of the invention
In view of this, the embodiment of the present invention provides the test method and device of silicon chip edge electricity group after a kind of etching, it can
The detection that edge resistance is carried out to the silicon wafer after etching in crystal silicon solar energy battery manufacturing process, to judge the etching of silicon wafer
Effect sub-elects silicon wafer best in quality, in case subsequent use.
In a first aspect, the embodiment of the invention provides a kind of test methods of silicon chip edge resistance after etching, comprising:
After the etched technique of silicon wafer, the test point of the front surface of silicon wafer inputs default electric signal after etching；
Obtain the electric signal of the test point output of the back surface away from the front surface；
According to the electric signal of the default electric signal and the output, the survey of the edge resistance of silicon wafer after the etching is calculated
Try resistance value.
Optionally, the method also includes:
According to the comparison result of the test resistance value and standard resistance value, the quality of silicon wafer after the etching is determined.
Optionally, the comparison result according to the test resistance value and standard resistance value, determines silicon wafer after the etching
Quality, comprising:
When the test resistance value is greater than the standard resistance value, silicon wafer is qualified after determining the etching；
When the test resistance value is less than the standard resistance value, silicon wafer is abnormal after determining the etching.
Optionally, it when the test resistance value is less than the standard resistance value, determines after the etching after silicon wafer exception, also
Include:
Silicon wafer returns to processing procedure starting point after controlling the etching, carries out reworked processing to silicon wafer after the etching.
Optionally, when the test resistance value is greater than the standard resistance value, after determining that silicon wafer is qualified after the etching, also
Include:
Silicon wafer after the etching is controlled to circulate the subsequent processing to etching technics.
Optionally, silicon wafer is quadrangle after the etching；
The test point of the front surface includes at least eight test point positioned at the edge of the front surface；The back surface
The test point of test point and the front surface be arranged in a one-to-one correspondence.
Second aspect, the embodiment of the invention provides a kind of test devices of silicon chip edge resistance after etching, comprising:
Default electric signal input module, is used for the test of the front surface of silicon wafer after etching after the etched technique of silicon wafer
Point inputs default electric signal；
It exports electric signal and obtains module, for obtaining the telecommunications for deviating from the test point output of the back surface of the front surface
Number；
Test resistance computing module calculates the quarter for the electric signal according to the default electric signal and the output
The test resistance value of the edge resistance of silicon wafer after erosion.
Optionally, described device further include:
Silicon wafer quality determining module determines the quarter for the comparison result according to the test resistance value and standard resistance value
The quality of silicon wafer after erosion.
Optionally, the silicon wafer quality determining module is specifically used for:
When the test resistance value is greater than the standard resistance value, silicon wafer is qualified after determining the etching；It is hindered in the test
When value is less than the standard resistance value, silicon wafer is abnormal after determining the etching.
Optionally, described device further include:
Silicon wafer reworked processing module is used for when the test resistance value is less than the standard resistance value, after determining the etching
After silicon wafer exception, silicon wafer returns to processing procedure starting point after controlling the etching, carries out reworked processing to silicon wafer after the etching.
Optionally, described device further include:
Silicon wafer process circulation module, is used for when the test resistance value is greater than the standard resistance value, after determining the etching
After silicon wafer is qualified, controls silicon wafer after the etching and circulate the subsequent processing to etching technics.
Optionally, silicon wafer is quadrangle after the etching；
The test point of the front surface includes at least eight test point positioned at the edge of the front surface；The back surface
The test point of test point and the front surface be arranged in a one-to-one correspondence.
The test method and device of silicon chip edge resistance after a kind of etching provided in an embodiment of the present invention, this method by
The test point of the front surface of silicon wafer inputs default electric signal after etching, and defeated in the acquisition of the test point of the back surface away from front surface
Electric signal out, to calculate the edge resistance of silicon wafer after etching according to the electric signal for presetting electric signal and output, so as to
The edge resistance of silicon wafer after manually test etches in the prior art is solved, testing efficiency is low, test data inaccuracy, and
Easily to silicon wafer after etching at pollution, broken, and then the technical issues of influence production efficiency and product yield.The embodiment of the present invention
Default electric signal, and the telecommunications of the test electric collecting output in back surface are inputted by the front surface test point of silicon wafer after etching
Number, testing efficiency is improved so as to test the silicon wafer after all etchings with the edge resistance of silicon wafer after calculating etching
With the accuracy of test data, and then production efficiency and product yield are improved.
Detailed description of the invention
Fig. 1 be the embodiment of the present invention one provide a kind of etching after silicon chip edge resistance test method flow chart；
Fig. 2 is the flow chart of the test method of silicon chip edge resistance after a kind of etching provided by Embodiment 2 of the present invention；
Fig. 3 be the embodiment of the present invention three provide a kind of etching after silicon chip edge resistance test method flow chart；
Fig. 4 be the embodiment of the present invention four provide a kind of etching after silicon chip edge resistance test device structural block diagram；
Fig. 5 be the embodiment of the present invention five provide a kind of etching after silicon chip edge resistance test device structural block diagram.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 1 be the embodiment of the present invention one provide a kind of etching after silicon chip edge resistance test method flow chart.It should
Method is applicable to the case where detecting to the edge resistance sizes of silicon wafer after etched technique, and this method can be by the present invention
The test device of silicon chip edge resistance executes after the etching that embodiment provides, which can be used the side of software and/or hardware
Formula realizes that the device can be integrated in data acquisition or detection device, as shown in Figure 1, this method specifically includes:
After the etched technique of S110, silicon wafer, the test point of the front surface of silicon wafer inputs default electric signal after etching.
Specifically, need to be performed etching to silicon wafer when preparing solar battery using silicon wafer.This performs etching work to silicon wafer
The purpose of skill is the PN junction for removing silicon chip edge and the phosphorosilicate glass layer on cleaning silicon chip surface, before to silicon wafer after etching
When the test point on surface is passed through electric signal, the front surface test point of silicon wafer and the test point of back surface can be by not gone after etching
The PN junction removed links together, and the test point for being equivalent to front surface test point and back surface is linked together by a conducting wire, into
And generate short circuit phenomenon.When silicon wafer be powered occur short circuit when, have biggish electric current and flow through silicon wafer, at this time the resistance of silicon wafer compared with
It is small.Therefore, it is tested by the edge resistance to silicon wafer after etching, is able to reflect out the etching effect of etching technics.Silicon wafer
After etched technique, the front surface of silicon wafer chooses test point after etching, which can be for example silicon chip edge after etching
Any one or more points, and the test point that the input of default electric signal is selected.
Wherein, silicon wafer is chosen as quadrangle after etching, and the test point that silicon wafer front surface is chosen after etching can be uniform
It is distributed in multiple test points on four sides of quadrangle.Illustratively, after the etched technique of silicon wafer, the front surface of silicon wafer after etching
Edge choose 8 test points, and 8 test points are uniformly distributed the edge with front surface, and by preset voltage signal U or
Current signal I inputs 8 test points respectively.
The electric signal that S120, the test point for obtaining the back surface away from the front surface export.
Specifically, the default electric signal can be from quarter after inputting default electric signal to the test point of silicon wafer front surface after etching
The back surface away from front surface of silicon wafer exports after erosion.The back surface of silicon wafer chooses corresponding test point after etching, and obtaining should
The electric signal of the test point output of back surface.Wherein, the test point of back surface can be one or more.In example as above, etching
Silicon wafer is chosen as quadrangle afterwards, and the test point of front surface may include at least eight at the edge of silicon wafer front surface after etching
Test point.Test point away from the back surface of front surface can be arranged in a one-to-one correspondence with the test point of front surface.I.e. when by default electricity
When signal inputs 8 test points of front surface respectively, 8 telecommunications of 8 test points output of back surface corresponding position can be obtained
Number.
S130, according to the electric signal of the default electric signal and the output, calculate the edge electricity of silicon wafer after the etching
The test resistance value of resistance.
Specifically, the resistance of resistance can be calculated by known current value and voltage value according to Ohm's law I=U/R
Value.The default electric signal of silicon wafer front surface test point is predeterminated voltage signal or predetermined current signal, output after inputting etching
Etching after silicon wafer back surface test point output electric signal be output current signal or output voltage signal when, pass through
The predetermined current signal or predeterminated voltage signal of input combine the voltage signal or current signal of output, calculate silicon wafer after etching
Edge resistance test resistance value.
Illustratively, the test point of silicon wafer front surface inputs predeterminated voltage signal Uo, and silicon wafer after etching after etching
The current signal Io of the test point detection output of back surface can calculate the edge resistance of silicon wafer according to Ohm's law I=U/R
Resistance value Ro:
Calculated edge resistance resistance value Ro be edge resistance test resistance value.
In addition, can also be by providing a power supply for silicon wafer after etching, which has fixed voltage value U1, and will etching
The test point of silicon wafer front surface and the test point of back surface are formed into a loop afterwards, the current value I1 in the circuit are tested, according to ohm
Law I=U/R can calculate the resistance value Ro of the edge resistance of silicon wafer:
Calculated edge resistance resistance value Ro be edge resistance test resistance value.
The embodiment of the present invention inputs default electric signal by the front surface test point of silicon wafer after etching, and in back surface
The electric signal of electric collecting output is tested, with the edge resistance of silicon wafer after calculating etching, so as to the silicon wafer after all etchings
It is tested, improves the accuracy of testing efficiency and test data, and then improve production efficiency and product yield.
Embodiment two
Fig. 2 is the flow chart of the test method of silicon chip edge resistance after a kind of etching provided by Embodiment 2 of the present invention.This
Embodiment is optimized on the basis of the above embodiments, and provide preferred further includes carving on the basis of the above embodiments
After erosion silicon wafer quality determine method, specifically: according to it is described test resistance value and standard resistance value comparison result, determine described in
The quality of silicon wafer after etching.As shown in Fig. 2, the method for the present embodiment includes:
After the etched technique of S210, silicon wafer, the test point of the front surface of silicon wafer inputs default electric signal after etching；
The electric signal that S220, the test point for obtaining the back surface away from the front surface export；
S230, according to the electric signal of the default electric signal and the output, calculate the edge electricity of silicon wafer after the etching
The test resistance value of resistance；
S240, according to it is described test resistance value and standard resistance value comparison result, determine the quality of silicon wafer after the etching.
Specifically, during preparing solar battery using silicon wafer, it, should be by the PN junction at edge after the etched technique of silicon wafer
And the phosphorosilicate glass layer removal on surface.If the PN junction of silicon chip edge does not remove after etching, the preceding table of silicon wafer after to etching
When the test point in face is passed through electric signal, the front surface test point of silicon wafer and the test point of back surface can be by not being removed after etching
PN junction link together, the test point for being equivalent to front surface test point and back surface is linked together by a conducting wire, thus
Short circuit phenomenon will be will appear.At this point, the resistance value of the edge resistance of silicon wafer is smaller after etching.It can be hindered as a result, by one standard of setting
Value, the test resistance value of the edge resistance of silicon wafer after etching is compared with standard resistance value, to determine silicon wafer after the etching
Etching effect.
Default electric signal is inputted by the test point of the front surface of silicon wafer after etching, such as can be predeterminated voltage signal
Or predetermined current signal, and the electric signal of the test point detection output of the back surface of silicon wafer after etching, the telecommunications of the output
It can be number for example the current signal or voltage signal of output.According to the test point of silicon wafer front surface input default electric signal and
The electric signal of back surface output, calculates the test resistance value of the edge resistance of silicon wafer after the etching.By edge resistance calculated
Test resistance value be compared with standard resistance value, according to silicon wafer after the comparison result of the test resistance value and standard resistance value judgement etching
Etching effect, with determine etching after silicon wafer quality.
Optionally, when the test resistance value is greater than the standard resistance value, silicon wafer is qualified after determining the etching；Described
When testing resistance value less than the standard resistance value, silicon wafer is abnormal after determining the etching.
Specifically, the resistance value of silicon wafer is larger after the etching, to silicon wafer after etching when testing resistance value greater than standard resistance value
When front surface test point and the test point of back surface are powered, not formed short circuit, silicon wafer has good quarter after judging the etching
Effect is lost, silicon wafer is qualified products after determining etching；When testing resistance value less than standard resistance value, to the preceding table of silicon wafer after etching
When face test point and the test point of back surface are powered, it is possible to create short circuit judges the etching effect of silicon wafer after the etching not
It is good, it is possible to there is the PN junction not being etched away, silicon wafer is abnormal products after determining etching, will affect the system of subsequent finished product
It is standby.
Illustratively, when multiple test points of the front surface of silicon wafer after etching each lead into default electric signal, etching
The correspondence test point of the back surface of silicon wafer will test out the electric signal of multiple outputs afterwards, respectively according to the test point of each front surface
The electric signal of the output of the test point of the default electric signal and back surface of input, calculates the corresponding edge resistance of each test point
Test resistance value.The test resistance value of the corresponding edge resistance of each test point is compared with standard resistance value respectively, is obtained each
The comparison result of a test resistance value and standard resistance value judges the etching when any test resistance value is less than standard resistance value
The etching effect that silicon wafer has afterwards is bad, it is possible to there is the PN junction not being etched away, silicon wafer produces after determining etching to be abnormal
Product.Wherein, the size of the standard resistance value is chosen as 1K Ω.
The present embodiment, according to comparison result, is sentenced by being compared the test resistance value of silicon wafer after etching with standard resistance value
Disconnected etching effect, determines the quality of silicon wafer after etching, thus prevent from preparing device using silicon wafer after undesirable etching, it can be into one
Step improves production efficiency and product yield.
Embodiment three
Fig. 3 be the embodiment of the present invention three provide a kind of etching after silicon chip edge resistance test method flow chart.This
Embodiment is optimized on the basis of the above embodiments, provides and preferably increases on the basis of the above embodiments
Judge after etching after the quality of silicon wafer, the method for determining silicon wafer whereabouts after etching, specifically: it is less than institute in the test resistance value
When stating standard resistance value, determine that silicon wafer returns to processing procedure starting point after controlling the etching, right after the etching after silicon wafer exception
Silicon wafer carries out reworked processing after the etching；Alternatively, determining the etching when the test resistance value is greater than the standard resistance value
After silicon wafer is qualified afterwards, controls silicon wafer after the etching and circulate the subsequent processing to etching technics.As shown in figure 3, this implementation
Example method include:
After the etched technique of S310, silicon wafer, the test point of the front surface of silicon wafer inputs default electric signal after etching；
The electric signal that S320, the test point for obtaining the back surface away from the front surface export；
S330, according to the electric signal of the default electric signal and the output, calculate the edge electricity of silicon wafer after the etching
The test resistance value of resistance；
S340, judge whether the test resistance value is greater than the standard resistance value；If so, sequence executes S350 and S360；
If it is not, then sequence executes S370 and S380；
S350, silicon wafer qualification after the etching is determined；
Silicon wafer circulates the subsequent processing to etching technics after S360, the control etching.
Specifically, inputting default electric signal, and silicon after etching by the test point of the front surface of silicon wafer after etching
The back surface of piece test point detection output electric signal, and according to the test point of silicon wafer front surface input default electric signal and
The electric signal of back surface output, calculates the test resistance value of the edge resistance of silicon wafer after the etching.By edge resistance calculated
Test resistance value be compared with standard resistance value, when testing resistance value and being greater than standard resistance value, the resistance value of silicon wafer is larger after the etching,
When the test point of front surface test point and back surface to silicon wafer after etching is powered, silicon after the etching is judged in not formed short circuit
Piece has good etching effect, and silicon wafer is qualified products after determining etching, and the silicon wafer after etching directly can circulate at this time
Silicon wafer after qualified etching is prepared as corresponding device by the subsequent processing after to etching.The side of silicon wafer after circulation etching
Formula for example can be to be picked up using manipulator, or pass through conveyer belt and transmit.
Illustratively, after testing the edge resistance of silicon wafer after the etching for preparing solar battery, after the etching
When the test resistance value of silicon wafer is greater than standard resistance value, silicon wafer is qualified products after determining etching, at this point, silicon wafer after etching can be used
Continue the processing steps such as plated film, printing, sintering, cell slice test, until silicon wafer is prepared as solar battery sheet.
S370, silicon wafer exception after the etching is determined；
Silicon wafer returns to processing procedure starting point after S380, the control etching, carries out reworked processing to silicon wafer after the etching.
Specifically, inputting default electric signal, and silicon after etching by the test point of the front surface of silicon wafer after etching
The back surface of piece test point detection output electric signal, and according to the test point of silicon wafer front surface input default electric signal and
The electric signal of back surface output, calculates the test resistance value of the edge resistance of silicon wafer after the etching.By edge resistance calculated
Test resistance value be compared with standard resistance value, test resistance value be less than standard resistance value when, to after etching silicon wafer front surface survey
When pilot and the test point of back surface are powered, it is possible to create short circuit judges silicon wafer has after the etching etching effect not
It is good, it is possible to there is the PN junction not being etched away, silicon wafer is abnormal products after determining etching, will affect the system of subsequent finished product
It is standby, need the silicon wafer after etching to carry out reworked processing at this time.Before carrying out reworked processing, first silicon wafer after etching can be carried out clear
It washes, so that silicon wafer reverts to the silicon wafer before preparation process after etching.
Illustratively, after testing the edge resistance of silicon wafer after the etching for preparing solar battery, after the etching
When the test resistance value of silicon wafer is less than standard resistance value, silicon wafer is abnormal products after determining etching, at this point, can be to silicon wafer after the etching
Reworked processing is carried out, silicon wafer after etching is cleaned again, after silicon chip surface making herbs into wool after etching and diffusion layer removal, again
Making herbs into wool, diffusion and etching are carried out to silicon wafer.
After silicon wafer carries out reworked processing after to etching, the resistance value that can carry out edge resistance to silicon wafer after etching again is carried out
Test, rejudges the etching effect of silicon wafer after the etching, to determine the quality of silicon wafer after etching again, until judging result
It works well for the silicon chip erosion after the etching, silicon wafer is qualified products after etching, then the silicon wafer after the etching circulates under
One process.Alternatively, the test resistance value for the edge resistance tested shows the etching after carrying out reworked processing to silicon wafer after the etching
The etching effect of silicon wafer is bad afterwards, then silicon wafer is handled according to abnormal silicon chip after the etching after this being done over again, and flows directly out
Manufacturing process.
The present embodiment determines silicon wafer after etching by the way that the test resistance value of silicon wafer after etching to be compared with standard resistance value
Quality, and when silicon wafer is qualified after etching, silicon wafer after etching is circulated to subsequent processing；Alternatively, silicon wafer is after etching
When abnormal, reworked processing is carried out to silicon wafer after etching, so as to before improving the accuracy of testing efficiency and test data
It puts, improves the utilization rate of silicon wafer, and then improve production efficiency and product yield.
Example IV
Fig. 4 be the embodiment of the present invention four provide a kind of etching after silicon chip edge resistance test device structural block diagram.
The device is suitable for the case where detecting to the edge resistance sizes of silicon wafer after etched technique, which can be used software
And/or the mode of hardware is realized, which can be integrated in data acquisition or detection device, as shown in figure 4, the device includes:
Default electric signal input module 10, output electric current obtain module 20 and test resistance computing module 30.
The default electric signal input module 10 is used for after the etched technique of silicon wafer, after etching the front surface of silicon wafer
Test point input default electric signal；
The output electric signal obtains module 20, what the test point for obtaining the back surface away from the front surface exported
Electric signal；
The test resistance computing module 30 is calculated for the electric signal according to the default electric signal and the output
The test resistance value of the edge resistance of silicon wafer after the etching.
The present embodiment inputs default electric signal by the front surface test point of silicon wafer after etching, and in the test of back surface
The electric signal of electric collecting output, with the edge resistance of silicon wafer after calculating etching, so as to be carried out to the silicon wafer after all etchings
Test improves the accuracy of testing efficiency and test data, and then improves production efficiency and product yield.
Embodiment five
Fig. 5 be the embodiment of the present invention five provide a kind of etching after silicon chip edge resistance test device structural block diagram.
The present embodiment is optimized on the basis of the above embodiments, as shown in figure 5, on the basis of the above embodiments, the dress
It sets further include: silicon wafer quality determining module 40.
The silicon wafer quality determining module 40 is determined for the comparison result according to the test resistance value and standard resistance value
The quality of silicon wafer after the etching.
Optionally, the silicon wafer quality determining module 40 is specifically used for being greater than the standard resistance value in the test resistance value
When, silicon wafer is qualified after determining the etching；When the test resistance value is less than the standard resistance value, silicon wafer after the etching is determined
It is abnormal.
Optionally, described device further include: silicon wafer reworked processing module 50.
The silicon wafer reworked processing module 50, described in determining when the test resistance value is less than the standard resistance value
After etching after silicon wafer exception, silicon wafer returns to processing procedure starting point after controlling the etching, returns to silicon wafer after the etching
Work processing.
Optionally, described device further include: silicon wafer process circulation module 60.
The silicon wafer process circulation module 60, described in determining when the test resistance value is greater than the standard resistance value
After silicon wafer is qualified after etching, controls silicon wafer after the etching and circulate the subsequent processing to etching technics.
Optionally, silicon wafer is quadrangle after the etching；The test point of the front surface includes being located at the front surface
At least eight test point at edge；The test point of the back surface and the test point of the front surface are arranged in a one-to-one correspondence.
The test device of silicon chip edge resistance after a kind of etching provided in an embodiment of the present invention, after realizing to etching technics,
The edge resistance of silicon wafer is tested after etching, to judge the etching effect of silicon wafer, sub-elects silicon wafer best in quality, in case after
It is continuous to use.
The test device of silicon chip edge resistance is for executing described in the various embodiments described above after etching described in the present embodiment
The test method of silicon chip edge resistance after etching, technical principle is similar with the technical effect of generation, and which is not described herein again.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (12)
1. the test method of silicon chip edge resistance after a kind of etching characterized by comprising
After the etched technique of silicon wafer, the test point of the front surface of silicon wafer inputs default electric signal after etching；
Obtain the electric signal of the test point output of the back surface away from the front surface；
According to the electric signal of the default electric signal and the output, the test resistance of the edge resistance of silicon wafer after the etching is calculated
Value.
2. the method according to claim 1, wherein further include:
According to the comparison result of the test resistance value and standard resistance value, the quality of silicon wafer after the etching is determined.
3. according to the method described in claim 2, it is characterized in that, the comparison according to the test resistance value and standard resistance value
As a result, determining the quality of silicon wafer after the etching, comprising:
When the test resistance value is greater than the standard resistance value, silicon wafer is qualified after determining the etching；
When the test resistance value is less than the standard resistance value, silicon wafer is abnormal after determining the etching.
4. according to the method described in claim 3, it is characterized in that, the test resistance value be less than the standard resistance value when, really
After the fixed etching after silicon wafer exception, further includes:
Silicon wafer returns to processing procedure starting point after controlling the etching, carries out reworked processing to silicon wafer after the etching.
5. according to the method described in claim 3, it is characterized in that, the test resistance value be greater than the standard resistance value when, really
After silicon wafer is qualified after the fixed etching, further includes:
Silicon wafer after the etching is controlled to circulate the subsequent processing to etching technics.
6. described in any item methods according to claim 1~5, which is characterized in that silicon wafer is quadrangle after the etching；
The test point of the front surface includes at least eight test point positioned at the edge of the front surface；The survey of the back surface
The test point of pilot and the front surface is arranged in a one-to-one correspondence.
7. the test device of silicon chip edge resistance after a kind of etching characterized by comprising
Default electric signal input module, for after the etched technique of silicon wafer, the test point of the front surface of silicon wafer to be defeated after etching
Enter default electric signal；
It exports electric signal and obtains module, for obtaining the electric signal for deviating from the test point output of the back surface of the front surface；
Test resistance computing module, for the electric signal according to the default electric signal and the output, after calculating the etching
The test resistance value of the edge resistance of silicon wafer.
8. device according to claim 7, which is characterized in that further include:
Silicon wafer quality determining module, for the comparison result according to the test resistance value and standard resistance value, after determining the etching
The quality of silicon wafer.
9. device according to claim 8, which is characterized in that the silicon wafer quality determining module is specifically used for:
When the test resistance value is greater than the standard resistance value, silicon wafer is qualified after determining the etching；It is small in the test resistance value
When the standard resistance value, silicon wafer is abnormal after determining the etching.
10. device according to claim 9, which is characterized in that further include:
Silicon wafer reworked processing module, for determining silicon wafer after the etching when the test resistance value is less than the standard resistance value
After exception, silicon wafer returns to processing procedure starting point after controlling the etching, carries out reworked processing to silicon wafer after the etching.
11. device according to claim 9, which is characterized in that further include:
Silicon wafer process circulation module, for determining silicon wafer after the etching when the test resistance value is greater than the standard resistance value
After qualification, controls silicon wafer after the etching and circulate the subsequent processing to etching technics.
12. according to the described in any item devices of claim 7~11, which is characterized in that silicon wafer is quadrangle after the etching；
The test point of the front surface includes at least eight test point positioned at the edge of the front surface；The survey of the back surface
The test point of pilot and the front surface is arranged in a one-to-one correspondence.
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