CN109643688A - 半导体集成电路装置 - Google Patents
半导体集成电路装置 Download PDFInfo
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- CN109643688A CN109643688A CN201780045986.6A CN201780045986A CN109643688A CN 109643688 A CN109643688 A CN 109643688A CN 201780045986 A CN201780045986 A CN 201780045986A CN 109643688 A CN109643688 A CN 109643688A
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Abstract
对采用了纳米线FET的半导体集成电路装置提供一种对制造的容易化有效的版图结构。布置有标准单元(C2),标准单元(C2)与具有逻辑功能的标准单元(C1)相邻且不具有逻辑功能。标准单元(C1)具有纳米线FET(P11、P12、N11、N12),纳米线FET(P11、P12、N11、N12)具有纳米线(11、12、13、14)和焊盘(21、22、23、24、25、26),标准单元(C2)具有虚设焊盘(51、52、53、54),虚设焊盘(51、52、53、54)对电路的逻辑功能不做贡献。
Description
技术领域
本公开涉及一种包括采用了纳米线FET(场效应晶体管:Field EffectTransistor)的标准单元(以下,有时也简称为单元)的半导体集成电路装置。
背景技术
已知:作为在半导体衬底上形成半导体集成电路的方法有标准单元方式。标准单元方式指的是以下方式,即事先将具有特定逻辑功能的基本单元(例如反相器、锁存器、触发器、全加器等)作为标准单元准备好,然后将多个标准单元布置在半导体衬底上,再用布线将这些标准单元连接起来,这样来设计LSI芯片的一种方式。
LSI的基本构成要素即晶体管通过缩小栅极长度(scaling,按比例缩小)而实现了集成度的提高、工作电压的降低以及工作速度的提高。但是,近年来,出现的问题是过度地按比例缩小会引起截止电流和功耗显著增大。为了解决该问题,人们已开始积极对立体构造晶体管进行研究,即将晶体管构造从现有的平面型变为立体型。作为立体构造晶体管之一,纳米线FET备受瞩目。
非专利文献1、2中公开了纳米线FET的制造方法之例。
非专利文献1:S.Bangsaruntip,et al.“High performance and highly uniformgate-all-around silicon nanowire MOSFETs with wire size dependent scaling”,Electron Devices Meeting(IEDM),2009IEEE International
非专利文献2:Isaac Laucer,et al.“Si Nanowire CMOS Fabricated withMinimal Deviation from RMG Fin FET Technology Showing Record Performance”,2015Symposium on VLSI Technology Digest of Technical Papers
发明内容
-发明要解决的技术问题-
到目前为止,还没有人对采用了纳米线FET的标准单元的构造、采用了纳米线FET的半导体集成电路的版图(layout)做具体的研究。
本公开涉及一种采用了纳米线FET的半导体集成电路装置,提供对制造的容易化有效的版图结构。
-用以解决技术问题的技术方案—
本公开的第一方面是一种半导体集成电路装置,具有第一标准单元和第二标准单元,所述第一标准单元具有纳米线FET(Field Effect Transistor,场效应晶体管)且具有逻辑功能,所述第二标准单元在第一方向上与所述第一标准单元相邻布置且不具有逻辑功能,所述纳米线FET具有:沿所述第一方向延伸的一条或并排设置的多条纳米线;以及一对焊盘,一对所述焊盘分别设在所述纳米线的所述第一方向上的两端,且下表面位于比所述纳米线的下表面低的位置上,并与所述纳米线相连,所述第二标准单元具有虚设焊盘,所述虚设焊盘为对电路的逻辑功能不做贡献的焊盘。
根据上述方面,布置有第二标准单元,其与具有逻辑功能的第一标准单元相邻且不具有逻辑功能。第一标准单元具有纳米线FET,纳米线FET具有纳米线和焊盘,第二标准单元具有对电路的逻辑功能不做贡献的焊盘即虚设焊盘。因此,在第一标准单元和第二标准单元中,能够规律地布置焊盘和虚设焊盘。这样一来,就能够抑制半导体集成电路装置的制造偏差,并能够提高成品率。
-发明的效果-
根据本公开,就采用了纳米线FET的半导体集成电路装置而言,既能够抑制制造偏差、性能偏差,又能够提高成品率。
附图说明
图1是俯视图,示出实施方式所涉及的半导体集成电路装置所具有的电路块的版图例子。
图2是俯视图,示出实施方式的标准单元的版图结构。
图3是图2的标准单元的剖视图。
图4(a)~(c)是俯视图,示出填充单元的单元宽度的变形例(variation)。
图5是俯视图,示出实施方式的标准单元的其他版图结构。
图6是俯视图,示出实施方式的标准单元的其他版图结构。
图7是俯视图,示出实施方式的标准单元的其他版图结构。
图8是俯视图,示出采用了虚设焊盘的电容单元的版图结构。
图9示出采用了虚设焊盘的电容单元的其他结构例,(a)是示出版图结构的俯视图,(b)是剖视图。
图10是俯视图,示出采用了虚设焊盘的电容单元的其他版图结构。
图11示出采用了虚设焊盘的电容单元的其他结构例,(a)是示出版图结构的俯视图,(b)是剖视图。
图12(a)、(b)是俯视图,示出采用了虚设焊盘的电容单元的其他版图结构。
图13(a)、(b)是俯视图,示出将图12的结构的单元宽度扩大后的变形例。
图14是图2的标准单元的版图结构的变形例。
图15是示意图,示出纳米线FET的基本构造。
图16是示意图,示出纳米线FET的基本构造。
具体实施方式
下面,参照附图对实施方式进行说明。在以下实施方式中,半导体集成电路装置包括多个标准单元,上述的多个标准单元中的至少一部分标准单元包括纳米线FET(FieldEffect Transistor)。
图15是示意图,示出纳米线FET的基本构造例子(也称为栅绕式(GAA:Gate AllAround)FET)。纳米线FET是使用了供电流流动的细线(纳米线)的FET。纳米线例如由硅形成。如图15所示,纳米线在衬底上沿着水平方向延伸,即平行于衬底延伸,其两端连接在成为纳米线FET的源极区和漏极区的构造物上。在本申请说明书中,将纳米线FET中连接在纳米线的两端上且成为纳米线FET的源极区和漏极区的构造物称为焊盘(pad)。图15中,在硅衬底上形成有STI(Shallow Trench Isolation,浅沟道隔离),硅衬底在纳米线的下方(加了斜线的部分)露出。需要说明的是,实际存在加了斜线的部分被热氧化膜等覆盖的情况,但在图15中,为了简化而省略图示热氧化膜等。
纳米线的周围被例如由多晶硅形成的栅极电极围绕一圈,在纳米线与栅极电极之间设置有氧化硅膜等绝缘膜。焊盘和栅极电极形成在衬底的表面上。根据该构造,因为纳米线的沟道区的上部、两侧部以及下部全被栅极电极围起来,所以能够在沟道区产生均匀的电场,由此,FET的开关特性良好。
需要说明的是,焊盘中的至少连接有纳米线的部分成为源极区/漏极区,但有时候,连接有纳米线的部分之下的部分未必会成为源极区/漏极区。而且,有时候,纳米线的一部分(未被栅极电极围起来的部分)会成为源极区/漏极区。
图15中,沿纵向即与衬底垂直的方向布置有两条纳米线。不过,沿纵向布置的纳米线的条数并不限于两条,可以是一条,也可以是三条以上。图15中,最上侧的纳米线的上端与焊盘的上端高度齐平。不过,不需要将它们的高度齐平,焊盘的上端比最上侧的纳米线的上端高也无妨。
也存在图16所示的情况,即在衬底的上表面上形成有BOX(Buried Oxide,隐埋氧化物),并在该BOX上形成有纳米线FET。
(实施方式)
图1是俯视图,示出实施方式所涉及的半导体集成电路装置所具有的电路块的版图例子。在图1的版图中,沿X方向(附图横向,相当于第一方向)并排设置的多个单元C构成单元列CR。并且,多个单元列CR沿Y方向(附图纵向,相当于第二方向)并排布置。在多个单元C中,除了具有与非(NAND)门、或非(NOR)门等逻辑功能的单元(以下,有时称为逻辑单元)以外,还包括填充单元CFL和单元列末端单元(也称为EndCap单元)CEC。
此处,“填充单元(Filler cell)”是指下述单元,其不具有逻辑功能,对电路块的逻辑功能不做贡献,且布置在逻辑单元之间。“单元列末端单元”是指下述单元,其不具有逻辑功能,对电路块的逻辑功能不做贡献,且用于终止单元列。通过布置单元列末端单元,能够使单元列中的阱(well)区沿X方向充分地扩散开。这样一来,就能够使位于单元列末端单元的内侧的逻辑单元的晶体管远离阱区端部,避免阱区端部附近的晶体管特性的变动。
在本实施方式中,在填充单元CFL和单元列末端单元CEC中,布置有虚设焊盘5。此处,“虚设焊盘”是指对电路的逻辑功能不做贡献的焊盘,换言之,是指由与构成纳米线FET的焊盘相同的构造形成且对电路块的逻辑功能不做贡献的构造物。
需要说明的是,在图1的图示中,逻辑单元的尺寸和版图全都相同。不过,实际版图不限于此,可以布置任意的逻辑单元。
在本实施方式中,金属布线(M1)与焊盘(pad)和栅极布线(gate)的连接方式是经局部布线LI和触点进行的连接。不过,在图1中,省略了触点的图示。
(填充单元的结构)
图2是图1的W1部分的放大图,是示出本实施方式的标准单元的版图结构的俯视图。在图2中,标准单元C1具有纳米线FET,且具有逻辑功能(此处为2输入NOR)。标准单元C2是不具有逻辑功能的填充单元,在X方向上与标准单元C1相邻布置。在标准单元C1、C2中,P型半导体区PA与N型半导体区NA沿Y方向并排布置。在金属布线层M1中,布置有在标准单元C1、C2的上边上沿X方向延伸且供给电源电位VDD的布线VDD和在标准单元C1、C2的下边上沿X方向延伸且供给接地电位VSS的布线VSS。
在标准单元C1中,在P型半导体区PA设有P型纳米线FET P11、P12,在N型半导体区NA设有N型纳米线FET N11、N12。纳米线FET P11、P12串联连接,纳米线FET N11、N12并联连接。纳米线FET P11包括多条纳米线11,纳米线FET P12包括多条纳米线12,纳米线FET N11包括多条纳米线13,纳米线FET N12包括多条纳米线14,多条纳米线11、12、13、14都沿X方向延伸且并排设置。此处,纳米线11、12、13、14分别沿Y方向并排设有四条。而且,如后所述,纳米线11、12、13、14分别沿纵向即与衬底垂直的方向设有两条,故纳米线11、12、13、14分别合计为八条。纳米线11、12、13、14呈圆柱状,且在衬底上沿着水平方向延伸,即平行于衬底延伸,且例如由硅形成。在标准单元C1中,形成有与纳米线11、12、13、14连接的焊盘21、22、23、24、25、26。P型杂质注入至焊盘21、22、23中的至少与纳米线11、12连接的部分中,该部分成为纳米线FET P11、P12的源极区或漏极区。N型杂质注入至焊盘24、25、26中的至少与纳米线13、14连接的部分中,该部分成为纳米线FET N11、N12的源极区或漏极区。
此处,焊盘21、22、23、24、25、26分别在Y方向上分开形成且分别形成有四个。焊盘21的分开的四个部分分别连接在沿Y方向而设的四条纳米线11上。焊盘22的分开的四个部分分别连接在沿Y方向而设的四条纳米线11上,而且还分别连接在沿Y方向而设的四条纳米线12上。焊盘23的分开的四个部分分别连接在沿Y方向而设的四条纳米线12上。焊盘24的分开的四个部分分别连接在沿Y方向而设的四条纳米线13上。焊盘25的分开的四个部分分别连接在沿Y方向而设的四条纳米线13上,而且还分别连接在沿Y方向而设的四条纳米线14上。焊盘26的分开的四个部分分别连接在沿Y方向而设的四条纳米线14上。
串联连接的纳米线FET P11、P12共用焊盘22。也就是说,纳米线FET P11具有与纳米线11连接的焊盘21、22,纳米线FET P12具有与纳米线12连接的焊盘22、23。并联连接的纳米线FET N11、N12共用焊盘25。也就是说,纳米线FET N11具有与纳米线13连接的焊盘24、25,纳米线FET N12具有与纳米线14连接的焊盘25、26。
在标准单元C1中还布置有沿Y方向直线状延伸的两条栅极布线31、32。栅极布线31是将纳米线FET P11的栅极电极31p与纳米线N11的栅极电极31n形成为一体而得到的。栅极布线31被设为:在纳米线11、13的X方向上的规定范围内将纳米线11、13围起来。栅极布线32是将纳米线FET P12的栅极电极32p与纳米线N12的栅极电极32n形成为一体而得到的。栅极布线32被设为:在纳米线12、14的X方向上的规定范围内将纳米线12、14围起来。在标准单元C1的两个侧边上分别布置有沿Y方向延伸的虚设栅极(dummy gate)布线35、36。
在金属布线层M1中还形成有布线41a~41f。布线41a形成为从布线VDD开始沿着Y方向朝下方延伸,且经局部布线(local wiring)45a与焊盘21相连接。布线41b形成为从布线VSS开始沿着Y方向朝上方延伸,且经局部布线45b与焊盘24相连接。布线41c形成为从布线VSS开始沿着Y方向朝上方延伸,且经局部布线45c与焊盘26相连接。布线41d将焊盘23、25连接起来,且经局部布线45d与焊盘23相连接,经局部布线45e与焊盘25相连接。布线41e经局部布线45f与栅极布线31相连接。布线41f经局部布线45g与栅极布线32相连接。布线41d、41e、41f分别与2输入NOR电路的输出Y、输入A、输入B相对应。在焊盘22上形成有局部布线45h。局部布线45h连接在焊盘22上,但没有与金属布线层M1中的布线连接。
需要说明的是,此处,金属布线41a~41f与焊盘21、23、24、25、26和栅极布线31、32的连接方式是经局部布线45a、45b、45c、45d、45e、45f、45g和触点43进行连接的。不过,金属布线与焊盘和栅极布线的连接方式还可以不经触点而仅经局部布线进行连接,也可以是不经局部布线而仅经触点进行连接。
另一方面,在标准单元C2中,在P型半导体区PA设有虚设焊盘51、52,在N型半导体区NA设有虚设焊盘53、54。此处,虚设焊盘51、52、53、54分别在Y方向上分开形成且分别形成有四个。与焊盘21、22、23同样,P型杂质注入至虚设焊盘51、52,与焊盘24、25、26同样,N型杂质注入至虚设焊盘53、54。在虚设焊盘51、53与虚设焊盘52、54之间,布置有沿Y方向延伸的虚设栅极布线61。在标准单元C2的与标准单元C1相反一侧的侧边上布置有沿Y方向延伸的虚设栅极布线65。
图3是图2的III-III线的剖视图。如图3所示,金属布线层M1中的布线41a~41f经触点43与局部布线45a~45g相连接。触点43与金属布线层M1中的布线41a~41f一起利用双嵌入工艺(Dual damascene process)形成。需要说明的是,触点43和金属布线层M1中的布线41a~41f还可以各自分别形成。金属布线层M1中的布线41a~41f例如由Cu形成,在布线41a~41f的表面上形成有例如含有钽或氮化钽的阻挡金属(Barrier metal)48。局部布线45a~45g例如由钨形成,在局部布线45a~45g的表面上形成有例如含有钛或氮化钛的胶(glue)膜47。需要说明的是,局部布线45a~45g也可以由钴形成。在该情况下,可以不用形成胶膜47。在焊盘21~26的表面上形成有硅化物膜(silicide film)49,该硅化物膜49例如由镍或钴等形成。
层间绝缘膜46a、46b例如是氧化硅膜。层间绝缘膜46c例如是如SiOC或多孔膜等低介电常数膜。需要说明的是,层间绝缘膜46c也可以具有两层或两层以上的叠层构造。
栅极电极31p、31n、32p、32n例如由多晶硅形成。需要说明的是,栅极电极31p、31n、32p、32n也可以由氮化钛等含金属的材料形成。栅极绝缘膜例如是氧化硅膜,且例如由热氧化法形成。需要说明的是,栅极绝缘膜也可以由铪、锆、镧、钇、铝、钛或钽的氧化物形成。
由图3的剖视图可知,在N型半导体区NA,焊盘24、25、26的下表面位于比纳米线13、14的下表面低的位置上。纳米线13、14的上表面的高度与焊盘24、25、26的上表面相同。栅极电极31n、32n形成为将纳米线13、14绕一圈围起来。同样地,在P型半导体区PA,焊盘21、22、23的下表面位于比纳米线11、12的下表面低的位置上。纳米线11、12的上表面的高度与焊盘21、22、23的上表面相同。栅极电极31p、32p形成为将纳米线11、12绕一圈围起来。即,形成在纳米线11、12、13、14上的沟道区的上表面、两侧面以及下表面全部经由绝缘膜被栅极电极31p、32p,31n、32n围起来。需要说明的是,纳米线13、14的上表面也可以位于比焊盘24、25、26的上表面低的位置上,纳米线11、12的上表面也可以位于比焊盘21、22、23的上表面低的位置上。并且,在衬底的上表面上还可以形成有BOX(Buried Oxide)。
在图2的版图中,栅极布线31、32和虚设栅极布线35、36、61、65以同一中心间距Pg布置在X方向上。标准单元C1的单元宽度(在X方向上的尺寸)是栅极中心间距Pg的3倍即(Pg×3),标准单元C2的单元宽度是栅极中心间距Pg的2倍即(Pg×2)。
在图2的版图中,焊盘和虚设焊盘以同一中心间距Pp布置在X方向上。即,在P型半导体区PA,焊盘21、22、23和虚设焊盘51、52以中心间距Pp布置,在N型半导体区NA,焊盘24、25、26和虚设焊盘53、54以中心间距Pp布置。栅极布线的中心间距Pg等于焊盘的中心间距Pp。即:
Pp=Pg。
并且,焊盘和虚设焊盘在X方向上的尺寸即焊盘宽度Wp完全相同,在Y方向上的尺寸即焊盘高度Hp也完全相同。而且,在P型半导体区PA,焊盘21、22、23和虚设焊盘51、52在Y方向上的布置位置相同,在N型半导体区NA,焊盘24、25、26和虚设焊盘53、54在Y方向上的布置位置相同。
根据上述结构,布置有标准单元C2,其与逻辑单元即标准单元C1相邻,且为填充单元。标准单元C1具有纳米线FET P11、P12、N11、N12,纳米线FET P11、P12、N11、N12具有纳米线11、12、13、14和焊盘21、22、23、24、25、26,标准单元C2具有虚设焊盘51、52、53、54。通过在标准单元C2中设置虚设焊盘51......,就能够在标准单元C1、C2中规律地布置焊盘21......和虚设焊盘51......。即,通过在填充单元中设置虚设焊盘,包括虚设焊盘的焊盘的布置就会变得规律。这样一来,就能够抑制半导体集成电路装置的制造偏差,并能够提高成品率。
标准单元C1的焊盘23、26与相邻的焊盘之间的距离因存在于标准单元C2中的虚设焊盘51、53而保持规定值不变。即,通过在填充单元中设置虚设焊盘,就能够将离逻辑单元的单元端部最近的焊盘与相邻的焊盘之间的距离定为规定值。这样一来,纳米线FET的性能的估算精度就得到提高。
需要说明的是,在上述结构中,焊盘和虚设焊盘以同一中心间距Pp布置在X方向上,但不限于此。并且,焊盘和虚设焊盘在X方向上的尺寸即焊盘宽度Wp完全相同,在Y方向上的尺寸即焊盘高度Hp也完全相同,但不限于此。而且,在P型半导体区PA,焊盘和虚设焊盘在Y方向上的布置位置相同,在N型半导体区NA,焊盘和虚设焊盘在Y方向上的布置位置相同,但不限于此。
图4是俯视图,示出填充单元的单元宽度的变形例。图4中,(a)是单元宽度为栅极中心间距的1倍的填充单元,(b)是单元宽度为栅极中心间距的3倍的填充单元,(c)是单元宽度为栅极中心间距的8倍的填充单元。与图2所示的标准单元C2一样,在图4(a)~(c)所示的填充单元中都设有虚设焊盘50和虚设栅极布线60。在图2中,填充单元即标准单元C2的单元宽度为栅极中心间距的2倍,但也可以按照逻辑单元间的空闲区的大小,布置如图4所示的单元宽度不同的填充单元。
(填充单元的变形例1)
图5是俯视图,示出图2所示的版图结构的变形例。在图5中,布置有结构不同的标准单元C2A作为填充单元,以此来代替图2的标准单元C2。在图5中,对与图2相同的构成要素标注与图2相同的符号,在此有时省略其详细说明。
在标准单元C2A中,在P型半导体区PA设有虚设焊盘51、52,在N型半导体区NA设有虚设焊盘53、54。此处,虚设焊盘51、52、53、54分别在Y方向上分开形成且分别形成有四个。与焊盘21、22、23同样,P型杂质注入至虚设焊盘51、52,与焊盘24、25、26同样,N型杂质注入至虚设焊盘53、54。在虚设焊盘51、53与虚设焊盘52、54之间,布置有沿Y方向延伸的虚设栅极布线61,在与标准单元C1相反一侧的侧边上布置有沿Y方向延伸的虚设栅极布线65。
在标准单元C2A中,在虚设焊盘51与虚设焊盘52之间,设有沿X方向延伸且并排设置的多条纳米线71,在虚设焊盘53与虚设焊盘54之间,设有沿X方向延伸且并排设置的多条纳米线72。此处,纳米线71、72分别沿Y方向并排设有四条,分别沿纵向即与衬底垂直的方向设有两条,故纳米线71、72分别合计为八条。纳米线71、72呈圆柱状,且在衬底上沿着水平方向延伸,即平行于衬底延伸,且例如由硅形成。纳米线71、72在Y方向上的布置中心间距等于标准单元C1的纳米线11、12、13、14在Y方向上的布置中心间距。纳米线71在Y方向上的布置位置与标准单元C1的纳米线11、12相同,纳米线72在Y方向上的布置位置与标准单元C1的纳米线13、14相同。
需要说明的是,纳米线71、72的条数不限于八条,还可以是与标准单元C1的纳米线11、12、13、14不同的条数。纳米线71、72在Y方向上的布置中心间距和布置位置也可以与标准单元C1的纳米线11、12、13、14不同。
(填充单元的变形例2)
图6是俯视图,示出图2所示的版图结构的变形例。在图6中,布置有结构不同的标准单元C2B作为填充单元,以此来代替图2的标准单元C2。对与图2相同的构成要素标注与图2相同的符号,此处有时省略其详细说明。
在标准单元C2B中,在P型半导体区PA设有虚设焊盘51、52,在N型半导体区NA设有虚设焊盘53、54。此处,虚设焊盘51、52、53、54分别在Y方向上分开形成且分别形成有四个。与焊盘21、22、23同样,P型杂质注入至虚设焊盘51、52,与焊盘24、25、26同样,N型杂质注入至虚设焊盘53、54。在虚设焊盘51、53与虚设焊盘52、54之间,布置有沿Y方向延伸的虚设栅极布线61,在与标准单元C1相反一侧的侧边上布置有沿Y方向延伸的虚设栅极布线65。
在标准单元C2B中,在虚设焊盘51与虚设焊盘52之间,设有沿X方向延伸且并排设置的多条纳米线71,在虚设焊盘53与虚设焊盘54之间,设有沿X方向延伸且并排设置的多条纳米线72。并且,在标准单元C2B中,在虚设栅极布线36与虚设焊盘51之间,设有沿X方向延伸且并排设置的多条纳米线73,在虚设栅极布线65与虚设焊盘52之间,设有沿X方向延伸且并排设置的多条纳米线74,在虚设焊盘53与虚设栅极布线36之间,设有沿X方向延伸且并排设置的多条纳米线75,在虚设焊盘54与虚设栅极布线65之间,设有沿X方向延伸且并排设置的多条纳米线76。此处,纳米线71、72、73、74、75、76分别沿Y方向并排设有四条,且分别沿纵向即与衬底垂直的方向设有两条,故纳米线71、72、73、74、75、76分别合计为八条。纳米线71、72、73、74、75、76呈圆柱状,且在衬底上沿着水平方向延伸,即平行于衬底延伸,且例如由硅形成。纳米线71、72、73、74、75、76在Y方向上的布置中心间距等于标准单元C1的纳米线11、12、13、14在Y方向上的布置中心间距。纳米线71、73、74在Y方向上的布置位置与标准单元C1的纳米线11、12相同,纳米线72、75、76在Y方向上的布置位置与标准单元C1的纳米线13、14相同。
需要说明的是,纳米线71、72、73、74、75、76的条数不限于八条,还可以是与标准单元C1的纳米线11、12、13、14不同的条数。纳米线71、72、73、74、75、76在Y方向上的布置中心间距和布置位置也可以与标准单元C1的纳米线11、12、13、14不同。
在图5所示的标准单元C2A和图6所示的标准单元C2B中,也可以与图4相同,设置单元宽度不同的单元。
(单元列末端单元的结构)
图7是图1的W2部分的放大图,是示出本实施方式的单元末端单元的版图结构的俯视图。在图7中,对与图2相同的构成要素标注与图2相同的符号,此处有时省略其详细说明。在图7中,标准单元C1具有纳米线FET,且具有逻辑功能(此处为2输入NOR)。标准单元C1的结构与图2的标准单元C1相同。
标准单元C3是不具有逻辑功能的单元末端单元,其在X方向上与标准单元C1相邻布置。通过布置标准单元C3,能够使N阱区NW沿X方向充分地扩散开。这样一来,就能够使标准单元C1的晶体管(纳米线FET)远离阱区端部,避免阱区端部附近的晶体管特性的变动。
与图2的标准单元C2一样,在标准单元C3中设有虚设焊盘50和虚设栅极布线60。此处,虚设焊盘50分别在Y方向上分开形成且分别形成有四个。虚设焊盘50和标准单元C3的焊盘21、22、23、24、25、26以同一中心间距Pp布置在X方向上。虚设栅极布线60与标准单元C3的栅极布线31、32和虚设栅极布线35、36以同一中心间距Pg布置在X方向上。标准单元C3的单元宽度是栅极中心间距Pg的4倍即(Pg×4)。
通过在单元末端单元中设置虚设焊盘,就能够得到与在填充单元中设置虚设焊盘时同样的作用和效果。即,包括虚设焊盘的焊盘的布置会变得规律,因此能够抑制半导体集成电路装置的制造偏差,并能够提高成品率。并且,因为能够使离逻辑单元的单元端部最近的焊盘与相邻的焊盘之间的距离保持规定值,所以纳米线FET的性能的估算精度会得到提高。
需要说明的是,在图7的结构中,使标准单元C3的单元宽度为栅极中心间距Pg的4倍。不过,单元末端单元的单元宽度不限于此,还可以与图4所示的填充单元的变形例相同,布置各种单元宽度的单元末端单元。此外,在图7的结构中,将单元末端单元布置在单元列CR的附图右侧的端部,但还可以将相同的单元末端单元布置在附图左侧的端部。
与上述填充单元的变形例相同,也可以将变形例应用于单元末端单元。例如还可以如图5的标准单元C2A那样,在虚设焊盘之间设置沿X方向延伸的纳米线。也可以像图6的标准单元C2B那样,在设在单元端部的虚设栅极布线与和它相邻的虚设焊盘之间设置沿X方向延伸的纳米线。
(采用了虚设焊盘的电容单元)
还可以将上述虚设焊盘的电位固定在电源电位上。这样一来,就能避免虚设焊盘进入电位浮动状态,能够使电路动作更加稳定。此外,还可以将P型半导体区的虚设焊盘固定在VDD,将N型半导体区的虚设焊盘固定在VSS。这样一来,因为虚设焊盘间会产生电容,所以具有该虚设焊盘的填充单元和单元列末端单元就会作为电容单元即电源间去耦电容器发挥作用。因此,能够实现电源电压的稳定化。
图8是俯视图,示出采用了虚设焊盘的电容单元的版图结构。作为图8的一例,示出单元宽度为栅极中心间距的2倍的填充单元,例如代替图2所示的标准单元C2布置(图9~图12也一样)。在图8的结构中,设在P型半导体区PA的虚设焊盘50a经布线81a和局部布线85a与布线VDD相连接。此处,虚设焊盘50a分别在Y方向上分开形成且分别形成有四个。设在N型半导体区NA的虚设焊盘50b经布线81b和局部布线85b与布线VSS相连接。此处,虚设焊盘50b分别在Y方向上分开形成且分别形成有四个。即,作为第一虚设焊盘的虚设焊盘50a的电位固定在作为第一电源电位的VDD,作为第二虚设焊盘的虚设焊盘50b的电位固定在作为第二电源电位的VSS。这样一来,在虚设焊盘50a与虚设焊盘50b之间就会产生电容(图中以点划线示出),因此,图8的填充单元就会作为电容单元发挥作用。
图9示出采用了虚设焊盘的电容单元的其他结构例,(a)是示出版图结构的俯视图,(b)是(a)的A-A’线的剖视图。与图8的结构相同,在图9的结构中,设在P型半导体区PA的虚设焊盘50a经布线81a和局部布线85a与布线VDD相连接,设在N型半导体区NA的虚设焊盘50b经线81b和局部布线85b与布线VSS相连接。而且,虚设栅极布线91经布线81c和局部布线85c与虚设焊盘50b相连接。即,在两个虚设焊盘50a之间沿Y方向延伸的虚设栅极布线91的电位固定在VSS。
利用上述结构,在虚设焊盘50a与虚设栅极布线91之间就会产生电容(在图9(b)中以点划线作出图示)。因此,能够实现具有比图8的结构更大的电容值的电容单元。与夹着栅极氧化膜的电容相比,虚设焊盘50a与虚设栅极布线91之间的电容的耐压性优异。
图10是俯视图,示出采用了虚设焊盘的电容单元的版图结构的其他例子。与图8的结构相同,在图10的结构中,设在P型半导体区PA的虚设焊盘50a经布线81a和局部布线85a与布线VDD相连接,设在N型半导体区NA的虚设焊盘50b经线81b和局部布线85b与布线VSS相连接。而且,在图10的结构中,布置有虚设栅极布线91a、91b,虚设栅极布线91a、91b布置在沿Y方向延伸的同一直线上,并且在P型半导体区PA和N型半导体区NA分开。虚设栅极布线91a经布线81d和局部布线85d与虚设焊盘50b相连接。即,作为第一虚设栅极布线的虚设栅极布线91a的电位固定在VSS。另一方面,虚设栅极布线91b经布线81e和局部布线85e与虚设焊盘50a相连接。即,作为第二虚设栅极布线的虚设栅极布线91b的电位固定在VDD。需要说明的是,虚设栅极布线91a、91b也可以不布置在同一直线上。
利用上述结构,在虚设焊盘50a与虚设栅极布线91a之间就会产生电容,在虚设焊盘50b与虚设栅极布线91b之间也会产生电容。即,分别在P型半导体区PA和N型半导体区NA,构成耐压性优异的较大电容。因此,能够实现具有比图9的结构更大的电容值的电容单元。
图11示出采用了虚设焊盘的电容单元的其他结构例,(a)是示出版图结构的俯视图,(b)是(a)的A-A’线的剖视图。不过,为了便于观看,图11(b)中放大了图示。与图9的结构相同,在图11的结构中,设在P型半导体区PA的虚设焊盘50a经布线81a和局部布线85a与布线VDD相连接,设在N型半导体区NA的虚设焊盘50b经线81b和局部布线85b与布线VSS相连接。在虚设焊盘50a之间,设有沿X方向并排延伸的多条纳米线92。此处,纳米线92分别沿Y方向并排设有三条,分别沿纵向即与衬底垂直的方向设有两条,故纳米线92合计为六条。沿Y方向延伸的栅极布线93被设为,隔着栅极绝缘膜94将纳米线92的周围围起来。栅极布线93经布线81c和局部布线85c与虚设焊盘50b相连接。即,栅极布线93的电位固定在VSS。
利用上述结构,在虚设焊盘50a与栅极布线93之间以及纳米线92与栅极布线93之间就会产生电容(在图11(b)中以点划线作出图示)。因此,能够实现具有比图9的结构更大的电容值的电容单元。需要说明的是,在图11的结构中,纳米线92的条数为6条,但不限于此。
也可以为,在如图10所示那样栅极布线在P型半导体区PA和N型半导体区NA分开的结构中,在虚设焊盘50a彼此之间和虚设焊盘50b彼此之间分别设置纳米线。这样一来,就分别在P型半导体区PA和N型半导体区NA,构成夹着栅极绝缘膜的电容。
图12示出采用了虚设焊盘的电容单元的其他结构例。在图12中,(a)示出在图9的结构中省略局部布线85b的结构,(b)示出在图11的结构中省略局部布线85b的结构。在图9和图11的结构中,在N型半导体区NA,虚设焊盘50b、虚设栅极布线91和栅极布线93的电位都固定在VSS,因此没有构成电容。因此,如图12所示,可以省略将虚设焊盘50b与布线51b连接起来的局部布线85b。
需要说明的是,在图8~图12中,以单元宽度为栅极中心间距的2倍的填充单元为例图示出电容单元的结构,但对于具有虚设焊盘的单元列末端单元,也能够同样地构成电容单元。对于具有其他单元宽度的填充单元和单元列末端单元,也可以同样地构成电容单元。
图13示出将图12的结构的单元宽度扩大后的变形例。在图13中,(a)是将图12(a)的结构的单元宽度扩大到栅极中心间距的6倍后的结构,(b)是将图12(b)的结构的单元宽度扩大到栅极中心间距的6倍后的结构。
需要说明的是,在以上说明中,纳米线呈圆柱状,但纳米线的形状并不限于此。例如,纳米线的剖面形状还可以是椭圆形、扁圆形,纳米线呈四棱柱状等棱柱状也无妨。
在以上说明中,在纳米线FET中,相对于沿Y方向设置的多条纳米线而言,焊盘是分开形成的。不过,还存在如下的情况,即,相对于沿Y方向设置的多条纳米线而言,焊盘形成为一体。图14是图2中的版图结构的变形例。在图14中,相对于沿Y方向分别设置有四条的纳米线11、12、13、14而言,焊盘21、22、23、24、25、26分别形成为一体。虚设焊盘51、52、53、54也分别形成为一体。
在以上说明中,在标准单元中,焊盘的宽度、焊盘间距全部相同,但并不限于此。例如,标准单元还可以具有宽度不同的焊盘,焊盘间距不同也无妨。在该情况下,也是只要焊盘以同一中心间距布置好,就能够实现焊盘有规律地排列着的布置图案。而且,在P型半导体区和N型半导体区,焊盘的位置在X方向上不一致也无妨。不过,优选一致。
在以上说明中,栅极布线的中心间距与焊盘的中心间距相等,但并不限于此。而且,将栅极布线设为在整个P型半导体区和N型半导体区沿Y方向直线状延伸,但并不限于此。
-产业实用性-
本公开对采用了纳米线FET的半导体集成电路装置提供对制造的容易化有效的版图结构,故本公开对于提高半导体集成电路装置的性能很有用。
-符号说明—
5 虚设焊盘
11、12、13、14 纳米线
21、22、23、24、25、26 焊盘
36 虚设栅极布线
50 虚设焊盘
50a 虚设焊盘(第一虚设焊盘)
50b 虚设焊盘(第二虚设焊盘)
51、52、53、54 虚设焊盘
65 虚设栅极布线
71、72、73、74、75、76 纳米线
91、93 虚设栅极布线
91a 虚设栅极布线(第一虚设栅极布线)
91b 虚设栅极布线(第二虚设栅极布线)
92 纳米线
93 栅极布线
C 标准单元
C1 第一标准单元
C2、C2A、C2B 第二标准单元
CFL 填充单元
CEC 单元列末端单元
P11、P12、N11、N12 纳米线FET
Claims (12)
1.一种半导体集成电路装置,其特征在于,具有第一标准单元和第二标准单元,
所述第一标准单元具有纳米线FET(Field Effect Transistor,场效应晶体管)且具有逻辑功能,
所述第二标准单元在第一方向上与所述第一标准单元相邻布置且不具有逻辑功能,
所述纳米线FET具有:
沿所述第一方向延伸的一条或并排设置的多条纳米线;以及
一对焊盘,一对所述焊盘分别设在所述纳米线的所述第一方向上的两端,且下表面位于比所述纳米线的下表面低的位置上,并与所述纳米线相连,
所述第二标准单元具有虚设焊盘,所述虚设焊盘为对电路的逻辑功能不做贡献的焊盘。
2.根据权利要求1所述的半导体集成电路装置,其特征在于,
所述虚设焊盘的在所述第一方向上的尺寸即焊盘宽度、在与所述第一方向垂直的第二方向上的尺寸即焊盘高度和所述第二方向上的布置位置中的至少任一者与所述焊盘相同。
3.根据权利要求1所述的半导体集成电路装置,其特征在于,
所述虚设焊盘和所述焊盘以同一中心间距布置在所述第一方向上。
4.根据权利要求1所述的半导体集成电路装置,其特征在于,
所述虚设焊盘包括并排布置在所述第一方向上的第一虚设焊盘和第二虚设焊盘,
所述第二标准单元具有设在所述第一虚设焊盘与所述第二虚设焊盘之间且沿所述第一方向延伸的一条或并排设置的多条纳米线。
5.根据权利要求1所述的半导体集成电路装置,其特征在于,
所述第二标准单元具有:
布置在所述第一方向上的单元端部的虚设栅极布线;以及
设在所述虚设焊盘与所述虚设栅极布线之间且沿所述第一方向延伸的一条或并排设置的多条纳米线。
6.根据权利要求1所述的半导体集成电路装置,其特征在于,
所述第一标准单元和所述第二标准单元被施加第一电源电位和第二电源电位,
所述虚设焊盘包括被施加所述第一电源电位的第一虚设焊盘。
7.根据权利要求6所述的半导体集成电路装置,其特征在于,
所述第一虚设焊盘包括并排设在所述第一方向上的两个虚设焊盘,
所述第二标准单元具有虚设栅极布线,所述虚设栅极布线在两个所述虚设焊盘之间沿与所述第一方向垂直的第二方向延伸,
所述虚设栅极布线被施加所述第二电源电位。
8.根据权利要求6所述的半导体集成电路装置,其特征在于,
所述第一虚设焊盘包括并排设在所述第一方向上的两个虚设焊盘,
所述第二标准单元具有:
设在两个所述虚设焊盘之间且沿所述第一方向延伸的一条或并排设置的多条第二纳米线;以及
沿与所述第一方向垂直的第二方向延伸且被设为在所述第二纳米线的所述第一方向上的规定范围内包围所述第二纳米线的周围的栅极布线,
所述栅极布线被施加所述第二电源电位。
9.根据权利要求6所述的半导体集成电路装置,其特征在于,
所述虚设焊盘包括被施加所述第二电源电位的第二虚设焊盘。
10.根据权利要求9所述的半导体集成电路装置,其特征在于,
所述第一虚设焊盘包括并排设在所述第一方向上的两个虚设焊盘,
所述第二虚设焊盘包括并排设在所述第一方向上的两个虚设焊盘,
所述第二标准单元具有:
在所述第一虚设焊盘所包括的两个所述虚设焊盘之间沿与所述第一方向垂直的第二方向延伸的第一虚设栅极布线;以及
在所述第二虚设焊盘所包括的两个所述虚设焊盘之间沿所述第二方向延伸的第二虚设栅极布线,
所述第一虚设栅极布线被施加所述第二电源电位,
所述第二虚设栅极布线被施加所述第一电源电位。
11.根据权利要求10所述的半导体集成电路装置,其特征在于,
所述第一虚设栅极布线和所述第二虚设栅极布线布置在沿所述第二方向延伸的同一直线上。
12.根据权利要求1到11中任一项权利要求所述的半导体集成电路装置,其特征在于,
所述第二标准单元是填充单元或单元列末端单元。
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US10354947B2 (en) | 2017-02-06 | 2019-07-16 | Samsung Electronics Co., Ltd. | Integrated circuit including standard cell |
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